HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6107 -gerrit commit 7c57f294ad01ce028263bcc853dbd50a93a9abdf Author: Elyes HAOUAS <ehaouas@noos.fr> Date: Wed Jun 25 20:58:05 2014 +0200 Add new board NEC 945G-M4 Change-Id: Iaea13e51658d1729a31414938b7a70252b10723a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> --- SerialICE/Kconfig | 114 ++++++++++++++++++++------------------ SerialICE/mainboard/nec_945g-m4.c | 95 +++++++++++++++++++++++++++++++ 2 files changed, 154 insertions(+), 55 deletions(-) diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig index 1a3a78c..4a38902 100644 --- a/SerialICE/Kconfig +++ b/SerialICE/Kconfig @@ -33,38 +33,30 @@ config BOARD_QEMU_X86 config BOARD_AMD_SERENGETI_CHEETAH bool "AMD Serengeti Cheetah (SimNOW)" -config BOARD_ASUS_P2_M3A3200 - bool "ASUS Pundit P2-M3A3200" - -config BOARD_KONTRON_986LCD_M - bool "Kontron 986LCD-M/mITX" - -config BOARD_RODA_RK886EX - bool "Roda RK886EX" - -config BOARD_INTEL_D945GCLF - bool "Intel D945GCLF" +config BOARD_AOPEN_DXPL_PLUS + bool "AOpen DXPL Plus" -config BOARD_INTEL_D945GNT - bool "Intel D945GNT" +config BOARD_ASROCK_775I65G + bool "ASRock 775i65G" -config BOARD_INTEL_D946GZIS - bool "Intel D946GZIS" +config BOARD_ASROCK_939A785GMH + bool "ASRock 939A785GMH" + select BUILD_XMMSTACK -config BOARD_DELL_S1850 - bool "Dell PowerEdge S1850" +config BOARD_ASROCK_P4I65GV + bool "ASRock P4i65GV" config BOARD_ASUS_F2A85_M bool "ASUS F2A85-M" select BUILD_XMMSTACK -config BOARD_ASUS_M2V_MX_SE - bool "ASUS M2V-MX SE" +config BOARD_ASUS_K8V_X + bool "ASUS K8V-X" select VIA_ROMSTRAP select BUILD_XMMSTACK -config BOARD_ASUS_K8V_X - bool "ASUS K8V-X" +config BOARD_ASUS_M2V_MX_SE + bool "ASUS M2V-MX SE" select VIA_ROMSTRAP select BUILD_XMMSTACK @@ -72,28 +64,64 @@ config BOARD_ASUS_M4A77TD_PRO bool "ASUS M4A77TD-PRO" select BUILD_XMMSTACK -config BOARD_ASROCK_939A785GMH - bool "ASRock 939A785GMH" +config BOARD_ASUS_P2_M3A3200 + bool "ASUS Pundit P2-M3A3200" + +config BOARD_ASUS_P2B + bool "ASUS P2B" + +config BOARD_ASUS_P4P800_VM + bool "ASUS P4P800-VM" + +config BOARD_COMMELL_LV_672 + bool "Commell LV-672" + +config BOARD_DELL_S1850 + bool "Dell PowerEdge S1850" + +config BOARD_HP_DL165_G6 + bool "HP DL165 G6" + +config BOARD_INTEL_D845GBV2 + bool "Intel D845GBV2" + +config BOARD_INTEL_D945GCLF + bool "Intel D945GCLF" + +config BOARD_INTEL_D945GNT + bool "Intel D945GNT" + +config BOARD_INTEL_D946GZIS + bool "Intel D946GZIS" + +config BOARD_JETWAY_NF81_T56N_LF + bool "Jetway NF81-T56N-LF" select BUILD_XMMSTACK +config BOARD_KONTRON_986LCD_M + bool "Kontron 986LCD-M/mITX" + config BOARD_MSI_MS6178 bool "MSI MS6178" config BOARD_MSI_MS7133 bool "MSI MS-7133" +config BOARD_NEC_945G_M4 + bool "NEC 945g-m4" + config BOARD_RCA_RM4100 bool "RCA RM4100" -config BOARD_THOMSON_IP1000 - bool "Thomson IP1000" - -config BOARD_ASUS_P2B - bool "ASUS P2B" +config BOARD_RODA_RK886EX + bool "Roda RK886EX" config BOARD_TELEVIDEO_TC7010 bool "Televideo TC7010" +config BOARD_THOMSON_IP1000 + bool "Thomson IP1000" + config BOARD_TYAN_S2892 bool "Tyan S2892" select CK804_ROMSTRAP @@ -106,36 +134,11 @@ config BOARD_TYAN_S2912 bool "Tyan S2912" select MCP55_ROMSTRAP -config BOARD_HP_DL165_G6 - bool "HP DL165 G6" - -config BOARD_WYSE_S50 - bool "WYSE S50" - -config BOARD_ASROCK_P4I65GV - bool "ASRock P4i65GV" - -config BOARD_ASUS_P4P800_VM - bool "ASUS P4P800-VM" - -config BOARD_AOPEN_DXPL_PLUS - bool "AOpen DXPL Plus" - config BOARD_VIA_EPIA_M850 bool "VIA EPIA M850" -config BOARD_INTEL_D845GBV2 - bool "Intel D845GBV2" - -config BOARD_ASROCK_775I65G - bool "ASRock 775i65G" - -config BOARD_COMMELL_LV_672 - bool "Commell LV-672" - -config BOARD_JETWAY_NF81_T56N_LF - bool "Jetway NF81-T56N-LF" - select BUILD_XMMSTACK +config BOARD_WYSE_S50 + bool "WYSE S50" endchoice @@ -172,6 +175,7 @@ config BOARD_INIT default "asrock_775i65g.c" if BOARD_ASROCK_775I65G default "commell_lv_672.c" if BOARD_COMMELL_LV_672 default "jetway_nf81_t56n_lf.c" if BOARD_JETWAY_NF81_T56N_LF + default "nec_945g-m4.c" if BOARD_NEC_945G_M4 config SOUTHBRIDGE_INIT string diff --git a/SerialICE/mainboard/nec_945g-m4.c b/SerialICE/mainboard/nec_945g-m4.c new file mode 100644 index 0000000..35889b7 --- /dev/null +++ b/SerialICE/mainboard/nec_945g-m4.c @@ -0,0 +1,95 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include "config.h" + +const char boardname[33]="945G M4 "; + +/* Hardware specific functions */ + +#define RCBA 0xfed1c000 +#define GCS 0x3410 +#define RCBA32(x) *((volatile u32 *)(RCBA + x)) + +static void southbridge_init(void) +{ + u16 reg16; + u32 reg32; + + // Set up RCBA + pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1); + +#if defined(CONFIG_POST_LPC) + // port80 writes go to LPC: + reg32 = RCBA32(GCS); + reg32 = reg32 & ~0x04; + RCBA32(GCS) = reg32; + outb(0x23, 0x80); +#endif + + // Enable Serial IRQ + pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x64), 0xd0); + // Set COM1 decode range + pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x80), 0x0010); + // Enable COM1 + pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x82), 0x340f); + // Enable SIO PM Events at 0x680 + pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x84), 0x00fc0a01); + + // Disable watchdog +#define PMBASE 0x500 +#define TCOBASE (PMBASE + 0x60) + pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x40), PMBASE | 1); + pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x44), 0x80); + reg16 = inw(TCOBASE + 0x08); + reg16 |= (1 << 11); + outw(reg16, TCOBASE + 0x08); + outw(0x0008, TCOBASE + 0x04); + outw(0x0002, TCOBASE + 0x06); +} + +static void superio_init(u8 cfg_port, u8 com_port, u8 pm) +{ + pnp_enter_ext_func_mode_alt(cfg_port); + + pnp_set_logical_device(cfg_port, com_port); + pnp_set_enable(cfg_port, 0); + pnp_set_iobase0(cfg_port, 0x3f8); + pnp_set_irq0(cfg_port, 4); + pnp_set_enable(cfg_port, 1); + + if (pm != 0) { + pnp_set_logical_device(cfg_port, pm); + pnp_set_enable(cfg_port, 0); + pnp_set_iobase0(cfg_port, 0x680); + pnp_set_irq0(cfg_port, 3); + pnp_set_enable(cfg_port, 1); + } + + pnp_exit_ext_func_mode(cfg_port); +} + +static void chipset_init(void) +{ + southbridge_init(); + superio_init(0x2e, 3, 4); + +} +