April 2012 - SerialICE - mail.coreboot.org

Patch set updated for serialice: 241fbef Add SIMBA: simulator for simple buses
by Kyösti Mälkki April 23, 2012

April 23, 2012

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/865 -gerrit commit 241fbef2bbe42fc96204b7da819046cd701359fb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Apr 23 15:55:25 2012 +0300 Add SIMBA: simulator for simple buses With simba library, I/O and memory accesses to defined regions can be handled in a simulated state machine on the host computer. There is no need to recompile Qemu, as simple state machines can be implemented within this librarys sources. An Intel 82801 (ICH4) SMBus host controller state machine is implemented as a functional example. At the moment it only parses the transactions. Change-Id: Ia19067aebc81450fc98ff57f01921b11fec4eecb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- SerialICE/patches/lua-5.1.4-shared.diff | 43 +++ SerialICE/simba/i82801dx.lua | 37 ++- SerialICE/util/simba/COPYING | 339 +++++++++++++++++++++ SerialICE/util/simba/Makefile | 35 +++ SerialICE/util/simba/README | 57 ++++ SerialICE/util/simba/config.h | 11 + SerialICE/util/simba/i2c-i801.h | 152 ++++++++++ SerialICE/util/simba/i82801_sim.c | 490 +++++++++++++++++++++++++++++++ SerialICE/util/simba/io_hooks.c | 167 +++++++++++ SerialICE/util/simba/io_hooks.h | 6 + SerialICE/util/simba/main.c | 155 ++++++++++ SerialICE/util/simba/simba.c | 121 ++++++++ SerialICE/util/simba/simba.h | 132 +++++++++ SerialICE/util/simba/simba_lua.c | 62 ++++ 14 files changed, 1795 insertions(+), 12 deletions(-) diff --git a/SerialICE/patches/lua-5.1.4-shared.diff b/SerialICE/patches/lua-5.1.4-shared.diff new file mode 100644 index 0000000..9371edd --- /dev/null +++ b/SerialICE/patches/lua-5.1.4-shared.diff @@ -0,0 +1,43 @@ +diff -ur lua-5.1.4/Makefile lua-5.1.4-patched/Makefile +--- lua-5.1.4/Makefile 2008-08-12 03:40:48.000000000 +0300 ++++ lua-5.1.4-patched/Makefile 2012-04-05 12:49:40.868289537 +0300 +@@ -43,7 +43,7 @@ + # What to install. + TO_BIN= lua luac + TO_INC= lua.h luaconf.h lualib.h lauxlib.h ../etc/lua.hpp +-TO_LIB= liblua.a ++TO_LIB= liblua.a liblua.so + TO_MAN= lua.1 luac.1 + + # Lua version and release. +diff -ur lua-5.1.4/src/Makefile lua-5.1.4-patched/src/Makefile +--- lua-5.1.4/src/Makefile 2012-04-05 20:49:22.636290315 +0300 ++++ lua-5.1.4-patched/src/Makefile 2012-04-05 12:44:28.684293164 +0300 +@@ -23,6 +23,8 @@ + PLATS= aix ansi bsd freebsd generic linux macosx mingw posix solaris + + LUA_A= liblua.a ++LUA_SO= liblua.so ++ + CORE_O= lapi.o lcode.o ldebug.o ldo.o ldump.o lfunc.o lgc.o llex.o lmem.o \ + lobject.o lopcodes.o lparser.o lstate.o lstring.o ltable.o ltm.o \ + lundump.o lvm.o lzio.o +@@ -36,7 +38,7 @@ + LUAC_O= luac.o print.o + + ALL_O= $(CORE_O) $(LIB_O) $(LUA_O) $(LUAC_O) +-ALL_T= $(LUA_A) $(LUA_T) $(LUAC_T) ++ALL_T= $(LUA_A) $(LUA_T) $(LUAC_T) $(LUA_SO) + ALL_A= $(LUA_A) + + default: $(PLAT) +@@ -51,6 +53,9 @@ + $(AR) $@ $? + $(RANLIB) $@ + ++$(LUA_SO): $(CORE_O) $(LIB_O) ++ $(CC) -o $@ -shared $? ++ + $(LUA_T): $(LUA_O) $(LUA_A) + $(CC) -o $@ $(MYLDFLAGS) $(LUA_O) $(LUA_A) $(LIBS) + diff --git a/SerialICE/simba/i82801dx.lua b/SerialICE/simba/i82801dx.lua index ec19c79..1615ba0 100644 --- a/SerialICE/simba/i82801dx.lua +++ b/SerialICE/simba/i82801dx.lua @@ -14,48 +14,61 @@ function lpc_decode_write(port, size, data, filter) end end -function lpc_decode_hook(bdfr, size, data) - printf("got LPC %08x %d %08x\n", bdfr, size, data); -end - -add_pci_cfg_hook(pci_bdf(0x0,0x1f,0x0,0xe4), 4, lpc_decode_hook) -add_pci_cfg_hook(pci_bdf(0x0,0x1f,0x0,0xe6), 2, lpc_decode_hook) - +prepend_to_list(io_write_hooks, lpc_decode_write) -- ********************************************************** -- -- SMBus controller handling +smbus_host_hooked = false smbus_host_base = 0 smbus_host_size = 0 +require("package") + +simba_init, err, str = package.loadlib("./libsimba.so", "luaopen_simba") +if (simba_init) then + simba_init() + printf("SerialICE: SIMBA initialized\n") +else + printf("SerialICE: %s : %s\n", err, str) +end + function smbus_io_write_log(port, size, data, target) if port >= smbus_host_base and port < smbus_host_base+smbus_host_size then - return not log_smbus_io + smbus_host.write_log(port, size, data, target) + return true end end function smbus_io_read_log(port, size, data, target) if port >= smbus_host_base and port < smbus_host_base+smbus_host_size then - return not log_smbus_io + smbus_host.read_log(port, size, data, target) + return true end end function smbus_bar_setup(base, size) - smbus_host_base = base + smbus_host_base = bit.band(base, bit.bnot(size-1)) smbus_host_size = size printf("SMBus BAR set up: 0x%08x\n", smbus_host_base) - if decode_smbus then + if simba then + simba.smbus_init(smbus_host_base, smbus_host_size) + end + if (not smbus_host_hooked) and decode_smbus and smbus_host then + smbus_host_hooked = true + printf("SIMBA: SMBus decode enabled\n") + smbus_host.show_io(log_smbus_io and 1 or 0) prepend_to_list(io_write_log_hooks, smbus_io_write_log) prepend_to_list(io_read_log_hooks, smbus_io_read_log) end end function smbus_bar_hook(bdfr, size, data) - smbus_bar_setup(bit.band(data, 0x10000-0x20), 0x20) + smbus_bar_setup(data, 0x20) end add_pci_cfg_hook(pci_bdf(0x0,0x1f,0x3,0x20), 2, smbus_bar_hook) diff --git a/SerialICE/util/simba/COPYING b/SerialICE/util/simba/COPYING new file mode 100644 index 0000000..d511905 --- /dev/null +++ b/SerialICE/util/simba/COPYING @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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If this is what you want to do, use the GNU Lesser General +Public License instead of this License. diff --git a/SerialICE/util/simba/Makefile b/SerialICE/util/simba/Makefile new file mode 100644 index 0000000..54e27ef --- /dev/null +++ b/SerialICE/util/simba/Makefile @@ -0,0 +1,35 @@ +## +## Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +CFLAGS += +LDFLAGS += -L$(cwd) -ldl -llua -lm + +cwd = $(shell pwd) + +drivers := i82801_sim.c i2c-i801.h +simba_src := simba.c simba.h simba_lua.c $(drivers) + +default: dump_smbus libsimba.so + +dump_smbus : main.c io_hooks.c io_hooks.h $(simba_src) + gcc $(CFLAGS) $(LDFLAGS) -o $@ $^ + +libsimba.so : $(simba_src) + gcc $(CFLAGS) -fPIC -shared -o $@ $^ + +clean: + -rm dump_smbus libsimba.so diff --git a/SerialICE/util/simba/README b/SerialICE/util/simba/README new file mode 100644 index 0000000..bcaa0f9 --- /dev/null +++ b/SerialICE/util/simba/README @@ -0,0 +1,57 @@ + +Serialice SMBus Host Controller simulator + +Not much here yet, but might already mostly work with many +Intel 82801 southbridges (aka ICHxx). There is a list of +PCI IDs in the i2c-i801.c file which have some chance. + +The common byte/word/block SMBus reads and writes have gone +through some testing. Process calls and i2c block variants +are not yet tested. + +NOTE: The "xx" in output means the byte was transferred on the +SMBus but firmware never read it out of the controller buffer. +On writes such bytes are to be considered as "no change". + +*** Build instructions + + $ make + +*** Command-line operation + +Input file is log output from serialice, stdout has +the smbus traffic translated into a more readable form. + + $ ./dump_smbus -h + +Parse SMBus access from SerialICE logfile +dump_smbus [-dhx] -f filename + -f file input serialice logfile + -d strips SMBus inb/outb + -x strips all but SMBus IO + + $ ./dump_smbus -f qemu_serialice_log.txt > filtered.log + $ diff -y -W 200 qemu_serialice_log.txt filtered.log + +Things one may want to change in config.h + + SMBUS_PCIFUNC : PCI function with SMBus BAR + SMBUS_BAR : PCI config register for SMBus BAR + +If BAR autodetect fails, set DEFAULT_SMBUS_HOST_BASE. + + +*** SerialICE runtime translation + +Copy libsimba.so into the same directory with serialice modular +lua scripts. Simulator library should load automatically, check +for keywords "SIMBA and SMBUS" in the log. The "log_smbus_io" +boolean set in serialice.lua controls whether to show individual +inb/outb to smbus host controller. + +It may be necessary to compile qemu to use a shared lua library +to be able to load libsimba.so. + + +Kyösti Mälkki +<kyosti.malkki(a)gmail.com> diff --git a/SerialICE/util/simba/config.h b/SerialICE/util/simba/config.h new file mode 100644 index 0000000..6475598 --- /dev/null +++ b/SerialICE/util/simba/config.h @@ -0,0 +1,11 @@ + + +/* Change these to match your ICH southbridge PCI function. */ + +#define SMBUS_PCIFUNC "0:1f.3" +#define SMBUS_BAR 0x20 + +#define DEFAULT_SMBUS_HOST_BASE 0x400 +#define SMBUS_HOST_SIZE 0x20 + + diff --git a/SerialICE/util/simba/i2c-i801.h b/SerialICE/util/simba/i2c-i801.h new file mode 100644 index 0000000..aaf15a0 --- /dev/null +++ b/SerialICE/util/simba/i2c-i801.h @@ -0,0 +1,152 @@ +/* + i2c-i801.c - Part of lm_sensors, Linux kernel modules for hardware + monitoring + Copyright (c) 1998 - 2002 Frodo Looijaard <frodol(a)dds.nl>, + Philip Edelbrock <phil(a)netroedge.com>, and Mark D. Studebaker + <mdsxyz123(a)yahoo.com> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +/* + SUPPORTED DEVICES PCI ID + 82801AA 2413 + 82801AB 2423 + 82801BA 2443 + 82801CA/CAM 2483 + 82801DB 24C3 (HW PEC supported, 32 byte buffer not supported) + 82801EB 24D3 (HW PEC supported, 32 byte buffer not supported) + 6300ESB 25A4 ("") + ICH6 266A ("") + ICH7 27DA ("") + ESB2 269B ("") + ICH8 283E ("") + ICH9 2930 ("") + Tolapai 5032 ("") + ICH10 3A30 ("") + ICH10 3A60 ("") + + This driver supports several versions of Intel's I/O Controller Hubs (ICH). + For SMBus support, they are similar to the PIIX4 and are part + of Intel's '810' and other chipsets. + See the doc/busses/i2c-i801 file for details. + I2C Block Read not supported. + Block Process Call are not supported. +*/ + + +/* 82801CA is undefined before kernel 2.4.13 */ +#ifndef PCI_DEVICE_ID_INTEL_82801CA_3 +#define PCI_DEVICE_ID_INTEL_82801CA_3 0x2483 +#endif + +/* 82801DB is undefined before kernel 2.4.19 */ +#ifndef PCI_DEVICE_ID_INTEL_82801DB_3 +#define PCI_DEVICE_ID_INTEL_82801DB_3 0x24c3 +#endif + +/* 82801EB is undefined before kernel 2.4.21 */ +#ifndef PCI_DEVICE_ID_INTEL_82801EB_3 +#define PCI_DEVICE_ID_INTEL_82801EB_3 0x24d3 +#endif + +/* ESB is undefined before kernel 2.4.22 */ +#ifndef PCI_DEVICE_ID_INTEL_ESB_4 +#define PCI_DEVICE_ID_INTEL_ESB_4 0x25a4 +#endif + +/* ESB2 - Enterprise Southbridge is undefined */ +#ifndef PCI_DEVICE_ID_INTEL_ESB2_17 +#define PCI_DEVICE_ID_INTEL_ESB2_17 0x269b +#endif + +/* ICH6 is undefined */ +#ifndef PCI_DEVICE_ID_INTEL_ICH6_16 +#define PCI_DEVICE_ID_INTEL_ICH6_16 0x266a +#endif + +/* ICH7 is undefined */ +#ifndef PCI_DEVICE_ID_INTEL_ICH7_17 +#define PCI_DEVICE_ID_INTEL_ICH7_17 0x27da +#endif + +/* ICH8 is undefined */ +#ifndef PCI_DEVICE_ID_INTEL_ICH8_5 +#define PCI_DEVICE_ID_INTEL_ICH8_5 0x283e +#endif + +/* ICH9 is undefined */ +#ifndef PCI_DEVICE_ID_INTEL_ICH9_6 +#define PCI_DEVICE_ID_INTEL_ICH9_6 0x2930 +#endif + +#ifndef PCI_DEVICE_ID_INTEL_TOLAPAI_1 +#define PCI_DEVICE_ID_INTEL_TOLAPAI_1 0x5032 +#endif + +#ifndef PCI_DEVICE_ID_INTEL_ICH10_4 +#define PCI_DEVICE_ID_INTEL_ICH10_4 0x3a30 +#endif + +#ifndef PCI_DEVICE_ID_INTEL_ICH10_5 +#define PCI_DEVICE_ID_INTEL_ICH10_5 0x3a60 +#endif + +#ifdef I2C_CLIENT_PEC +#define HAVE_PEC +#endif + +/* I801 SMBus address offsets */ +#define SMBHSTSTS (0 + i801_smba) +#define SMBHSTCNT (2 + i801_smba) +#define SMBHSTCMD (3 + i801_smba) +#define SMBHSTADD (4 + i801_smba) +#define SMBHSTDAT0 (5 + i801_smba) +#define SMBHSTDAT1 (6 + i801_smba) +#define SMBBLKDAT (7 + i801_smba) +#define SMBPEC (8 + i801_smba) /* ICH4 only */ +#define SMBAUXSTS (12 + i801_smba) /* ICH4 only */ +#define SMBAUXCTL (13 + i801_smba) /* ICH4 only */ + +/* PCI Address Constants */ +#define SMBBA 0x020 +#define SMBHSTCFG 0x040 +#define SMBREV 0x008 + +/* Host configuration bits for SMBHSTCFG */ +#define SMBHSTCFG_HST_EN 1 +#define SMBHSTCFG_SMB_SMI_EN 2 +#define SMBHSTCFG_I2C_EN 4 + +/* Other settings */ +#define MAX_TIMEOUT 100 +#define ENABLE_INT9 0 /* set to 0x01 to enable - untested */ + +/* I801 command constants */ +#define I801_QUICK 0x00 +#define I801_BYTE 0x04 +#define I801_BYTE_DATA 0x08 +#define I801_WORD_DATA 0x0C +#define I801_PROC_CALL 0x10 /* later chips only, unimplemented */ +#define I801_BLOCK_DATA 0x14 +#define I801_I2C_BLOCK_DATA 0x18 /* unimplemented */ +#define I801_BLOCK_LAST 0x34 +#define I801_I2C_BLOCK_LAST 0x38 /* unimplemented */ +#define I801_START 0x40 +#define I801_PEC_EN 0x80 /* ich4 and later */ + + + + diff --git a/SerialICE/util/simba/i82801_sim.c b/SerialICE/util/simba/i82801_sim.c new file mode 100644 index 0000000..b28e9ad --- /dev/null +++ b/SerialICE/util/simba/i82801_sim.c @@ -0,0 +1,490 @@ +/* + * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdio.h> + +/* Intel 82801 SMBus Controller defines from linux src. */ +#include "i2c-i801.h" + +/* complement i2c-i801.c */ +#define i801_smba 0 +#define I801_BLOCK_PROCESS 0x1c + +#include "simba.h" + +static struct smbus_ctrl i801_smbus_controller; +static struct smbus_ctrl *host = &i801_smbus_controller; + +static unsigned int smbus_host_base = 0; +static unsigned int smbus_host_size = 0; +static int show_smbus_io = 1; + +static int passive_mode = 1; + +/* test for !passive_mode */ +void smbus_transaction(struct smbus_ctrl *host) +{ + int i; + unsigned char smb_cmd = (host->control & 0x1c); + + if (smb_is_read(host)) { + for (i=0; i<host->data0; i++) { + host->block_sram[i].hw = 0x80 + i; + host->block_sram[i].hw_valid = 1; + } + } + /* Finish all */ + host->status &= ~0x01; + host->status |= 0x02; +} + +static int smbus_completed(void); + + +static void smbus_state_switch(smb_state_t new_state) +{ + unsigned char smb_cmd = (host->control & 0x1c); + int i; + + if (new_state == host->state) { + dprintf("SMBus: state switch without switch\n"); + return; + } + + switch (new_state) { + case HOST_NOOP: + dprintf("SMBus: state switch to HOST_NOOP\n"); + new_state = HOST_IDLE_0; + break; + + case HOST_IDLE_0: + break; + + case HOST_ACTIVE_0: + /* INUSE_STS is set on SMBHSTSTS read */ + host->status = 0x0; + break; + + case HOST_ACTIVE_1: + { + host->status |= 0x01; + host->wr_data0 = host->data0; + host->wr_data1 = host->data1; + if (smb_is_read(host)) { + host->data0_valid = 0; + host->data1_valid = 0; + } + for (i=0; i<MAX_BLOCK_SRAM; i++) { + /* On block writes, previously read data in buffer is also valid. */ + if (host->block_sram[i].tmp_valid) { + host->block_sram[i].hw = host->block_sram[i].tmp; + host->block_sram[i].tmp_valid = 0; + host->block_sram[i].hw_valid = 1; + } + /* On block reads, no data in buffer is yet valid. */ + if (smb_is_read(host) && smb_cmd == I801_BLOCK_DATA) + host->block_sram[i].hw_valid = 0; + } + break; + } + + case HOST_DONE_0: + if (!smbus_completed()) + host->next_state = HOST_WAIT_0; + else + host->next_state = HOST_DONE_1; + break; + + case HOST_DONE_2: + host->next_state = host->state_completion; + break; + + case HOST_FAIL_0: + host->next_state = HOST_ACTIVE_0; + break; + + default: + break; + } + + host->new_state = new_state; +} + +static void smbus_state_run(void) +{ + smb_state_t next_state; + + while (host->state != host->new_state) { + dprintf("SMBus: state change %s -> %s\n", + ctrl_state[host->state], ctrl_state[host->new_state]); + host->state = host->new_state; + + switch (host->state) { + case HOST_DONE_1: + case HOST_DONE_2: + case HOST_FAIL_0: + smbus_dump_transaction(host); + break; + } + + next_state = host->next_state; + host->next_state = HOST_NOOP; + if (next_state != HOST_NOOP) + smbus_state_switch(next_state); + } +} + +static int smbus_completed(void) +{ + int complete = 0; + + if (!smb_is_read(host)) + return 1; + + switch (get_cmdcode(host)) { + + case SMBUS_QUICK: + complete = 1; + break; + + case SMBUS_BYTE: + complete = host->data0_valid; + break; + + case SMBUS_BYTE_DATA: + complete = host->data0_valid; + break; + + case SMBUS_WORD_DATA: + complete = host->data0_valid && host->data1_valid; + break; + + case SMBUS_BLOCK_DATA: + complete = host->data0_valid && (host->block_ptr >= host->data0); + break; + + case SMBUS_PROC_CALL: + case SMBUS_I2C_BLOCK_DATA: + case SMBUS_BLOCK_PROCESS: + default: + printf("SMBus (cmd_%02x): Unimplemented completion\n", host->smb_cmd); + break; + + } + return complete; +} + +static void smbus_signal_status(unsigned char data, unsigned char io_write) +{ + int reset_inuse = (data & 0x40); + int reset_intr = (data & 0x02); + +#if 0 + if (reset_inuse && (host->state != HOST_DONE_1)) + dprintf("SMBus: Premature reset of bit INUSE_STS\n"); +#endif + + switch (host->state) { + + case HOST_DONE_1: + if (reset_inuse && reset_intr) + smbus_state_switch(HOST_IDLE_0); + else if (reset_intr) + smbus_state_switch(HOST_ACTIVE_0); + break; + + case HOST_WAIT_0: + if (reset_inuse && reset_intr) { + host->state_completion = HOST_IDLE_0; + smbus_state_switch(HOST_WAIT_1); + } else if (reset_intr) { + host->state_completion = HOST_ACTIVE_0; + smbus_state_switch(HOST_WAIT_1); + } + break; + + case HOST_WAIT_1: + if (reset_intr) + smbus_state_switch(HOST_DONE_2); + break; + + default: + break; + } + +} + +static void smbus_signal_start(void) +{ + switch (host->state) { + case HOST_IDLE_0: + case HOST_ACTIVE_0: + smbus_state_switch(HOST_ACTIVE_1); + break; + + default: + printf("SMBus: Starting from illegal state\n"); + break; + } + + switch (host->control & 0x1c) { + + case I801_QUICK: + set_cmdcode(host, SMBUS_QUICK); + break; + + case I801_BYTE: + set_cmdcode(host, SMBUS_BYTE); + break; + + case I801_BYTE_DATA: + set_cmdcode(host, SMBUS_BYTE_DATA); + break; + + case I801_WORD_DATA: + set_cmdcode(host, SMBUS_WORD_DATA); + break; + + case I801_PROC_CALL: + set_cmdcode(host, SMBUS_PROC_CALL); + break; + + case I801_BLOCK_DATA: + set_cmdcode(host, SMBUS_BLOCK_DATA); + break; + + case I801_I2C_BLOCK_DATA: + set_cmdcode(host, SMBUS_I2C_BLOCK_DATA); + break; + + case I801_BLOCK_PROCESS: + set_cmdcode(host, SMBUS_BLOCK_PROCESS); + break; + + default: + printf("SMBus: Unknown controlcode\n"); + break; + } + +} + +/* + * + */ +static void smbus_host_status(unsigned char * data, unsigned char io_write) +{ + if (!io_write) { + if (passive_mode) + host->status = *data; + + switch (host->state) { + + case HOST_IDLE_0: + if (! (host->status & 0x40)) + smbus_state_switch(HOST_ACTIVE_0); + break; + + case HOST_ACTIVE_1: + if ((!host->status & 0x02) && (!passive_mode)) + smbus_transaction(host); + if (host->status & 0x1c) + smbus_state_switch(HOST_FAIL_0); + else if ((host->status & 0x02) && !(host->status & 0x01)) + smbus_state_switch(HOST_DONE_0); + break; + } + + if (!passive_mode) { + *data = host->status; + host->status |= 0x40; + } + } else { + if (!passive_mode) + host->status &= ~(*data); + + smbus_signal_status(*data, io_write); + } + +} + + +static void smbus_host_control(unsigned char * data, unsigned char io_write) +{ + if (!io_write) { + host->block_ptr=0; + if (!passive_mode) + *data = host->control & ~0x40; + } else { + host->control = *data; + if (host->control & 0x80) + printf("SMBus: No PEC simulation\n"); + if (host->control & 0x40) + smbus_signal_start(); + } +} + + +static void smbus_block_data(unsigned char * data, unsigned char io_write) +{ + if (passive_mode) { + if (host->block_ptr < MAX_BLOCK_SRAM) { + if (!io_write) { + host->block_sram[host->block_ptr].hw = *data; + host->block_sram[host->block_ptr].hw_valid = 1; + } + host->block_sram[host->block_ptr].tmp = *data; + host->block_sram[host->block_ptr].tmp_valid = 1; + } + } else { + if (host->block_ptr < MAX_BLOCK_SRAM) { + if (io_write) { + host->block_sram[host->block_ptr].tmp = *data; + host->block_sram[host->block_ptr].tmp_valid = 1; + } else { + *data = 0xff; + if (host->block_sram[host->block_ptr].tmp_valid) + *data = host->block_sram[host->block_ptr].tmp; + else if (host->block_sram[host->block_ptr].hw_valid) + *data = host->block_sram[host->block_ptr].hw; + } + } + } + host->block_ptr++; +} + + + +static void i82801_smbus_pre_io(unsigned char reg, unsigned char data, unsigned char io_write) +{ + switch (host->state) { + case HOST_WAIT_1: + /* Restarting previous transaction. */ + if (io_write && reg == SMBHSTCNT && data & 0x40) + smbus_state_switch(HOST_DONE_2); + + /* Programming new transaction. */ + if (io_write && reg >= SMBHSTCMD && reg <= SMBHSTDAT1) + smbus_state_switch(HOST_DONE_2); + + /* FIXME: Killing on-going transaction. */ + if (io_write && reg == SMBHSTCNT && data & 0x02) + smbus_state_switch(HOST_DONE_2); + break; + } + smbus_state_run(); +} + +static void i82801_smbus_post_io(unsigned char reg, unsigned char data, unsigned char io_write) +{ + switch (host->state) { + case HOST_WAIT_1: + if (smbus_completed()) + smbus_state_switch(HOST_DONE_2); + break; + } + smbus_state_run(); +} + +static void i82801_smbus_io(unsigned char reg, unsigned char * data, unsigned char io_write) +{ + /* In passive mode, data registers update both ways. */ + int data_write = io_write || passive_mode; + + switch (reg) { + + case SMBHSTSTS: + smbus_host_status(data, io_write); + break; + + case SMBHSTCNT: + smbus_host_control(data, io_write); + break; + + case SMBHSTCMD: + if (data_write) + host->command = *data; + else + *data = host->command; + break; + + case SMBHSTADD: + if (data_write) + host->slave = *data; + else + *data = host->slave; + break; + + case SMBHSTDAT0: + if (data_write) + host->data0 = *data; + else + *data = host->data0; + host->data0_valid = 1; + break; + + case SMBHSTDAT1: + if (data_write) + host->data1 = *data; + else + *data = host->data1; + host->data1_valid = 1; + break; + + case SMBBLKDAT: + smbus_block_data(data, io_write); + break; + + case SMBAUXCTL: + if (data_write) + host->aux_ctl = *data; + else + *data = host->aux_ctl; + break; + + default: + printf("SMBus: Unknown register 0x%02x\n", reg); + break; + } + smbus_state_run(); +} + +int serialice_smbus_io_access(unsigned int addr, unsigned int data, int io_write, int len) +{ + unsigned char reg = addr & (host->size - 1); + unsigned char cdata = data; + + i82801_smbus_pre_io(reg, data, io_write); + i82801_smbus_io(reg, (unsigned char*)&data, io_write); + if (show_smbus_io) + smbus_dump_io(io_write, addr, cdata, data); + i82801_smbus_post_io(reg, data, io_write); + return 0; +} + +void serialice_smbus_show_io(int show_io) +{ + show_smbus_io = !!show_io; +} + +void serialice_smbus_init(unsigned int base, unsigned int size) +{ + host->base = base & ~(size-1); + host->size = size; + dprintf("SMBus: base=0x%08x size=%04x\n", host->base, host->size); + smbus_state_switch(HOST_IDLE_0); +} + diff --git a/SerialICE/util/simba/io_hooks.c b/SerialICE/util/simba/io_hooks.c new file mode 100644 index 0000000..4823ae0 --- /dev/null +++ b/SerialICE/util/simba/io_hooks.c @@ -0,0 +1,167 @@ +/* + * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdio.h> +#include <stdlib.h> +#include <libio.h> +#include <string.h> +#include <unistd.h> + +#include "simba.h" +#include "io_hooks.h" +#include "config.h" + +static unsigned int smbus_host_base = 0; +static unsigned int smbus_host_size = 0; + +union cfg_io_register { + unsigned char r8[4]; + unsigned short r16[2]; + unsigned int r32; +}; + +typedef struct { + union cfg_io_register valid; + union cfg_io_register data; +} pci_config_reg; + +#define PCI_V23_SPACE 0x40 + +typedef struct { + char pcifunc[10]; + pci_config_reg map[PCI_V23_SPACE]; +} pci_config_space; + +pci_config_space tmpdev; + +pci_config_space sb_lpc = { + .pcifunc = SMBUS_PCIFUNC, +// .parser = sb_lpc_parser, +}; + +static pci_config_space * pci_cfg_get_bdf(char *newfunc) +{ + int i; + + if (strncmp(tmpdev.pcifunc, newfunc, sizeof(tmpdev.pcifunc))==0) + return &tmpdev; + + if (strncmp(sb_lpc.pcifunc, newfunc, sizeof(sb_lpc.pcifunc))==0) + return &sb_lpc; + + strncpy(tmpdev.pcifunc, newfunc, sizeof(tmpdev.pcifunc)); + + for (i=0; i<PCI_V23_SPACE; i++) + tmpdev.map[i].valid.r32=0; + return &tmpdev; +} + +static void pci_cfg_reg_update(pci_config_space *cfg, unsigned int reg, char len, unsigned int data) +{ + if ((reg>>2) >= PCI_V23_SPACE) + return; + + unsigned char ireg = reg & 0x03; + union cfg_io_register * rvalid = &(cfg->map[reg>>2].valid); + union cfg_io_register * rdata = &(cfg->map[reg>>2].data); + + switch (len) { + case 8: + rvalid->r8[ireg] |= 0xff; + rdata->r8[ireg] = data & 0xff; + break; + case 16: + if (ireg & 0x01) + dprintf("PCI: Bad alignment for word at %04x\n", reg); + ireg &= 0x2; + rvalid->r16[ireg] |= 0xffff; + rdata->r16[ireg] = data & 0xffff; + break; + case 32: + if (ireg & 0x03) + dprintf("PCI: Bad alignment for long at %04x\n", reg); + rvalid->r32 = 0xffffffff; + rdata->r32 = data; + break; + default: + break; + } +} + +static void pci_cfg_update(pci_config_space *cfg, unsigned int reg, unsigned int data, char io_write, char len) +{ + int vid=0, did=0; + const char *prefix[2] = {"PCI", "SubSystem" }; + pci_config_reg *pci_id; + + pci_cfg_reg_update(cfg, reg, len, data); + + if ((reg>=0x0 && reg<0x4) || (reg>=0x2c && reg<0x30)) + { + int subsys = reg>4; + pci_id = &cfg->map[reg>>2]; + vid = pci_id->valid.r8[0] && pci_id->valid.r8[1] && (pci_id->data.r16[0]!=0xffff); + did = pci_id->valid.r8[2] && pci_id->valid.r8[3] && (pci_id->data.r16[1]!=0xffff); + + if (vid && did) + dprintf("PCI_trigger: %s Vendor:Device ID = %04x:%04x\n", prefix[subsys], pci_id->data.r16[0], pci_id->data.r16[1]); + else if (vid) + dprintf("PCI_trigger: %s Vendor ID = %04x\n", prefix[subsys], pci_id->data.r16[0]); + else if (did) + dprintf("PCI_trigger: %s Device ID = %04x\n", prefix[subsys], pci_id->data.r16[1]); + } + + /* Catch SMBus Host BAR */ + if (cfg == &sb_lpc && reg>=SMBUS_BAR && reg<SMBUS_BAR+3) { + union cfg_io_register * rvalid = &cfg->map[reg>>2].valid; + union cfg_io_register * rdata = &cfg->map[reg>>2].data; + if (rvalid->r8[0] && rvalid->r8[1]) { + smbus_host_base = rdata->r16[0] & ~(SMBUS_HOST_SIZE-1); + smbus_host_size = SMBUS_HOST_SIZE; + serialice_smbus_init(smbus_host_base, smbus_host_size); + } + } +} + +int handle_pci(char *pcifunc, unsigned int reg, unsigned int data, char io_write, char len) +{ + int done=0; + + pci_config_space * cfg = pci_cfg_get_bdf(pcifunc); + pci_cfg_update(cfg, reg, data, io_write, len); + + return 0; +} + +int handle_io(unsigned int addr, unsigned int data, char io_write, int len) +{ + int done=0; + if ((addr >= smbus_host_base) && (addr < (smbus_host_base + smbus_host_size))) { + serialice_smbus_io_access(addr, data, io_write, len); + done = 1; + } + return done; +} + +void smbus_defaults_init(int smbus_show_io) +{ + smbus_host_base = DEFAULT_SMBUS_HOST_BASE; + smbus_host_size = SMBUS_HOST_SIZE; + serialice_smbus_init(smbus_host_base, smbus_host_size); + serialice_smbus_show_io(smbus_show_io); +} + diff --git a/SerialICE/util/simba/io_hooks.h b/SerialICE/util/simba/io_hooks.h new file mode 100644 index 0000000..e21ebd2 --- /dev/null +++ b/SerialICE/util/simba/io_hooks.h @@ -0,0 +1,6 @@ + + +void smbus_defaults_init(int show_smbus_io); + +int handle_pci(char *pcifunc, unsigned int reg, unsigned int data, char io_write, char len); +int handle_io(unsigned int addr, unsigned int data, char io_write, int len); diff --git a/SerialICE/util/simba/main.c b/SerialICE/util/simba/main.c new file mode 100644 index 0000000..b8cd8f4 --- /dev/null +++ b/SerialICE/util/simba/main.c @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdio.h> +#include <stdlib.h> +#include <libio.h> +#include <string.h> +#include <unistd.h> +#include <errno.h> + +#include "io_hooks.h" + +/* serialice log parser */ +static char line[80]; +static char s_cmd[3]=""; +static char s_pcidev[10]=""; +static char s_addr[]="0x00000000"; +static char s_data[]="0x00000000"; +static char s_reg[]="0x00"; + +static int try_parse_io(const char * line) +{ + unsigned int addr, data; + int valid=0, len=0; + + valid = sscanf(line, "IO: %*4s %8s %2s %8s", &s_addr[2], &s_cmd[0], &s_data[2]) == 3; + if (!valid) + return 0; + + valid &= (sscanf(s_addr, "%x", &addr)==1); + valid &= (sscanf(s_data, "%x", &data)==1); + len = 4 * (strlen(s_data) - 2); + + if (valid && strcmp("=>", s_cmd)==0) + valid = handle_io(addr, data, 0, len); + else if (valid && strcmp("<=", s_cmd)==0) + valid = handle_io(addr, data, 1, len); + + return valid; +} + +static int try_parse_pci(const char * line) +{ + unsigned int addr, data, reg; + int valid=0, len=0; + + valid = sscanf(line, "PCI %6s R.%2s %2s %8s", &s_pcidev[0], &s_reg[2], &s_cmd[0], &s_data[2]) == 4; + if (!valid) + return 0; + + valid &= (sscanf(s_reg, "%x", &reg)==1); + valid &= (sscanf(s_data, "%x", &data)==1); + len = 4 * (strlen(s_data) - 2); + if (valid && strcmp("=>", s_cmd)==0) + valid = handle_pci(s_pcidev, reg, data, 0, len); + else if (valid && strcmp("<=", s_cmd)==0) + valid = handle_pci(s_pcidev, reg, data, 1, len); + + return valid; +} + + +void usage(void) +{ + printf( "Parse SMBus access from SerialICE logfile\n" + "dump_smbus [-dhx] -f filename\n" + "\t-f file input serialice logfile\n" + "\t-d strips SMBus inb/outb\n" + "\t-x strips all but SMBus IO\n"); +} + +int main(int argc, char *argv[]) +{ + char * filename = NULL; + int show_smbus_only = 0; + int show_smbus_io = 1; + int c; + FILE *txtlog; + + while ((c = getopt (argc, argv, "df:hx")) != -1) { + switch (c) { + case 'd': + show_smbus_io = 0; + break; + case 'f': + filename = optarg; + break; + case 'h': + usage(); + exit(0); + break; + case 'x': + show_smbus_only = 1; + break; + case '?': + if (optopt == 'f') + fprintf (stderr, "Option -%c requires an argument.\n", optopt); + else if (isprint (optopt)) + fprintf (stderr, "Unknown option `-%c'.\n", optopt); + else + fprintf (stderr, "Unknown option character `\\x%x'.\n", optopt); + return 1; + default: + abort (); + } + } + + if (! filename) { + usage(); + exit(1); + } + + txtlog = fopen(filename, "r"); + if (! txtlog) { + printf("File %s : %s\n", filename, strerror(errno)); + exit(2); + } + + smbus_defaults_init(show_smbus_io); + + while (!feof(txtlog)) { + int done = 0, show = 0; + + fgets(line, sizeof(line), txtlog); + + if (!done) { + done = try_parse_io(line); + } + + if (!done) + done = try_parse_pci(line); + + if (!done && !show_smbus_only) + fputs(line, stdout); + continue; + } + + fclose(txtlog); + exit(0); +} + diff --git a/SerialICE/util/simba/simba.c b/SerialICE/util/simba/simba.c new file mode 100644 index 0000000..dcdea47 --- /dev/null +++ b/SerialICE/util/simba/simba.c @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdio.h> +#include <string.h> +#include "simba.h" + +void smbus_dump_block(struct smbus_ctrl *host) +{ + int i; + for (i=0; i<host->data0 && i<MAX_BLOCK_SRAM; i++) { + if (host->block_sram[i].hw_valid) + printf(" %02x", host->block_sram[i].hw); + else + printf(" xx"); + } +} + +void smbus_dump_io(unsigned char io_write, unsigned int reg, unsigned char pre_data, unsigned char post_data) +{ + const char *moded[2] = {" !!", "" }; + if (io_write) + printf("IO: outb %04x <= %02x%s\n", reg, post_data, + moded[pre_data==post_data]); + else + printf("IO: inb %04x => %02x%s\n", reg, post_data, + moded[pre_data==post_data]); +} + +void smbus_dump_transaction(struct smbus_ctrl *host) +{ + const char invalid[] = "xx"; + const char *iodir[2] = { "<=", "=>" }; + const char *dir = smb_is_read(host) ? iodir[1] : iodir[0]; + char data0[4], data1[4]; + int length; + + if (host->data0_valid) { + length = host->data0; + sprintf(data0, "%02x", host->data0); + } else { + length = 0; + strncpy(data0, invalid, sizeof(data0)); + } + + if (host->data1_valid) + sprintf(data1, "%02x", host->data1); + else + strncpy(data1, invalid, sizeof(data1)); + + printf("SMBus: 00:%02x proto=%02x ", smb_client(host), get_cmdcode(host)); + + if (host->state == HOST_FAIL_0) { + printf("Failed transaction (%s)\n", dir); + return; + } + + switch (get_cmdcode(host)) { + + case SMBUS_QUICK: + printf("\n"); + break; + + case SMBUS_BYTE: + printf("%02x %s %s\n", host->command, dir, data0); + break; + + case SMBUS_BYTE_DATA: + printf("%02x %s %s\n", host->command, dir, data0); + break; + + case SMBUS_WORD_DATA: + printf("%02x %s %s%s\n", host->command, dir, data0, data1); + break; + + case SMBUS_PROC_CALL: + printf("%02x %02x %02x %s %s %s\n", + host->command, host->wr_data0, host->wr_data1, + iodir[1], data0, data1); + break; + + case SMBUS_BLOCK_DATA: + printf("%02x len=%02d %s", host->command, length, dir); + smbus_dump_block(host); + printf("\n"); + break; + + case SMBUS_I2C_BLOCK_DATA: + printf("%02x %02x %02x len=%02d %s", + host->command, host->data0, host->data1, host->block_ptr, dir); + smbus_dump_block(host); + printf("\n"); + break; + + case SMBUS_BLOCK_PROCESS: + printf("%02x len=%02d %s", host->command, length, iodir[1]); + smbus_dump_block(host); + printf("\n"); + break; + + default: + printf("Cannot parse command\n"); + break; + } +} + + diff --git a/SerialICE/util/simba/simba.h b/SerialICE/util/simba/simba.h new file mode 100644 index 0000000..b048e10 --- /dev/null +++ b/SerialICE/util/simba/simba.h @@ -0,0 +1,132 @@ +/* + * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +/* Our SMBus Host Simulator states. */ +typedef enum { + HOST_NOOP, + HOST_IDLE_0, + HOST_ACTIVE_0, + HOST_ACTIVE_1, + HOST_DONE_0, + HOST_DONE_1, + HOST_DONE_2, + HOST_WAIT_0, + HOST_WAIT_1, + HOST_FAIL_0, +} smb_state_t; + +static const char *ctrl_state[] = { + "noop", + "idle_0", + "active_0", + "active_1", + "done_0", + "done_1", + "done_2", + "wait_0", + "wait_1", + "fail_0", +}; + +typedef enum { + SMBUS_NOOP, + SMBUS_QUICK, + SMBUS_BYTE, + SMBUS_BYTE_DATA, + SMBUS_WORD_DATA, + SMBUS_PROC_CALL, + SMBUS_BLOCK_DATA, + SMBUS_I2C_BLOCK_DATA, + SMBUS_BLOCK_PROCESS, +} smb_cmd_t; + + +#define MAX_BLOCK_SRAM 32 + + +struct sram_buf { + unsigned char hw; + unsigned char hw_valid; + unsigned char tmp; + unsigned char tmp_valid; +}; + +struct smbus_ctrl { + + /* IO region */ + unsigned int base; + unsigned int size; + + /* HW registers */ + unsigned char status; + unsigned char control; + unsigned char command; + unsigned char slave; + unsigned char data0; + unsigned char data1; + unsigned char aux_ctl; + + unsigned char data0_valid; + unsigned char data1_valid; + + /* for state machine */ + smb_state_t state; + smb_state_t new_state; + smb_state_t next_state; + smb_state_t state_completion; + smb_cmd_t smb_cmd; + + /* for E32B */ + unsigned char block_ptr; + unsigned char max_block_ptr; + struct sram_buf block_sram[MAX_BLOCK_SRAM]; + + /* for Process Call */ + unsigned char wr_data0; + unsigned char wr_data1; +}; + + +#if DEBUG +#define dprintf(x, ...) do { printf(x, ## __VA_ARGS__); } while (0) +#else +#define dprintf(x, ...) do { } while (0) +#endif + + +#define smb_is_read(x) (x->slave & 0x01) +#define smb_client(x) (x->slave >> 1) + +static inline void set_cmdcode(struct smbus_ctrl *host, int code) +{ + host->smb_cmd = (code<<1) | smb_is_read(host); +} + +static inline int get_cmdcode(struct smbus_ctrl *host) +{ + return (host->smb_cmd>>1); +} + +void smbus_dump_block(struct smbus_ctrl *host); +void smbus_dump_transaction(struct smbus_ctrl *host); +void smbus_dump_io(unsigned char io_write, unsigned int reg, unsigned char pre_data, unsigned char post_data); + +void serialice_smbus_init(unsigned int base, unsigned int size); +void serialice_smbus_show_io(int show_io); +int serialice_smbus_io_access(unsigned int addr, unsigned int data, int io_write, int len); + diff --git a/SerialICE/util/simba/simba_lua.c b/SerialICE/util/simba/simba_lua.c new file mode 100644 index 0000000..b31c1e1 --- /dev/null +++ b/SerialICE/util/simba/simba_lua.c @@ -0,0 +1,62 @@ + + +#include <lua.h> +#include <lauxlib.h> + +static int l_smbus_show_io(lua_State *L) +{ + int show_io = lua_tonumber(L, 1); + serialice_smbus_show_io(show_io); + return 0; +} + +static int l_smbus_read_log(lua_State *L) +{ + unsigned int addr = lua_tonumber(L, 1); + unsigned int size = lua_tonumber(L, 2); + unsigned int data = lua_tonumber(L, 3); + serialice_smbus_io_access(addr, data, 0, size); + return 0; +} + +static int l_smbus_write_log(lua_State *L) +{ + unsigned int addr = lua_tonumber(L, 1); + unsigned int size = lua_tonumber(L, 2); + unsigned int data = lua_tonumber(L, 3); + serialice_smbus_io_access(addr, data, 1, size); + return 0; +} + +static const struct luaL_reg smbus_hostsim_lib [] = { + {"show_io", l_smbus_show_io}, + {"read_log", l_smbus_read_log}, + {"write_log", l_smbus_write_log}, + {NULL, NULL} /* sentinel */ +}; + +static int l_smbus_init(lua_State *L) +{ + unsigned int base = lua_tonumber(L, 1); + unsigned int size = lua_tonumber(L, 2); + + serialice_smbus_init(base, size); + luaL_openlib(L, "smbus_host", smbus_hostsim_lib, 0); + return 1; +} + +/* + * + */ + +static const struct luaL_reg simba_lib [] = { + {"smbus_init", l_smbus_init}, + {NULL, NULL} /* sentinel */ +}; + +int luaopen_simba(lua_State *L) +{ + luaL_openlib(L, "simba", simba_lib, 0); + return 1; +} +

1 0

Patch set updated for serialice: a50001d Modularized SerialICE scripting
by Kyösti Mälkki April 23, 2012

April 23, 2012

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/860 -gerrit commit a50001d222b62ba64971184b84e8fda6b94dfae7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Apr 23 15:53:12 2012 +0300 Modularized SerialICE scripting This is script/serialice.lua split into separate files. It expects to find a match for the *mb command response and load a correct .lua file for that particular mainboard. There is a bit improved filter for PCI configuration registers, even when written in multiple parts. Good for catching BARs. There is some decoding of CMOS nvram and PnP cycles to SuperIO. Some filters for which I did not yet find proper location are in the file leftover.lua, some of these were vendor bios binary specific. As for the name simba/, it stands for simulated bus access. Plan is to modify these further and divert some SMBus traffic to qemu and not the real hw. One could then read SPD data from a local file. Change-Id: Idba1c3dc7e80ebf169ff277ab7918a1564822bfe Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- SerialICE/simba/aopen_dxpl_plus.lua | 96 ++++++++++++ SerialICE/simba/core_io.lua | 283 +++++++++++++++++++++++++++++++++++ SerialICE/simba/cpu.lua | 94 ++++++++++++ SerialICE/simba/i82801dx.lua | 109 ++++++++++++++ SerialICE/simba/leftover.lua | 135 +++++++++++++++++ SerialICE/simba/memory.lua | 239 +++++++++++++++++++++++++++++ SerialICE/simba/misc.lua | 198 ++++++++++++++++++++++++ SerialICE/simba/serialice.lua | 158 +++++++++++++++++++ SerialICE/simba/superio.lua | 235 +++++++++++++++++++++++++++++ 9 files changed, 1547 insertions(+), 0 deletions(-) diff --git a/SerialICE/simba/aopen_dxpl_plus.lua b/SerialICE/simba/aopen_dxpl_plus.lua new file mode 100644 index 0000000..e215e32 --- /dev/null +++ b/SerialICE/simba/aopen_dxpl_plus.lua @@ -0,0 +1,96 @@ + + +dofile("i82801dx.lua") + +-- ********************************************************** +-- + +function mainboard_io_read(port, size, data, filter) + -- KBD controller returns status=0xff, clear 0x02 + -- as I cannot modify data, fake timeout errors + if ( port == 0x64 and size == 1 ) then + filter.filter = true + filter.data = 0x60 + return true + end + + -- Timer loop + if ( port == 0x61 ) then + -- if ( regs.cs == 0x1000 and regs.eip == 0x1634 ) then + if ( regs.eip == 0x1634 ) then + printf("Skipping delay at %04x:%04x\n", regs.cs, regs.eip); + regs.ecx = 0x01 + return true, 0x20 + end + -- if ( regs.cs == 0x1000 and regs.eip == 0x163a ) then + if ( regs.eip == 0x163a ) then + printf("Skipping delay at %04x:%04x\n", regs.cs, regs.eip); + regs.ecx = 0x01 + return true, 0x30 + end + end + +end + + +function mainboard_io_write(port, size, data, filter) + + -- ********************************************************** + -- Not catching the end of RAM init is not problematic, except + -- that it makes decompression of the BIOS core to RAM incredibly + -- slow as the decompressor inner loop has to be fetched + -- permanently from the target (several reads/writes per + -- decompressed byte). + + if port == 0x80 and data == 0x2c and ram_is_initialized == false then + ram_is_initialized = true + -- Register low RAM 0x00000000 - 0x000dffff + SerialICE_register_physical(0x00000000, 0xa0000) + -- SMI/VGA memory should go to the target... + SerialICE_register_physical(0x000c0000, 0x20000) + printf("\nLow RAM accesses are now directed to Qemu.\n") + + return false, data + end + + if ( port == 0xed ) then + -- if ( regs.cs == 0x1000 and regs.eip == 0x1792 and regs.ecx == 0x0000fff0 ) then + if ( regs.eip == 0x1792 ) then + printf("Skipping IO delay... #2 \n") + regs.ecx = 0x01 + end + +if false then + -- SIPI delay + -- if ( regs.cs == 0xe000 and regs.eip == 0xb3bc and regs.ecx == 0x200) then + if ( regs.eip == 0xb3bc or regs.eip == 0xb3bf ) then + printf("Skipping IO delay... IPI #0\n") + regs.ecx = 0x01 + end + -- if ( regs.cs == 0xe000 and regs.eip == 0xb4af and regs.ecx == 0x200) then + if ( regs.eip == 0xb4ad or regs.eip == 0xb4af ) then + printf("Skipping IO delay... IPI #1\n") + regs.ecx = 0x01 + end +end + + return false, data + end + +end + +function mainboard_io_write_log(port, size, data, target) + if port == 0xed then + return true -- Ignore + end + if port == 0xcfb then + return true -- Ignore + end +end + + +prepend_to_list(io_read_hooks, mainboard_io_read) +prepend_to_list(io_write_hooks, mainboard_io_write) +prepend_to_list(io_write_log_hooks, mainboard_io_write_log) + + diff --git a/SerialICE/simba/core_io.lua b/SerialICE/simba/core_io.lua new file mode 100644 index 0000000..128b132 --- /dev/null +++ b/SerialICE/simba/core_io.lua @@ -0,0 +1,283 @@ + +-- ********************************************************** +-- +-- IO access + + +io_read_hooks = new_list() +io_write_hooks = new_list() +io_read_log_hooks = new_list() +io_write_log_hooks = new_list() + + +-- SerialICE_io_read_filter is the filter function for IO reads. +-- +-- Parameters: +-- port IO port to be read +-- data_size Size of the IO read +-- Return values: +-- caught True if the filter intercepted the read +-- data Value returned if the read was intercepted + +function SerialICE_io_read_filter(port, size) + local data = 0 + filter = { filter = false, data = data } + if walk_list(io_read_hooks, port, size, data, filter) then + return filter.filter, filter.data + end + + return false, data +end + +-- SerialICE_io_write_filter is the filter function for IO writes. +-- +-- Parameters: +-- port IO port to be written to +-- size Size of the IO write +-- data Data to be written to +-- Return values: +-- caught True if the filter intercepted the write +-- data Value returned if the write was *not* intercepted + +function SerialICE_io_write_filter(port, size, data) + filter = { filter = false, data = data } + if walk_list(io_write_hooks, port, size, data, filter) then + return filter.filter, filter.data + end + + return false, data +end + + +function SerialICE_io_write_log(port, size, data, target) + log_cs_ip() + if walk_list(io_write_log_hooks, port, size, data, target) then + return + end + + printf("IO: out%s %04x <= %s\n", size_suffix(size), port, size_data(size, data)) +end + +function SerialICE_io_read_log(port, size, data, target) + log_cs_ip() + if walk_list(io_read_log_hooks, port, size, data, target) then + return + end + + printf("IO: in%s %04x => %s\n", size_suffix(size), port, size_data(size, data)) +end + + + +-- ********************************************************** +-- +-- PCI IO config access + + +pci_cfg_hooks = new_list() + +function add_pci_cfg_hook(bdf, size, func) + value = { bdf = bdf, size = size, func = func } + prepend_to_list(pci_cfg_hooks, value) +end + +function is_pci_cfg_hooked(bdf) + local l = pci_cfg_hooks.list + while l do + if bdf == bit.band(l.value.bdf, bit.bnot(0x03)) then + return true + end + l = l.next + end + return false +end + +function call_pci_cfg_hook(bdf, size, data) + local l = pci_cfg_hooks.list + while l do + if l.value.bdf == bdf and l.value.size == size then + l.value.func(bdf, size, data) + end + l = l.next + end + return false +end + +function pci_bdf(bus, dev, func, reg) + return 0x80000000 + bus*65536 + dev*2048 + func*256 + reg +end + +-- Remember the PCI device selected via IO CF8 +SerialICE_pci_device = 0 + + +-- Catch partial PCI configuration register writes. +-- This synthesizes 32/16 bit wide access from separate +-- 16/8 bit accesses for pci_cfg_hooks. + +port_0cf8 = 0 +port_0cfc = 0 +bv = {} + +function port_0cf8_reset(data) + local port_0cf8_new = bit.band(data,bit.bnot(0x3)) + if not (port_0cf8 == port_0cf8_new) then + port_0cf8 = 0 + if (is_pci_cfg_hooked(port_0cf8_new)) then + port_0cf8 = port_0cf8_new + end + for i = 0, 3, 1 do bv[i] = false end + end +end + +function port_0cfc_access(port, size, data) + + local av = {} + + for i = 0, 3, 1 do av[i] = false end + + ll = 8 * (port%4) + if (size == 1) then + av[port%4] = true + bv[port%4] = true + amask = bit.lshift(0xff, ll) + omask = bit.lshift(data, ll) + port_0cfc = bit.band(port_0cfc, bit.bnot(amask)) + port_0cfc = bit.bor(port_0cfc, omask) + elseif (size == 2) then + av[port%4] = true + bv[port%4] = true + av[port%4+1] = true + bv[port%4+1] = true + amask = bit.lshift(0xffff, ll) + omask = bit.lshift(data, ll) + port_0cfc = bit.band(port_0cfc, bit.bnot(amask)) + port_0cfc = bit.bor(port_0cfc, omask) + elseif (size == 4) then + port_0cfc = data + for i = 0, 3, 1 do av[i] = true end + for i = 0, 3, 1 do bv[i] = true end + end + + for i = 0, 3, 1 do + if (bv[i] and av[i]) then + call_pci_cfg_hook(port_0cf8 + i, 1, + bit.band(0xff, bit.rshift(port_0cfc, i*8))) + end + end + if ((bv[0] and bv[1]) and (av[0] or av[1])) then + call_pci_cfg_hook(port_0cf8 + 0x00, 2, + bit.band(0xffff, bit.rshift(port_0cfc, 0))) + end + if (bv[2] and bv[3] and (av[2] or av[3])) then + call_pci_cfg_hook(port_0cf8 + 0x02, 2, + bit.band(0xffff, bit.rshift(port_0cfc, 16))) + end + if (bv[0] and bv[1] and bv[2] and bv[3]) then + call_pci_cfg_hook(port_0cf8, 4, port_0cfc) + end +end + + +function pci_io_cfg_write(port, size, data, filter) + if port == 0xcf8 then + port_0cf8_reset(data) + SerialICE_pci_device = data + return false + end + if port_0cf8 ~= 0 and port >= 0xcfc and port <= 0xcff then + port_0cfc_access(port, size, data) + end + return false +end + +-- not enabled +function pci_io_cfg_read(port, size, data, filter) + if port_0cf8 ~= 0 and port >= 0xcfc and port <= 0xcff then + port_0cfc_access(port, size, data) + end + return false +end + +function pci_io_cfg_write_log(port, size, data, target) + if port == 0xcf8 then + return not log_pci_io_cfg + end + if port >= 0xcfc and port <= 0xcff then + printf("PCI %x:%02x.%x R.%02x <= %s\n", + bit.band(0xff,bit.rshift(SerialICE_pci_device, 16)), + bit.band(0x1f,bit.rshift(SerialICE_pci_device, 11)), + bit.band(0x7,bit.rshift(SerialICE_pci_device, 8)), + bit.band(0xff,SerialICE_pci_device + (port - 0xcfc)), + size_data(size, data)) + return not log_pci_io_cfg + end +end + +function pci_io_cfg_read_log(port, size, data, target) + if port == 0xcf8 then + return not log_pci_io_cfg + end + if port >= 0xcfc and port <= 0xcff then + printf("PCI %x:%02x.%x R.%02x => %s\n", + bit.band(0xff,bit.rshift(SerialICE_pci_device, 16)), + bit.band(0x1f,bit.rshift(SerialICE_pci_device, 11)), + bit.band(0x7,bit.rshift(SerialICE_pci_device, 8)), + bit.band(0xff,SerialICE_pci_device + (port - 0xcfc)), + size_data(size, data)) + return not log_pci_io_cfg + end +end + +if decode_pci_io_cfg then + prepend_to_list(io_write_hooks, pci_io_cfg_write) +-- prepend_to_list(io_read_hooks, pci_io_cfg_read) + prepend_to_list(io_write_log_hooks, pci_io_cfg_write_log) + prepend_to_list(io_read_log_hooks, pci_io_cfg_read_log) +end + +-- ********************************************************** +-- +-- PCIe MM config access + +PCIe_bar = 0 +PCIe_size = 0 + +function pci_mm_cfg_read_log(addr, size, data, target) + if addr >= PCIe_bar and addr < (PCIe_bar + PCIe_size) then + printf("PCIe %x:%02x.%x R.%02x => %s\n", + bit.band(0xff,bit.rshift(addr, 20)), + bit.band(0x1f,bit.rshift(addr, 15)), + bit.band(0x7,bit.rshift(addr, 12)), + bit.band(0xfff,addr), + size_data(size, data)) + return not log_pci_mm_cfg + end +end + +function pci_mm_cfg_write_log(addr, size, data, target) + if addr >= PCIe_bar and addr < (PCIe_bar + PCIe_size) then + printf("PCIe %x:%02x.%x R.%02x <= %s\n", + bit.band(0xff,bit.rshift(addr, 20)), + bit.band(0x1f,bit.rshift(addr, 15)), + bit.band(0x7,bit.rshift(addr, 12)), + bit.band(0xfff,addr), + size_data(size, data)) + return not log_pci_mm_cfg + end +end + +function pcie_mm_cfg_bar(base, size) + + PCIe_bar = base + PCIe_size = size + printf("PCIe MM config BAR: 0x%08x\n", PCIe_bar) + + if decode_pci_mm_cfg then + --prepend_to_list(mem_write_hooks, pci_mm_cfg_write) + --prepend_to_list(mem_read_hooks, pci_mm_cfg_read) + prepend_to_list(mem_write_log_hooks, pci_mm_cfg_write_log) + prepend_to_list(mem_read_log_hooks, pci_mm_cfg_read_log) + end +end + diff --git a/SerialICE/simba/cpu.lua b/SerialICE/simba/cpu.lua new file mode 100644 index 0000000..760fb16 --- /dev/null +++ b/SerialICE/simba/cpu.lua @@ -0,0 +1,94 @@ + + +msr_read_log_hooks = new_list() +msr_write_log_hooks = new_list() + + +function var_mtrr_log_write(addr, hi, lo, filtered) + if addr >= 0x200 and addr < 0x210 then + if addr % 2 == 0 then + mt = lo % 0x100 + if mt == 0 then memtype = "Uncacheable" + elseif mt == 1 then memtype = "Write-Combine" + elseif mt == 4 then memtype = "Write-Through" + elseif mt == 5 then memtype = "Write-Protect" + elseif mt == 6 then memtype = "Write-Back" + else memtype = "Unknown" + end + printf("CPU: Set MTRR %x base to %08x.%08x (%s)\n", (addr - 0x200) / 2, hi, bit.band(lo, 0xffffff00), memtype) + else + if bit.band(lo, 0x800) == 0x800 then + valid = "valid" + else + valid = "disabled" + end + printf("CPU: Set MTRR %x mask to %08x.%08x (%s)\n", (addr - 0x200) / 2, hi, bit.band(lo, 0xfffff000), valid) + end + return true + end + return false +end + + + +function SerialICE_msr_read_filter(addr, hi, lo) + -- Intel CPU microcode revision check. + if addr == 0x8b then + -- fake microcode revision of my 0x6f6 Core 2 Duo Mobile + return true, 0xc7, 0x00 + end + + return false, hi, lo +end + +function SerialICE_msr_write_filter(addr, hi, lo) + -- Intel CPU microcode update + if addr == 0x79 then + return true, 0, 0xffff0000 + end + + return false, hi, lo +end + +function SerialICE_msr_write_log(addr, hi, lo, filtered) + log_cs_ip() + if not walk_list(msr_write_log_hooks, addr, hi, lo, filtered) then + printf("CPU: wrmsr %08x <= %08x.%08x\n", addr, hi, lo) + end +end + +function SerialICE_msr_read_log(addr, hi, lo, filtered) + log_cs_ip() + if not walk_list(msr_read_log_hooks, addr, hi, lo, filtered) then + printf("CPU: rdmsr %08x => %08x.%08x\n", addr, hi, lo) + end +end + + +prepend_to_list(msr_write_log_hooks, var_mtrr_log_write) + + +-- ********************************************************** +-- +-- CPUID instruction + +function SerialICE_cpuid_filter(in_eax, in_ecx, eax, ebx, ecx, edx) + -- Set number of cores to 1 on Core Duo and Atom to trick the + -- firmware into not trying to wake up non-BSP nodes. + if in_eax == 1 then + ebx = bit.band(0xff00ffff, ebx); + ebx = bit.bor(0x00010000, ebx); + return true, eax, ebx, ecx, edx + end + + -- return false, so the result is not filtered. + return false, eax, ebx, ecx, edx +end + + +function SerialICE_cpuid_log(in_eax, in_ecx, out_eax, out_ebx, out_ecx, out_edx, filtered) + log_cs_ip() + printf("CPU: CPUID eax: %08x; ecx: %08x => %08x.%08x.%08x.%08x\n", + in_eax, in_ecx, out_eax, out_ebx, out_ecx, out_edx) +end + diff --git a/SerialICE/simba/i82801dx.lua b/SerialICE/simba/i82801dx.lua new file mode 100644 index 0000000..ec19c79 --- /dev/null +++ b/SerialICE/simba/i82801dx.lua @@ -0,0 +1,109 @@ +-- ********************************************************** +-- +-- LPC decode ranges + +function lpc_decode_write(port, size, data, filter) + -- LPC decode registers + if SerialICE_pci_device == pci_bdf(0x0,0x1f,0x0,0xe4) then + if (port == 0xcfc and size == 4) or (port == 0xcfe) then + printf("LPC decode register 0:1f.0 R.e6 (filtered)\n") + filter.filter = true + filter.data = data + return true + end + end +end + +function lpc_decode_hook(bdfr, size, data) + printf("got LPC %08x %d %08x\n", bdfr, size, data); +end + +add_pci_cfg_hook(pci_bdf(0x0,0x1f,0x0,0xe4), 4, lpc_decode_hook) +add_pci_cfg_hook(pci_bdf(0x0,0x1f,0x0,0xe6), 2, lpc_decode_hook) + + +-- ********************************************************** +-- +-- SMBus controller handling + +smbus_host_base = 0 +smbus_host_size = 0 + +function smbus_io_write_log(port, size, data, target) + if port >= smbus_host_base and port < smbus_host_base+smbus_host_size then + return not log_smbus_io + end +end + +function smbus_io_read_log(port, size, data, target) + if port >= smbus_host_base and port < smbus_host_base+smbus_host_size then + return not log_smbus_io + end +end + + +function smbus_bar_setup(base, size) + + smbus_host_base = base + smbus_host_size = size + + printf("SMBus BAR set up: 0x%08x\n", smbus_host_base) + if decode_smbus then + prepend_to_list(io_write_log_hooks, smbus_io_write_log) + prepend_to_list(io_read_log_hooks, smbus_io_read_log) + end +end + +function smbus_bar_hook(bdfr, size, data) + smbus_bar_setup(bit.band(data, 0x10000-0x20), 0x20) +end + +add_pci_cfg_hook(pci_bdf(0x0,0x1f,0x3,0x20), 2, smbus_bar_hook) + + +-- ********************************************************** +-- + +function acpi_bar_hook(bdfr, size, data) + printf("ACPI BAR set up: 0x%08x\n", data) + printf("TCO BAR set up: 0x%08x\n", data + 0x60) + --acpi_bar_setup(bit.band(data, 0x10000-0x80), 0x80) +end + + +function gpio_bar_hook(bdfr, size, data) + printf("GPIO BAR set up: 0x%08x\n", data) + --gpio_bar_setup(bit.band(data, 0x10000-0x40), 0x40) +end + +add_pci_cfg_hook(pci_bdf(0x0,0x1f,0x0,0x40), 2, acpi_bar_hook) +add_pci_cfg_hook(pci_bdf(0x0,0x1f,0x0,0x58), 2, gpio_bar_hook) + + +-- ********************************************************** +-- +-- AC '97 controller handling + +function audio_nambar_hook(bdfr, size, data) + printf("AUDIO NAMBAR set up: 0x%08x\n", data) +end +function audio_nabmbar_hook(bdfr, size, data) + printf("AUDIO NABMBAR set up: 0x%08x\n", data) +end +function audio_mmbar_hook(bdfr, size, data) + printf("AUDIO MMBAR set up: 0x%08x\n", data) +end +function audio_mbbar_hook(bdfr, size, data) + printf("AUDIO MBBAR set up: 0x%08x\n", data) +end + +add_pci_cfg_hook(pci_bdf(0x0,0x1f,0x5,0x10), 2, audio_nambar_hook) +add_pci_cfg_hook(pci_bdf(0x0,0x1f,0x5,0x14), 2, audio_nabmbar_hook) +add_pci_cfg_hook(pci_bdf(0x0,0x1f,0x5,0x18), 4, audio_mmbar_hook) +add_pci_cfg_hook(pci_bdf(0x0,0x1f,0x5,0x1c), 4, audio_mbbar_hook) + + + + + + diff --git a/SerialICE/simba/leftover.lua b/SerialICE/simba/leftover.lua new file mode 100644 index 0000000..4624ffe --- /dev/null +++ b/SerialICE/simba/leftover.lua @@ -0,0 +1,135 @@ + + + -- ********************************************************** + -- + -- Dell 1850 BMC filter + + if port == 0xe8 then + -- lua lacks a switch statement + if data == 0x44656c6c then printf("BMC: Dell\n") + elseif data == 0x50726f74 then printf("BMC: Prot\n") + elseif data == 0x496e6974 then + printf("BMC: Init (filtered)\n") + return true, data + else + printf("BMC: unknown %08x\n", data) + end + return false, data + end + + -- ********************************************************** + -- + -- Phoenix BIOS reconfigures 0:1f.0 reg 0x80/0x82. + -- This effectively wipes out our communication channel + -- so we mut not allow it. + + if port == 0xcfc then + if SerialICE_pci_device == 0x8000f880 then + printf("LPC (filtered)\n") + return true, data + end + + return false, data + end + + + -- ********************************************************** + -- + -- Intel 82945 (reference BIOS) RAM switch + -- + + -- The RAM initialization code for the i945 used by AMI and + -- Phoenix uses the same POST codes. We use this to determine + -- when RAM init is done on that chipset. + + + if port == 0x80 and data == 0xff37 and ram_is_initialized == false then + ram_is_initialized = true + -- Register low RAM 0x00000000 - 0x000dffff + SerialICE_register_physical(0x00000000, 0xa0000) + -- SMI/VGA memory should go to the target... + SerialICE_register_physical(0x000c0000, 0x20000) + printf("\nLow RAM accesses are now directed to Qemu.\n") + + return false, data + end + + + -- ********************************************************** + -- + -- unknown io_write delay hooks + -- + + if ( port == 0xed and data == 0x40 ) then + if ( regs.eip == 0x3ed and regs.ecx == 0x00000290 ) then + printf("Skipping IO delay...\n") + -- f100:03ed + regs.ecx = 0x05 + end + end + + if ( port == 0xed and data == 0x83 ) + then + if ( regs.eip == 0x1bb and regs.ecx == 0x0000fff0 ) then + printf("Skipping IO delay...\n") + -- e002:01bb + regs.ecx = 0x10 + regs.ebx = 0x01 + end + end + + + + + -- ********************************************************** + -- + -- io_read hooks, unknown vendor + + -- if port == 0x42 then + -- printf("WARNING: Hijacking timer port 0x42\n") + -- data = 0x80 + -- caught = true + -- end + + -- + -- + + if ( port == 0x60 and data_size == 1 ) then + if ( regs.eip == 0xbd6d and regs.eax == 0x8aa and regs.ecx == 0x00fffff0 ) then + -- f000:bd6d + printf("Skipping keyboard timeout...\n") + regs.eax = 0x01aa + regs.ecx = 0x0010 + end + end + + +-- ********************************************************** +-- Intel 82945 PCIe BAR + +function pcie_bar_hook(bdfr, size, data) + -- size is hard coded 64k for now. + pcie_mm_cfg_bar(bit.band(0xfc000000,data) % 0x100000000, 64 * 1024) +end + +if northbridge == "intel-i945" then + add_pci_cfg_hook(pci_bdf(0,0,0,0x48), 4, pcie_bar_hook) +end + +-- ********************************************************** +-- +-- Vendor specific Cache-As-Ram regions + +printf("SerialICE: Registering physical memory areas for Cache-As-Ram:\n") + +-- Register Phoenix BIOS Cache as RAM area as normal RAM +-- 0xffd80000 - 0xffdfffff +new_car_region(0xffd80000, 0x80000) + +-- Register AMI BIOS Cache as RAM area as normal RAM +-- 0xffbc0000 - 0xffbfffff +new_car_region(0xffbc0000, 0x40000) + +-- current Phoenix BIOS +new_car_region(0xde000, 0x2000) + diff --git a/SerialICE/simba/memory.lua b/SerialICE/simba/memory.lua new file mode 100644 index 0000000..3e13838 --- /dev/null +++ b/SerialICE/simba/memory.lua @@ -0,0 +1,239 @@ + + +mem_read_log_hooks = new_list() +mem_write_log_hooks = new_list() + + +car_regions = { list = nil } + +function new_car_region(start, size) + car_regions.list = { next = car_regions.list, start = start, size = size } + SerialICE_register_physical(start, size) +end + +function is_car(addr) + if car_regions.list == nil then + return false + end + local l = car_regions.list + while l do + if addr >= l.start and addr < l.start + l.size then + return true + end + l = l.next + end + return false +end + + +-- SerialICE_memory_read_filter is the filter function for memory reads +-- +-- Parameters: +-- addr memory address to be read +-- size Size of the memory read +-- Return values: +-- to_hw True if the read should be directed to the target +-- to_qemu True if the read should be directed to Qemu +-- result Read result if both to_hw and to_qemu are false + +function SerialICE_memory_read_filter(addr, size) + + -- Example: catch memory read and return a value + -- defined in this script: + -- + -- if addr == 0xfec14004 and size == 4 then + -- return false, false, 0x23232323 + -- end + + -- Cache-As-RAM is exclusively + -- handled by Qemu (RAM backed) + if is_car(addr) then + return false, true, 0 + end + + if addr >= rom_base and addr <= 0xffffffff then + -- ROM accesses go to Qemu only + return false, true, 0 + elseif addr >= PCIe_bar and addr <= (PCIe_bar + PCIe_size) then + -- PCIe MMIO config space accesses are + -- exclusively handled by the SerialICE + -- target + return true, false, 0 + elseif addr >= 0xfed10000 and addr <= 0xfed1ffff then + -- Intel chipset BARs are exclusively + -- handled by the SerialICE target + return true, false, 0 + elseif addr >= 0xfee00000 and addr <= 0xfeefffff then + -- Local APIC.. Hm, not sure what to do here. + -- We should avoid that someone wakes up cores + -- on the target system that go wild. + return true, false, 0 -- XXX Handled by target + elseif addr >= 0xfec00000 and addr <= 0xfecfffff then + -- IO APIC.. Hm, not sure what to do here. + return true, false, 0 -- XXX Handled by target + elseif addr >= 0xfed40000 and addr <= 0xfed45000 then + -- ICH7 TPM + -- Phoenix "Secure" Core bails out if we don't pass this on ;-) + return true, false, 0 + elseif addr >= 0x000e0000 and addr <= 0x000fffff then + -- Low ROM accesses go to Qemu memory + return false, true, 0 + elseif addr >= 0x000a0000 and addr <= 0x000affff then + -- SMI/VGA go to target + return true, false, 0 + elseif addr >= 0x00000000 and addr <= 0x000dffff then + -- RAM access. This is handled by SerialICE + -- but *NOT* exclusively. Writes should end + -- up in Qemu memory, too + if not ram_is_initialized then + -- RAM init has not not been marked done yet. + -- so send reads to the target only. + return true, false, 0 + end + -- RAM init is done. Send all RAM accesses + -- to Qemu. Using the target as storage would + -- only slow execution down. + -- TODO handle VGA / SMI memory correctly + return false, true, 0 + elseif addr >= 0x00100000 and addr <= 0xcfffffff then + -- 3.25GB RAM. This is handled by SerialICE. + -- We refrain from backing up this memory in Qemu + -- because Qemu would need 3.25G RAM on the host + -- and firmware usually does not intensively use + -- high memory anyways. + return true, false, 0 + else + printf("\nWARNING: undefined load operation @%08x\n", addr) + -- Fall through and handle by Qemu + end + return false, true, 0 +end + +-- SerialICE_memory_write_filter is the filter function for memory writes +-- +-- Parameters: +-- addr memory address to write to +-- size Size of the memory write +-- data Data to be written +-- Return values: +-- to_hw True if the write should be directed to the target +-- to_qemu True if the write should be directed to Qemu +-- result Data to be written (may be changed in filter) + +function SerialICE_memory_write_filter(addr, size, data) + -- Cache-As-RAM is exclusively + -- handled by Qemu (RAM backed) + if is_car(addr) then + return false, true, data + end + + if addr >= rom_base and addr <= 0xffffffff then + printf("\nWARNING: write access to ROM?\n") + -- ROM accesses go to Qemu only + return false, true, data + elseif addr >= PCIe_bar and addr <= (PCIe_bar + PCIe_size) then + -- PCIe MMIO config space accesses are + -- exclusively handled by the SerialICE + -- target + return true, false, data + elseif addr >= 0xfed10000 and addr <= 0xfed1ffff then + -- Intel chipset BARs are exclusively + -- handled by the SerialICE target + return true, false, data + elseif addr >= 0xfee00000 and addr <= 0xfeefffff then + -- Local APIC.. Hm, not sure what to do here. + -- We should avoid that someone wakes up cores + -- on the target system that go wild. + return true, false, data + elseif addr >= 0xfec00000 and addr <= 0xfecfffff then + -- IO APIC.. Hm, not sure what to do here. + return true, false, data + elseif addr >= 0xfed40000 and addr <= 0xfed45000 then + -- ICH7 TPM + return true, false, data + elseif addr >= 0x000e0000 and addr <= 0x000fffff then + -- Low ROM accesses go to Qemu memory + return false, true, data + elseif addr >= 0x000a0000 and addr <= 0x000affff then + -- SMI/VGA go to target + return true, true, data + elseif addr >= 0x00000000 and addr <= 0x000dffff then + -- RAM access. This is handled by SerialICE during + -- RAM initialization and by Qemu later on. + if not ram_is_initialized then + return true, true, data + end + -- Don't send writes to the target for speed reasons. + return false, true, data + elseif addr >= 0x00100000 and addr <= 0xcfffffff then + if addr == 0x00100000 then + if regs.cs == 0xe002 and regs.eip == 0x07fb then + -- skip high memory wipe + regs.ecx = 0x10 + end + if regs.cs == 0xe002 and regs.eip == 0x076c and regs.edi == 0x3f then + -- skip high memory test + regs.edi=1; + end + end + + -- 3.25 GB RAM ... This is handled by SerialICE + return true, false, data + else + printf("\nWARNING: undefined store operation @%08x\n", addr) + -- Fall through, send to SerialICE + end + + return true, false, data +end + + + +function SerialICE_memory_write_log(addr, size, data, target) + if addr >= 0x00000000 and addr <= 0x0009ffff and ram_is_initialized then + return + end + if addr >= 0x000c0000 and addr <= 0x000dffff and ram_is_initialized then + return + end + + log_cs_ip() + + if walk_list(mem_write_log_hooks, addr, size, data, target) then + return + end + + printf("MEM: write%s %08x <= %s", size_suffix(size), addr, size_data(size, data)) + if target then + printf(" *") + end + printf("\n") +end + +function SerialICE_memory_read_log(addr, size, data, target) + if addr >= 0x00000000 and addr <= 0x0009ffff and ram_is_initialized then + return + end + if addr >= 0x000c0000 and addr <= 0x000dffff and ram_is_initialized then + return + end + if addr >= 0xe0000 and addr <= 0xfffff and not log_rom_access then + return + end + if addr >= rom_base and addr <= 0xffffffff and not log_rom_access then + return + end + + log_cs_ip() + + if walk_list(mem_read_log_hooks, addr, size, data, target) then + return + end + + printf("MEM: read%s %08x => %s", size_suffix(size), addr, size_data(size, data)) + if target then + printf(" *") + end + printf("\n") +end + diff --git a/SerialICE/simba/misc.lua b/SerialICE/simba/misc.lua new file mode 100644 index 0000000..e7be535 --- /dev/null +++ b/SerialICE/simba/misc.lua @@ -0,0 +1,198 @@ +-- ********************************************************** +-- +-- KBD controller 8042 + +i8042_data = 0x0 +i8042_sts = 0x0 +i8042_cmd = 0x0 + +function i8042_write(port, size, data, filter) + if port == 0x60 then + i8042_data = data + i8042_sts = bit.band(i8042_sts, 0xf7) + if (i8042_cmd == 0xd1) then + gate_A20 = (bit.band(0x02, data) == 0x02) + end + end + if port == 0x64 then + i8042_cmd = data + i8042_sts = bit.bor(i8042_sts, 0x0a) + end + return false +end + +function i8042_read(port, size, data, filter) + if port == 0x60 then + i8042_data = data + i8042_sts = bit.band(i8042_sts, 0xfe) + end + return false +end + +function i8042_write_log(port, size, data, target) + if port == 0x60 and i8042_cmd == 0xd1 then + if gate_A20 then + printf("i8042: A20 enabled\n") + else + printf("i8042: A20 disabled\n") + end + + end + return false +end + +function i8042_read_log(port, size, data, target) + return false +end + + +if decode_i8042 then + prepend_to_list(io_write_hooks, i8042_write) + prepend_to_list(io_read_hooks, i8042_read) + prepend_to_list(io_write_log_hooks, i8042_write_log) + prepend_to_list(io_read_log_hooks, i8042_read_log) +end + +-- ********************************************************** +-- +-- CMOS nvram + +port_70_reg = 0x0 +port_72_reg = 0x0 + +nvram_data = {} +nvram_set = {} + +for i = 0, 0xff, 1 do nvram_data[i] = 0 end +for i = 0, 0xff, 1 do nvram_set[i] = false end + +function nvram_write(port, size, data, filter) + if port < 0x70 or port >= 0x74 then + return false + end + + + if port == 0x70 then + port_70_reg = bit.band(0x7f, data) + if port_70_reg < 0x0E then + filter.filter = false + else + filter.filter = true + end + elseif port == 0x71 then + nvram_data[port_70_reg] = data + nvram_set[port_70_reg] = true + if port_70_reg < 0x0E then + filter.filter = false + else + filter.filter = true + end + elseif port == 0x72 then + port_72_reg = bit.band(0x7f, data) + filter.filter = true + elseif port == 0x73 then + local index = 0x80 + port_72_reg + nvram_data[index] = data + nvram_set[index] = true + filter.filter = true + end + if cache_nvram then + return filter.filter + end + return false +end + +function nvram_read(port, size, data, filter) + if port < 0x70 or port >= 0x74 then + return false + end + filter.data = 0 + if port == 0x70 then + -- NMI returned as 0 + filter.data = port_70_reg + if port_70_reg < 0x0E then + filter.filter = false + else + filter.filter = true + end + elseif port == 0x71 then + if port_70_reg < 0x0E then + filter.filter = false + elseif nvram_set[port_70_reg] then + filter.data = nvram_data[port_70_reg] + filter.filter = true + else + filter.filter = true + end + elseif port == 0x72 then + -- NMI returned as 0 + filter.data = port_72_reg + filter.filter = false + elseif port == 0x73 then + local index = 0x80 + port_72_reg + if nvram_set[index] then + filter.data = nvram_data[index] + end + filter.filter = true + end + if cache_nvram then + return filter.filter + end + return false +end + +function nvram_write_log(port, size, data, target) + if port < 0x70 or port >= 0x74 then + return false + end + if port == 0x71 then + printf("NVram: [%02x] <= %02x\n", port_70_reg, data) + elseif port == 0x73 then + printf("NVram: [%02x] <= %02x\n", 0x80 + port_72_reg, data) + end + return not log_nvram_io +end + +function nvram_read_log(port, size, data, target) + if port < 0x70 or port >= 0x74 then + return false + end + if port == 0x71 then + printf("NVram: [%02x] => %02x\n", port_70_reg, data) + elseif port == 0x73 then + printf("NVram: [%02x] => %02x\n", 0x80 + port_72_reg, data) + end + return not log_nvram_io +end + + +if decode_nvram then + prepend_to_list(io_write_hooks, nvram_write) + prepend_to_list(io_read_hooks, nvram_read) + prepend_to_list(io_write_log_hooks, nvram_write_log) + prepend_to_list(io_read_log_hooks, nvram_read_log) +end + +-- ********************************************************** +-- +-- System reset + +function sys_rst(port, size, data, filter) + if port == 0xcf9 and data == 0x06 then + SerialICE_system_reset() + return false + end +end + +function sys_rst_log(port, size, data, target) + if port == 0xcf9 then + printf("Reset triggered at %04x:%04x\n", regs.cs, regs.eip); + return true + end +end + +if decode_sys_rst then + prepend_to_list(io_write_hooks, sys_rst) + prepend_to_list(io_write_log_hooks, sys_rst_log) +end + diff --git a/SerialICE/simba/serialice.lua b/SerialICE/simba/serialice.lua new file mode 100644 index 0000000..1c00204 --- /dev/null +++ b/SerialICE/simba/serialice.lua @@ -0,0 +1,158 @@ +-- SerialICE +-- +-- Copyright (c) 2009 coresystems GmbH +-- +-- Permission is hereby granted, free of charge, to any person obtaining a copy +-- of this software and associated documentation files (the "Software"), to deal +-- in the Software without restriction, including without limitation the rights +-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +-- copies of the Software, and to permit persons to whom the Software is +-- furnished to do so, subject to the following conditions: +-- +-- The above copyright notice and this permission notice shall be included in +-- all copies or substantial portions of the Software. +-- +-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +-- THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +-- THE SOFTWARE. +-- + +io.write("SerialICE: Starting LUA script\n") + +-- If you get an error here, install bitlib +-- (ie. http://luaforge.net/projects/bitlib/) +require("bit") + + +-- ------------------------------------------------------------------- +-- logging functions + +function log_cs_ip() + if (ip_logging) then printf("[%04x:%04x] -- ", regs.cs, regs.eip) end +end + +function printf(s,...) + return io.write(s:format(...)) +end + +function trim (s) + return (string.gsub(s, "^%s*(.-)%s*$", "%1")) +end + +function size_suffix(size) + if size == 1 then return "b" + elseif size == 2 then return "w" + elseif size == 4 then return "l" + elseif size == 8 then return "ll" + else return string.format("invalid size: %d", size) + end +end + +function size_data(size, data) + if size == 1 then return string.format("%02x", data) + elseif size == 2 then return string.format("%04x", data) + elseif size == 4 then return string.format("%08x", data) + elseif size == 8 then return string.format("%16x", data) + else return string.format("Error: size=%x", size) + end +end + + + +function new_list() + return { list = nil } +end + +function prepend_to_list(list, value) + list.list = { next = list.list, value = value } +end + +function walk_list(list, ...) + if list == nil or list.list == nil then + return false + end + local l = list.list + while l do + if l.value(...) then + return true + end + l = l.next + end + return false +end + + + +-- In the beginning, during RAM initialization, it is essential that +-- all DRAM accesses are handled by the target, or RAM will not work +-- correctly. After RAM initialization, RAM access has no "special" +-- meaning anymore, so we can just use Qemu's memory (and thus get +-- an incredible speed-up) + +-- Not catching the end of RAM init is not problematic, except +-- that it makes decompression of the BIOS core to RAM incredibly +-- slow as the decompressor inner loop has to be fetched +-- permanently from the target (several reads/writes per +-- decompressed byte). + +ram_is_initialized = false + + +-- Set to "true" to log read access (code fetches) to 0xe0000 to 0xfffff + +log_rom_access = false + +-- Set to "true" to log CS:IP for each access + +ip_logging = false + + +rom_size = 4 * 1024 * 1024 +rom_base = 0x100000000 - rom_size + + +decode_pci_io_cfg = true +decode_pci_mm_cfg = true +decode_nvram = true +decode_sys_rst = true +decode_smbus = true +decode_superio = true +decode_i8042 = true + +-- Log hooks only apply when decode above is enabled +log_pci_io_cfg = false +log_pci_mm_cfg = false +log_superio_cfg = false +log_nvram_io = false +log_smbus_io = false + +-- Use lua table for NVram +cache_nvram = false + +-- This initialization is executed right after target communication +-- has been established + +dofile("core_io.lua") +dofile("superio.lua") +dofile("memory.lua") +dofile("cpu.lua") +dofile("misc.lua") + +printf("SerialICE: LUA script initialized.\n") + +mainboard_file = string.format("%s.lua", string.lower(string.gsub(SerialICE_mainboard, " ", "_"))) + +local mainboard_lua = loadfile(mainboard_file) +if (mainboard_lua) then + mainboard_lua() + printf("SerialICE: Mainboard script %s initialized.\n", mainboard_file) +else + printf("SerialICE: Mainboard script %s not found.\n", mainboard_file) +end + +return true + diff --git a/SerialICE/simba/superio.lua b/SerialICE/simba/superio.lua new file mode 100644 index 0000000..9f0c93b --- /dev/null +++ b/SerialICE/simba/superio.lua @@ -0,0 +1,235 @@ +-- ********************************************************** +-- +-- SuperIO config handling + +port_2e_reg = 0x0 +port_2e_ldn = 0x0 +port_2f_reg = 0x0 + +port_4e_reg = 0x0 +port_4e_ldn = 0x0 +port_4f_reg = 0x0 + +if 1 then + -- SMSC? + port_2e_ldn_register = 0x07 + port_4e_ldn_register = 0x07 +else + -- Winbond + port_2e_ldn_register = 0x06 + port_4e_ldn_register = 0x06 +end + + +ldn_set = {} +ldn_data = {} + +function reset_2e_ldn(data) + if not (port_2e_ldn == data) then + port_2e_ldn = data + for i = 0, 0xff, 1 do ldn_data[i] = 0 end + for i = 0, 0xff, 1 do ldn_set[i] = false end + end +end + +function set_2e_reg(data) + port_2e_reg = data +end + +function set_2e_data(data) + + if port_2e_reg == port_2e_ldn_register then + reset_2e_ldn(data) + end + ldn_data[port_2e_reg] = data; + ldn_set[port_2e_reg] = true; +end + + +function port_2f_write_log(port, size, data, target) + + local pnpdev = bit.band(port, 0xfe) + + if port_2e_reg == port_2e_ldn_register then + return true + end + + if ((port_2e_reg == 0x30) or (port_2e_reg == 0x60) or (port_2e_reg == 0x61)) then + if (ldn_set[0x30] and not (ldn_data[0x30]==0x0)) then + if (ldn_set[0x60] and ldn_set[0x61]) then + local iobase = bit.bor(bit.lshift(ldn_data[0x60], 8), ldn_data[0x61]) + printf("PnP: %02x:%02x enabled @ iobase = 0x%04x\n", + pnpdev, port_2e_ldn, iobase) + elseif (port_2e_reg == 0x30) then + printf("PnP: %02x:%02x enabled\n", pnpdev, port_2e_ldn) + end + elseif (port_2e_reg == 0x30) and (ldn_set[0x30]==true) and (ldn_data[0x30]==0x0) then + printf("PnP: %02x:%02x disabled\n", pnpdev, port_2e_ldn) + end + return true + end + + if port_2e_reg == 0x70 then + printf("PnP: %02x:%02x irq = %d\n", pnpdev, port_2e_ldn, ldn_data[0x70]) + return true + end + if port_2e_reg == 0x72 then + printf("PnP: %02x:%02x irq2 = %d\n", pnpdev, port_2e_ldn, ldn_data[0x72]) + return true + end + + printf("PnP: %02x:%02x R.%02x <= %02x\n", pnpdev, port_2e_ldn, port_2e_reg, ldn_data[port_2e_reg]) + return true +end + +function port_2f_read_log(port, size, data, target) + local pnpdev = bit.band(port, 0xfe) + printf("PnP %02x:%02x R.%02x => %02x\n", pnpdev, port_2e_ldn, port_2e_reg, data) + return true +end + +function superio_write(port, size, data, filter) + + if port == 0x2e then + set_2e_reg(data) + return false + end + + if port == 0x2f then + set_2e_data(data) + + -- Don't allow that our SIO power gets disabled. + if port_2e_reg == 0x02 then + printf("SuperIO (filtered)\n") + filter.filter = true + filter.data = data + return true + end + + -- Don't mess with oscillator setup. + if port_2e_reg == 0x24 then + printf("SuperIO (filtered)\n") + filter.filter = true + filter.data = data + return true + end + end + + if port == 0x4e then + port_4e_reg = data + filter.filter = false + filter.data = data + return false + end + + if port == 0x4f then + if port_4e_reg == port_4e_ldn_register then + port_4e_ldn = data + return false + end + -- Don't allow that our Serial power gets disabled. + if port_4e_reg == 0x02 then + printf("SuperIO (filtered)\n") + return true, data + end + -- Don't mess with oscillator setup. + if port_4e_reg == 0x24 then + printf("SuperIO (filtered)\n") + filter.filter = true + filter.data = data + return true + end + + end + + return false +end + + + +function superio_write_log(port, size, data, target) + + if port == 0x2e then + return not log_superio_cfg + end + if port == 0x2f then + port_2f_write_log(port, size, data, target) + return not log_superio_cfg + end + + if port == 0x4e then + return not log_superio_cfg + end + if port == 0x4f then + if not (port_4e_reg == port_4e_ldn_register) then + printf("PnP: %02x:%02x R.%02x <= %02x\n", 0x4e, port_4e_ldn, port_4e_reg, data) + end + return not log_superio_cfg + end + return false +end + +function superio_read_log(port, size, data, target) + + if port == 0x2e then + return not log_superio_cfg + end + if port == 0x2f then + port_2f_read_log(port, size, data, target) + return not log_superio_cfg + end + + if port == 0x4e then + return not log_superio_cfg + end + if port == 0x4f then + printf("PnP %02x:%02x R.%02x => %02x\n", 0x4e, port_4e_ldn, port_4e_reg, data) + return not log_superio_cfg + end + return false +end + +if decode_superio then + prepend_to_list(io_write_hooks, superio_write) + prepend_to_list(io_write_log_hooks, superio_write_log) + prepend_to_list(io_read_log_hooks, superio_read_log) +end + + + +-- ********************************************************** +-- +-- Serial Port handling + +com1_base = 0x3f8 +com1_size = 0x8 + + +function uart_write(port, size, data, filter) + if port > com1_base and port < com1_base + com1_size then + printf("serial I/O (filtered)\n") + filter.filter = true + filter.data = data + return true + end + + if port == com1_base then + printf("COM1: %c\n", data) + filter.filter = true + filter.data = data + return true + end +end + +function uart_read(port, size, data, filter) + if port >= com1_base and port < com1_base + com1_size then + printf("Serial I/O read (filtered)\n") + filter.filter = true + filter.data = 0xff + return true + end +end + +prepend_to_list(io_write_hooks, uart_write) +prepend_to_list(io_read_hooks, uart_read) +

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Patch merged into serialice/master: 459e9ef Change IO write logging order
by gerrit＠coreboot.org April 22, 2012

April 22, 2012

the following patch was just integrated into master: commit 459e9ef54e9251d983b324aeec8af3a07fcc2077 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Apr 22 16:33:58 2012 +0300 Change IO write logging order Apply the write filter before log, so logged value will match the value going to the target. Follow the style of IO read functions in the implementation. Change-Id: I3740ff417522eadddf2c058535c4d0b4bf4ae56f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Sun Apr 22 18:07:44 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Mon Apr 23 03:47:50 2012, giving +2 See http://review.coreboot.org/920 for details. -gerrit

1 0

Patch merged into serialice/master: 932d3eb Log filtered IO reads
by gerrit＠coreboot.org April 22, 2012

April 22, 2012

the following patch was just integrated into master: commit 932d3eb861928b40e2950385f3ffdabe159c0c13 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Apr 22 16:26:38 2012 +0300 Log filtered IO reads With inb/inw/inl instructions, read_log() was not called if the IO was filtered and did not reach the target HW. QEMU will still receive some input value, so log it. Change-Id: Iccf635938322177c88664e55ca9f36197fcfd92e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Sun Apr 22 17:58:04 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Mon Apr 23 03:46:59 2012, giving +2 See http://review.coreboot.org/919 for details. -gerrit

1 0

New patch to review for serialice: 459e9ef Change IO write logging order
by Kyösti Mälkki April 22, 2012

April 22, 2012

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/920 -gerrit commit 459e9ef54e9251d983b324aeec8af3a07fcc2077 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Apr 22 16:33:58 2012 +0300 Change IO write logging order Apply the write filter before log, so logged value will match the value going to the target. Follow the style of IO read functions in the implementation. Change-Id: I3740ff417522eadddf2c058535c4d0b4bf4ae56f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- qemu-0.15.x/serialice.c | 45 +++++++++++++++++++++++++++------------------ 1 files changed, 27 insertions(+), 18 deletions(-) diff --git a/qemu-0.15.x/serialice.c b/qemu-0.15.x/serialice.c index 9963c7d..a91f9c6 100644 --- a/qemu-0.15.x/serialice.c +++ b/qemu-0.15.x/serialice.c @@ -776,46 +776,55 @@ uint32_t serialice_inl(uint16_t port) void serialice_outb(uint8_t data, uint16_t port) { uint32_t filtered_data = (uint32_t) data; + int filtered; - serialice_log(LOG_WRITE | LOG_IO, data, port, 1); + filtered = serialice_io_write_filter(&filtered_data, port, 1); - if (serialice_io_write_filter(&filtered_data, port, 1)) { - return; + if (filtered) { + data = (uint8_t) filtered_data; + } else { + data = (uint8_t) filtered_data; + sprintf(s->command, "*wi%04x.b=%02x", port, data); + serialice_command(s->command, 0); } - data = (uint8_t) filtered_data; - sprintf(s->command, "*wi%04x.b=%02x", port, data); - serialice_command(s->command, 0); + serialice_log(LOG_WRITE | LOG_IO, data, port, 1); } void serialice_outw(uint16_t data, uint16_t port) { uint32_t filtered_data = (uint32_t) data; + int filtered; - serialice_log(LOG_WRITE | LOG_IO, data, port, 2); + filtered = serialice_io_write_filter(&filtered_data, port, 2); - if (serialice_io_write_filter(&filtered_data, port, 2)) { - return; + if (filtered) { + data = (uint16_t) filtered_data; + } else { + data = (uint16_t) filtered_data; + sprintf(s->command, "*wi%04x.w=%04x", port, data); + serialice_command(s->command, 0); } - data = (uint16_t) filtered_data; - sprintf(s->command, "*wi%04x.w=%04x", port, data); - serialice_command(s->command, 0); + serialice_log(LOG_WRITE | LOG_IO, data, port, 2); } void serialice_outl(uint32_t data, uint16_t port) { uint32_t filtered_data = data; + int filtered; - serialice_log(LOG_WRITE | LOG_IO, data, port, 4); + filtered = serialice_io_write_filter(&filtered_data, port, 4); - if (serialice_io_write_filter(&filtered_data, port, 4)) { - return; + if (filtered) { + data = filtered_data; + } else { + data = filtered_data; + sprintf(s->command, "*wi%04x.l=%08x", port, data); + serialice_command(s->command, 0); } - data = filtered_data; - sprintf(s->command, "*wi%04x.l=%08x", port, data); - serialice_command(s->command, 0); + serialice_log(LOG_WRITE | LOG_IO, data, port, 4); } uint8_t serialice_readb(uint32_t addr)

1 0

New patch to review for serialice: 932d3eb Log filtered IO reads
by Kyösti Mälkki April 22, 2012

April 22, 2012

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/919 -gerrit commit 932d3eb861928b40e2950385f3ffdabe159c0c13 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Apr 22 16:26:38 2012 +0300 Log filtered IO reads With inb/inw/inl instructions, read_log() was not called if the IO was filtered and did not reach the target HW. QEMU will still receive some input value, so log it. Change-Id: Iccf635938322177c88664e55ca9f36197fcfd92e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- qemu-0.15.x/serialice.c | 51 +++++++++++++++++++++++++++------------------- 1 files changed, 30 insertions(+), 21 deletions(-) diff --git a/qemu-0.15.x/serialice.c b/qemu-0.15.x/serialice.c index 4ad082b..9963c7d 100644 --- a/qemu-0.15.x/serialice.c +++ b/qemu-0.15.x/serialice.c @@ -711,15 +711,18 @@ uint8_t serialice_inb(uint16_t port) { uint8_t ret; uint32_t data; + int filtered; - if (serialice_io_read_filter(&data, port, 1)) { - return data & 0xff; - } + filtered = serialice_io_read_filter(&data, port, 1); - sprintf(s->command, "*ri%04x.b", port); - // command read back: "\n00" (3 characters) - serialice_command(s->command, 3); - ret = (uint8_t) strtoul(s->buffer + 1, (char **)NULL, 16); + if (filtered) { + ret = data & 0xff; + } else { + sprintf(s->command, "*ri%04x.b", port); + // command read back: "\n00" (3 characters) + serialice_command(s->command, 3); + ret = (uint8_t) strtoul(s->buffer + 1, (char **)NULL, 16); + } serialice_log(LOG_READ | LOG_IO, ret, port, 1); @@ -730,15 +733,18 @@ uint16_t serialice_inw(uint16_t port) { uint16_t ret; uint32_t data; + int filtered; - if (serialice_io_read_filter(&data, port, 2)) { - return data & 0xffff; - } + filtered = serialice_io_read_filter(&data, port, 2); - sprintf(s->command, "*ri%04x.w", port); - // command read back: "\n0000" (5 characters) - serialice_command(s->command, 5); - ret = (uint16_t) strtoul(s->buffer + 1, (char **)NULL, 16); + if (filtered) { + ret = data & 0xffff; + } else { + sprintf(s->command, "*ri%04x.w", port); + // command read back: "\n0000" (5 characters) + serialice_command(s->command, 5); + ret = (uint16_t) strtoul(s->buffer + 1, (char **)NULL, 16); + } serialice_log(LOG_READ | LOG_IO, ret, port, 2); @@ -749,15 +755,18 @@ uint32_t serialice_inl(uint16_t port) { uint32_t ret; uint32_t data; + int filtered; - if (serialice_io_read_filter(&data, port, 4)) { - return data; - } + filtered = serialice_io_read_filter(&data, port, 4); - sprintf(s->command, "*ri%04x.l", port); - // command read back: "\n00000000" (9 characters) - serialice_command(s->command, 9); - ret = (uint32_t) strtoul(s->buffer + 1, (char **)NULL, 16); + if (filtered) { + ret = data; + } else { + sprintf(s->command, "*ri%04x.l", port); + // command read back: "\n00000000" (9 characters) + serialice_command(s->command, 9); + ret = (uint32_t) strtoul(s->buffer + 1, (char **)NULL, 16); + } serialice_log(LOG_READ | LOG_IO, ret, port, 4);

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Patch merged into serialice/master: d20332a Fix lua detection
by gerrit＠coreboot.org April 22, 2012

April 22, 2012

the following patch was just integrated into master: commit d20332a4a817fc20aa715af2db3212e581c29b28 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Apr 21 21:18:43 2012 +0300 Fix lua detection With these changes I can used shared lua library. Change-Id: I8bb19216aaae61fc04554a63e8b65ee84c298af1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Sun Apr 22 10:18:43 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Sun Apr 22 16:22:42 2012, giving +2 See http://review.coreboot.org/918 for details. -gerrit

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Patch merged into serialice/master: f82f6df Fix build with lua5.2
by gerrit＠coreboot.org April 22, 2012

April 22, 2012

the following patch was just integrated into master: commit f82f6df2c6a0a1cccbec4b879cce82c594cf8c00 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Apr 21 20:58:06 2012 +0300 Fix build with lua5.2 Reuse the following commit for qemu-0.15.x: c6fae6554d1fd48780258bef2b3be4b45ef3a588 Change-Id: I8b4ddd12aff3fb4a1799a1b446fdc71162b6b40f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sun Apr 22 11:51:27 2012, giving +2 See http://review.coreboot.org/917 for details. -gerrit

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Patch merged into serialice/master: 82c89f1 Apply serialice patch
by gerrit＠coreboot.org April 22, 2012

April 22, 2012

the following patch was just integrated into master: commit 82c89f1a63fa33076ee5e9e4639653d1596281ca Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Apr 21 20:24:39 2012 +0300 Apply serialice patch Apply SerialICE/patches/serialice-qemu-0.15.0.diff from commit: b1ddcd86f4ea27bf8f20020ae24954da5d948b4e Change-Id: I5b70840516d633ffa7bea644c995fe9d241c372c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sun Apr 22 11:51:13 2012, giving +2 See http://review.coreboot.org/916 for details. -gerrit

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Patch merged into serialice/master: ba9ddeb Import QEMU 0.15.1
by gerrit＠coreboot.org April 22, 2012

April 22, 2012

the following patch was just integrated into master: commit ba9ddeb0975204057dc02ee70c777cb886b6ec59 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Apr 21 16:45:23 2012 +0300 Import QEMU 0.15.1 Download from QEMU main site: http://wiki.qemu.org/download/qemu-0.15.1.tar.gz md5sum: 34f17737baaf1b3495c89cd6d4a607ed Renamed directory qemu-0.15.1 to qemu-0.15.x Change-Id: Iaaa13f3c5cdbd5ddf4d235731be91e25607ea7d2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sun Apr 22 11:50:45 2012, giving +2 See http://review.coreboot.org/915 for details. -gerrit

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