[PATCH 2/4] pci: Allow scanning pci bus number up to 255 in CSM mode
From 3bf91481863ec504d113aa6b94827bf92840e291 Mon Sep 17 00:00:00 2001 From: gaobin <gaobin@amazon.com> Date: Thu, 19 Sep 2019 11:23:04 -0700 Subject: [PATCH 2/4] pci: Allow scanning pci bus number up to 255 in CSM mode On real hardware especially server platforms, there are many pci devices, bridges, either SoC integrated or addon. They can exhaust all the pci bus numbers. So when scanning the pci bus, we need to allow the bus number up to 255. Signed-off-by: gaobin <gaobin@amazon.com> --- src/hw/pcidevice.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/hw/pcidevice.c b/src/hw/pcidevice.c index 8853cf7..acf15b4 100644 --- a/src/hw/pcidevice.c +++ b/src/hw/pcidevice.c @@ -26,6 +26,12 @@ pci_probe_devices(void) struct hlist_node **pprev = &PCIDevices.first; int extraroots = romfile_loadint("etc/extra-pci-roots", 0); int bus = -1, lastbus = 0, rootbuses = 0, count=0; + + // On real hardware especially server platforms, the bus number + // could run up to the top value, i.e. 0xff + if (CONFIG_CSM) + extraroots = 0xff; + while (bus < 0xff && (bus < MaxPCIBus || rootbuses < extraroots)) { bus++; int bdf; -- 2.17.1
On Mon, Nov 25, 2019 at 07:25:26PM -0800, Your Real Name wrote:
From 3bf91481863ec504d113aa6b94827bf92840e291 Mon Sep 17 00:00:00 2001 From: gaobin <gaobin@amazon.com> Date: Thu, 19 Sep 2019 11:23:04 -0700 Subject: [PATCH 2/4] pci: Allow scanning pci bus number up to 255 in CSM mode
On real hardware especially server platforms, there are many pci devices, bridges, either SoC integrated or addon. They can exhaust all the pci bus numbers. So when scanning the pci bus, we need to allow the bus number up to 255.
Signed-off-by: gaobin <gaobin@amazon.com> --- src/hw/pcidevice.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/src/hw/pcidevice.c b/src/hw/pcidevice.c index 8853cf7..acf15b4 100644 --- a/src/hw/pcidevice.c +++ b/src/hw/pcidevice.c @@ -26,6 +26,12 @@ pci_probe_devices(void) struct hlist_node **pprev = &PCIDevices.first; int extraroots = romfile_loadint("etc/extra-pci-roots", 0); int bus = -1, lastbus = 0, rootbuses = 0, count=0; + + // On real hardware especially server platforms, the bus number + // could run up to the top value, i.e. 0xff + if (CONFIG_CSM) + extraroots = 0xff;
What exactly you are trying to fix here? seabios should find all pci devices behind bridges without problems. cheers, Gerd
On Wed, Nov 27, 2019 at 08:08:23AM +0100, Gerd Hoffmann wrote:
On Mon, Nov 25, 2019 at 07:25:26PM -0800, Your Real Name wrote:
From 3bf91481863ec504d113aa6b94827bf92840e291 Mon Sep 17 00:00:00 2001 From: gaobin <gaobin@amazon.com> Date: Thu, 19 Sep 2019 11:23:04 -0700 Subject: [PATCH 2/4] pci: Allow scanning pci bus number up to 255 in CSM mode
On real hardware especially server platforms, there are many pci devices, bridges, either SoC integrated or addon. They can exhaust all the pci bus numbers. So when scanning the pci bus, we need to allow the bus number up to 255.
Signed-off-by: gaobin <gaobin@amazon.com> --- src/hw/pcidevice.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/src/hw/pcidevice.c b/src/hw/pcidevice.c index 8853cf7..acf15b4 100644 --- a/src/hw/pcidevice.c +++ b/src/hw/pcidevice.c @@ -26,6 +26,12 @@ pci_probe_devices(void) struct hlist_node **pprev = &PCIDevices.first; int extraroots = romfile_loadint("etc/extra-pci-roots", 0); int bus = -1, lastbus = 0, rootbuses = 0, count=0; + + // On real hardware especially server platforms, the bus number + // could run up to the top value, i.e. 0xff + if (CONFIG_CSM) + extraroots = 0xff;
What exactly you are trying to fix here?
seabios should find all pci devices behind bridges without problems.
The problem is from the following statement: while (bus < 0xff && (bus < MaxPCIBus || rootbuses < extraroots)) { extraroots always returns 0 in csm mode, and "bus < MaxPCIBus" returns false very early. So the while loop ends early, leaving many pci devices un-scanned. Without the patch, I got: "Found 33 PCI devices (max PCI bus is 02)" With the patch, I got: "Found 159 PCI devices (max PCI bus is b2)"
cheers, Gerd
Hi,
+ // On real hardware especially server platforms, the bus number + // could run up to the top value, i.e. 0xff + if (CONFIG_CSM) + extraroots = 0xff;
What exactly you are trying to fix here?
seabios should find all pci devices behind bridges without problems.
The problem is from the following statement:
while (bus < 0xff && (bus < MaxPCIBus || rootbuses < extraroots)) {
extraroots always returns 0 in csm mode, and "bus < MaxPCIBus" returns false very early. So the while loop ends early, leaving many pci devices un-scanned.
So the question is whenever there are *really* multiple roots or if that patch just papers over a bug somewhere in seabios.
Without the patch, I got: "Found 33 PCI devices (max PCI bus is 02)"
With the patch, I got: "Found 159 PCI devices (max PCI bus is b2)"
Can you run "lspci -vt" and post the output here? thanks, Gerd
On Tue, Dec 03, 2019 at 10:55:27AM +0100, Gerd Hoffmann wrote:
Hi,
+ // On real hardware especially server platforms, the bus number + // could run up to the top value, i.e. 0xff + if (CONFIG_CSM) + extraroots = 0xff;
What exactly you are trying to fix here?
seabios should find all pci devices behind bridges without problems.
The problem is from the following statement:
while (bus < 0xff && (bus < MaxPCIBus || rootbuses < extraroots)) {
extraroots always returns 0 in csm mode, and "bus < MaxPCIBus" returns false very early. So the while loop ends early, leaving many pci devices un-scanned.
So the question is whenever there are *really* multiple roots or if that patch just papers over a bug somewhere in seabios.
Without the patch, I got: "Found 33 PCI devices (max PCI bus is 02)"
With the patch, I got: "Found 159 PCI devices (max PCI bus is b2)"
Can you run "lspci -vt" and post the output here?
Here is the output of lspci -vt: -+-[0000:b2]-+-05.0 Intel Corporation Device 2034 | +-05.2 Intel Corporation Sky Lake-E RAS Configuration Registers | +-05.4 Intel Corporation Device 2036 | +-0e.0 Intel Corporation Device 2058 | +-0e.1 Intel Corporation Device 2059 | +-0f.0 Intel Corporation Device 2058 | +-0f.1 Intel Corporation Device 2059 | +-10.0 Intel Corporation Device 2058 | +-10.1 Intel Corporation Device 2059 | +-12.0 Intel Corporation Sky Lake-E M3KTI Registers | +-12.1 Intel Corporation Sky Lake-E M3KTI Registers | +-12.2 Intel Corporation Sky Lake-E M3KTI Registers | +-12.4 Intel Corporation Sky Lake-E M3KTI Registers | +-12.5 Intel Corporation Sky Lake-E M3KTI Registers | +-15.0 Intel Corporation Sky Lake-E M2PCI Registers | +-16.0 Intel Corporation Sky Lake-E M2PCI Registers | +-16.4 Intel Corporation Sky Lake-E M2PCI Registers | \-17.0 Intel Corporation Sky Lake-E M2PCI Registers +-[0000:64]-+-00.0-[65-68]----00.0-[66-68]----03.0-[67-68]--+-00.0 Intel Corporation Ethernet Connection X722 for 10GbE SFP+ | | +-00.1 Intel Corporation Ethernet Connection X722 for 10GbE SFP+ | | +-00.2 Intel Corporation Ethernet Connection X722 for 10GbE SFP+ | | \-00.3 Intel Corporation Ethernet Connection X722 for 10GbE SFP+ | +-05.0 Intel Corporation Device 2034 | +-05.2 Intel Corporation Sky Lake-E RAS Configuration Registers | +-05.4 Intel Corporation Device 2036 | +-08.0 Intel Corporation Device 2066 | +-09.0 Intel Corporation Device 2066 | +-0a.0 Intel Corporation Device 2040 | +-0a.1 Intel Corporation Device 2041 | +-0a.2 Intel Corporation Device 2042 | +-0a.3 Intel Corporation Device 2043 | +-0a.4 Intel Corporation Device 2044 | +-0a.5 Intel Corporation Device 2045 | +-0a.6 Intel Corporation Device 2046 | +-0a.7 Intel Corporation Device 2047 | +-0b.0 Intel Corporation Device 2048 | +-0b.1 Intel Corporation Device 2049 | +-0b.2 Intel Corporation Device 204a | +-0b.3 Intel Corporation Device 204b | +-0c.0 Intel Corporation Device 2040 | +-0c.1 Intel Corporation Device 2041 | +-0c.2 Intel Corporation Device 2042 | +-0c.3 Intel Corporation Device 2043 | +-0c.4 Intel Corporation Device 2044 | +-0c.5 Intel Corporation Device 2045 | +-0c.6 Intel Corporation Device 2046 | +-0c.7 Intel Corporation Device 2047 | +-0d.0 Intel Corporation Device 2048 | +-0d.1 Intel Corporation Device 2049 | +-0d.2 Intel Corporation Device 204a | \-0d.3 Intel Corporation Device 204b +-[0000:16]-+-03.0-[17]----00.0 Device 1987:5012 | +-05.0 Intel Corporation Device 2034 | +-05.2 Intel Corporation Sky Lake-E RAS Configuration Registers | +-05.4 Intel Corporation Device 2036 | +-08.0 Intel Corporation Sky Lake-E CHA Registers | +-08.1 Intel Corporation Sky Lake-E CHA Registers | +-08.2 Intel Corporation Sky Lake-E CHA Registers | +-08.3 Intel Corporation Sky Lake-E CHA Registers | +-08.4 Intel Corporation Sky Lake-E CHA Registers | +-08.5 Intel Corporation Sky Lake-E CHA Registers | +-08.6 Intel Corporation Sky Lake-E CHA Registers | +-08.7 Intel Corporation Sky Lake-E CHA Registers | +-09.0 Intel Corporation Sky Lake-E CHA Registers | +-09.1 Intel Corporation Sky Lake-E CHA Registers | +-09.2 Intel Corporation Sky Lake-E CHA Registers | +-09.3 Intel Corporation Sky Lake-E CHA Registers | +-09.4 Intel Corporation Sky Lake-E CHA Registers | +-09.5 Intel Corporation Sky Lake-E CHA Registers | +-09.6 Intel Corporation Sky Lake-E CHA Registers | +-09.7 Intel Corporation Sky Lake-E CHA Registers | +-0a.0 Intel Corporation Sky Lake-E CHA Registers | +-0a.1 Intel Corporation Sky Lake-E CHA Registers | +-0a.2 Intel Corporation Sky Lake-E CHA Registers | +-0a.3 Intel Corporation Sky Lake-E CHA Registers | +-0a.4 Intel Corporation Sky Lake-E CHA Registers | +-0a.5 Intel Corporation Sky Lake-E CHA Registers | +-0a.6 Intel Corporation Sky Lake-E CHA Registers | +-0a.7 Intel Corporation Sky Lake-E CHA Registers | +-0b.0 Intel Corporation Sky Lake-E CHA Registers | +-0b.1 Intel Corporation Sky Lake-E CHA Registers | +-0b.2 Intel Corporation Sky Lake-E CHA Registers | +-0b.3 Intel Corporation Sky Lake-E CHA Registers | +-0e.0 Intel Corporation Sky Lake-E CHA Registers | +-0e.1 Intel Corporation Sky Lake-E CHA Registers | +-0e.2 Intel Corporation Sky Lake-E CHA Registers | +-0e.3 Intel Corporation Sky Lake-E CHA Registers | +-0e.4 Intel Corporation Sky Lake-E CHA Registers | +-0e.5 Intel Corporation Sky Lake-E CHA Registers | +-0e.6 Intel Corporation Sky Lake-E CHA Registers | +-0e.7 Intel Corporation Sky Lake-E CHA Registers | +-0f.0 Intel Corporation Sky Lake-E CHA Registers | +-0f.1 Intel Corporation Sky Lake-E CHA Registers | +-0f.2 Intel Corporation Sky Lake-E CHA Registers | +-0f.3 Intel Corporation Sky Lake-E CHA Registers | +-0f.4 Intel Corporation Sky Lake-E CHA Registers | +-0f.5 Intel Corporation Sky Lake-E CHA Registers | +-0f.6 Intel Corporation Sky Lake-E CHA Registers | +-0f.7 Intel Corporation Sky Lake-E CHA Registers | +-10.0 Intel Corporation Sky Lake-E CHA Registers | +-10.1 Intel Corporation Sky Lake-E CHA Registers | +-10.2 Intel Corporation Sky Lake-E CHA Registers | +-10.3 Intel Corporation Sky Lake-E CHA Registers | +-10.4 Intel Corporation Sky Lake-E CHA Registers | +-10.5 Intel Corporation Sky Lake-E CHA Registers | +-10.6 Intel Corporation Sky Lake-E CHA Registers | +-10.7 Intel Corporation Sky Lake-E CHA Registers | +-11.0 Intel Corporation Sky Lake-E CHA Registers | +-11.1 Intel Corporation Sky Lake-E CHA Registers | +-11.2 Intel Corporation Sky Lake-E CHA Registers | +-11.3 Intel Corporation Sky Lake-E CHA Registers | +-1d.0 Intel Corporation Sky Lake-E CHA Registers | +-1d.1 Intel Corporation Sky Lake-E CHA Registers | +-1d.2 Intel Corporation Sky Lake-E CHA Registers | +-1d.3 Intel Corporation Sky Lake-E CHA Registers | +-1e.0 Intel Corporation Sky Lake-E PCU Registers | +-1e.1 Intel Corporation Sky Lake-E PCU Registers | +-1e.2 Intel Corporation Sky Lake-E PCU Registers | +-1e.3 Intel Corporation Sky Lake-E PCU Registers | +-1e.4 Intel Corporation Sky Lake-E PCU Registers | +-1e.5 Intel Corporation Sky Lake-E PCU Registers | \-1e.6 Intel Corporation Sky Lake-E PCU Registers \-[0000:00]-+-00.0 Intel Corporation Sky Lake-E DMI3 Registers +-04.0 Intel Corporation Sky Lake-E CBDMA Registers +-04.1 Intel Corporation Sky Lake-E CBDMA Registers +-04.2 Intel Corporation Sky Lake-E CBDMA Registers +-04.3 Intel Corporation Sky Lake-E CBDMA Registers +-04.4 Intel Corporation Sky Lake-E CBDMA Registers +-04.5 Intel Corporation Sky Lake-E CBDMA Registers +-04.6 Intel Corporation Sky Lake-E CBDMA Registers +-04.7 Intel Corporation Sky Lake-E CBDMA Registers +-05.0 Intel Corporation Sky Lake-E MM/Vt-d Configuration Registers +-05.2 Intel Corporation Device 2025 +-05.4 Intel Corporation Device 2026 +-08.0 Intel Corporation Sky Lake-E Ubox Registers +-08.1 Intel Corporation Sky Lake-E Ubox Registers +-08.2 Intel Corporation Sky Lake-E Ubox Registers +-11.0 Intel Corporation Device a1ec +-11.1 Intel Corporation Device a1ed +-11.5 Intel Corporation Lewisburg SSATA Controller [AHCI mode] +-14.0 Intel Corporation Lewisburg USB 3.0 xHCI Controller +-14.2 Intel Corporation Lewisburg Thermal Subsystem +-16.0 Intel Corporation Lewisburg CSME: HECI #1 +-16.1 Intel Corporation Lewisburg CSME: HECI #2 +-16.4 Intel Corporation Lewisburg CSME: HECI #3 +-17.0 Intel Corporation Lewisburg SATA Controller [AHCI mode] +-1c.0-[01-02]----00.0-[02]----00.0 Matrox Electronics Systems Ltd. MGA G200e [Pilot] ServerEngines (SEP1) +-1f.0 Intel Corporation Lewisburg LPC Controller +-1f.2 Intel Corporation Lewisburg PMC +-1f.3 Intel Corporation Lewisburg MROM 0 +-1f.4 Intel Corporation Lewisburg SMBus +-1f.5 Intel Corporation Lewisburg SPI Controller \-1f.6 Intel Corporation Ethernet Connection (3) I219-LM
thanks, Gerd _______________________________________________ SeaBIOS mailing list -- seabios@seabios.org To unsubscribe send an email to seabios-leave@seabios.org
So the question is whenever there are *really* multiple roots
Without the patch, I got: "Found 33 PCI devices (max PCI bus is 02)"
Can you run "lspci -vt" and post the output here?
Here is the output of lspci -vt:
-+-[0000:b2]-+-05.0 Intel Corporation Device 2034 | +-05.2 Intel Corporation Sky Lake-E RAS Configuration Registers [ ... ]
+-[0000:64]-+-00.0-[65-68]----00.0-[66-68]----03.0-[67-68]--+-00.0 Intel Corporation Ethernet Connection X722 for 10GbE SFP+ | | +-00.1 Intel Corporation Ethernet Connection X722 for 10GbE SFP+ [ ... ]
+-[0000:16]-+-03.0-[17]----00.0 Device 1987:5012 | +-05.0 Intel Corporation Device 2034 [ ... ]
\-[0000:00]-+-00.0 Intel Corporation Sky Lake-E DMI3 Registers +-04.0 Intel Corporation Sky Lake-E CBDMA Registers [ ... ] +-1c.0-[01-02]----00.0-[02]----00.0 Matrox Electronics Systems Ltd. MGA G200e [Pilot] ServerEngines (SEP1) [ ... ]
Ok, so there are really multiple pci roots, and seabios finds the first only without setting extraroots. Can we turn this off on qemu? It is not needed there and slows down the boot a bit. "if (CONFIG_CSM && !CONFIG_QEMU_HARDWARE)" should do the trick. cheers, Gerd
participants (2)
-
Gerd Hoffmann -
Your Real Name