June 2025 - SeaBIOS - mail.coreboot.org

regression: cannot boot from nvme anymore, disabling 64bit pci io window helps
by Marek Marczykowski-Górecki July 7, 2026

July 7, 2026

Hi, After an update some time ago, a VM wit 8GB RAM cannot boot from nvme anymore. QEMU cmdline: /usr/bin/qemu-system-x86_64 \ -chardev ringbuf,id=serial0,logfile=serial0,logappend=on \ -serial chardev:serial0 \ -m 8192 \ -enable-kvm \ -vnc :2,share=force-shared \ -blockdev driver=file,node-name=hd0-file,filename=disk.qcow2,cache.no-flush=on,discard=unmap \ -blockdev driver=qcow2,node-name=hd0,file=hd0-file,cache.no-flush=on,discard=unmap \ -device nvme,id=hd0-device,drive=hd0,serial=hd0 \ -chardev stdio,id=seabios -device isa-debugcon,iobase=0x402,chardev=seabios \ -bios /home/user/seabios/out/bios.bin There is nothing fancy on the disk, just standard grub2 setup, but also I believe it doesn't matter, as it doesn't even reach grub. When it fails, the seabios log contains: PCI: 64: 0000038000000000 - 0000038040000000 PCI: map device bdf=00:04.0 bar 0, addr 38000000000, size 00004000 [mem] ... Searching bootorder for: /pci@i0cf8/isa@1/fdc@03f0/floppy@0 ATA controller 1 at 1f0/3f4/0 (irq 14 dev 9) ATA controller 2 at 170/374/0 (irq 15 dev 9) Searching bootorder for: HALT Can not map memory bar over 4Gig ... Boot failed: could not read the boot disk Working version has this instead: PCI: map device bdf=00:04.0 bar 0, addr febf0000, size 00004000 [mem] ... Booting from Hard Disk... Booting from 0000:7c00 00:04.0 is the nvme. I'm attaching full logs for both cases. Bisect shows: 96a8d130a8c2e908e357ce62cd713f2cc0b0a2eb is the first bad commit commit 96a8d130a8c2e908e357ce62cd713f2cc0b0a2eb (HEAD) Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Fri Sep 9 10:17:15 2022 +0200 be less conservative with the 64bit pci io window Current seabios code will only enable and use the 64bit pci io window in case it runs out of space in the 32bit pci mmio window below 4G. This patch will also enable the 64bit pci io window when (a) RAM above 4G is present, and (b) the physical address space size is known, and (c) seabios is running on a 64bit capable processor. This operates with the assumption that guests which are ok with memory above 4G most likely can handle mmio above 4G too. In case the 64bit pci io window is enabled also assign more memory to prefetchable pci bridge windows and the complete 64bit pci io window. The total mmio window size is 1/8 of the physical address space. Minimum bridge windows size is 1/256 of the total mmio window size. Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> I've tried the recent "[PATCH] limit address space used for pci devices, part two" patch from the ML, but it doesn't help. OTOH, the series with "only enable 64bit pci io window when RAM >64G" does help. -- Best Regards, Marek Marczykowski-Górecki Invisible Things Lab

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[PATCH] src/sercon.c: fix the keycodes for F11 and F12
by Andrei Purdea July 1, 2025

July 1, 2025

Hello, This fixes what happens when F11/F12 is sent via serial port. The existing code already correctly detected the byte sequence that was sent on the serial connection, however it translated it to incorrect keycode. The termseq table must map to "DOS scan codes". The incorrect value matched "PS2 set1 scan codes" for F11 and F12, so I think this was simply an implementation mistake. I have tested the attached patch on real hardware. I am not the author of the patch, the original change can be found here: https://github.com/Dasharo/SeaBIOS/commit/0f4530859f11b3235b7d6163388f19577… Thanks, Andrei

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MSR_IA32_FEATURE_CONTROL on vCPU hotplug
by Andrey Zhadchenko June 12, 2025

June 12, 2025

Hello! Looks like MSR_IA32_FEATURE_CONTROL is not set by firmware on CPU hotplug. This crashes Windows kvm (cpu=host) guests on processors with SGX, as win expects to see bit #18 on a new CPU in this register. Linux got this issue patched in 5.6 (1db2a6e1e29f) to set msr 3a itself in case firmware forgot to lock it. Host kernel tracing events looks like this: echo 1 > /sys/kernel/tracing/events/kvm/kvm_msr/enable ... cat /sys/kernel/tracing/trace | grep 3a CPU 0/KVM-16856 [007] ....... 380.398696: kvm_msr: msr_write 3a = 0x40005 <Guest firmware write> CPU 3/KVM-16859 [001] ....... 380.398914: kvm_msr: msr_write 3a = 0x40005 <Guest firmware write> CPU 2/KVM-16858 [006] ....... 380.398964: kvm_msr: msr_write 3a = 0x40005 <Guest firmware write> CPU 1/KVM-16857 [004] ....... 380.399007: kvm_msr: msr_write 3a = 0x40005 <Guest firmware write> CPU 0/KVM-16856 [001] ....... 384.497714: kvm_msr: msr_read 3a = 0x40005 <Guest OS read> CPU 0/KVM-16856 [001] ....... 384.497716: kvm_msr: msr_read 3a = 0x40005 CPU 1/KVM-16857 [007] ....... 384.934791: kvm_msr: msr_read 3a = 0x40005 CPU 1/KVM-16857 [007] ....... 384.934793: kvm_msr: msr_read 3a = 0x40005 CPU 2/KVM-16858 [002] ....... 384.977871: kvm_msr: msr_read 3a = 0x40005 CPU 2/KVM-16858 [002] ....... 384.977873: kvm_msr: msr_read 3a = 0x40005 CPU 3/KVM-16859 [006] ....... 385.021217: kvm_msr: msr_read 3a = 0x40005 CPU 3/KVM-16859 [006] ....... 385.021220: kvm_msr: msr_read 3a = 0x40005 <here vCPU is hotplugged and firmware should also do msr_write> CPU 4/KVM-17500 [002] ....... 453.733743: kvm_msr: msr_read 3a = 0x0 <- new vcpu, Windows reads and expects to see 0x40005 here instead of default 0> CPU 4/KVM-17500 [002] ....... 453.733745: kvm_msr: msr_read 3a = 0x0 <windows crash> I tried to fix that myself, but it got me nowhere. I see that after SIPI CPUs start at handle_smp(), but only during startup. After that looks like ASL code manages hotplug. But I was not able to follow if it even executes bios code or just jumps to somewhere in the OS. I would appreciate any advice how can I set MSR_IA32_FEATURE_CONTROL on newly hotplugged CPUs. Kind regards Andrey

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[ANNOUNCE] SeaBIOS 1.17.0
by Kevin O'Connor June 10, 2025

June 10, 2025

The 1.17.0 version of SeaBIOS has now been released. For more information on the release, please see: https://seabios.org/Releases New in this release: * Prefer PCI IO allocations above 4Gig on 64bit capable machines. * Multiple simultaneous USB keyboard and mouse support. * Legacy support for internally generated ACPI tables has been removed. * SeaVGABIOS support for VBE get/set palette data. * Several bug fixes and code cleanups. For information on obtaining SeaBIOS, please see: https://seabios.org/Download ===== git shortlog -n rel-1.16.0..rel-1.17.0 ===== Gerd Hoffmann (17): malloc: use variable for ZoneHigh size malloc: use large ZoneHigh when there is enough memory virtio-blk: use larger default request size disable array bounds warning better kvm detection detect physical address space size move 64bit pci window to end of address space be less conservative with the 64bit pci io window qemu: log reservations in fw_cfg e820 table check for e820 conflict limit address space used for pci devices. limit address space used for pci devices, part two drop obsolete acpi table code drop acpi tables and hex includes add romfile_loadbool() update pci_pad_mem64 handling ahci: add controller reset Kevin O'Connor (14): vgasrc: Use curmode_g instead of vmode_g when mode is the current video mode vgasrc: Rename vgahw_get_linesize() to vgahw_minimum_linelength() stdvgamodes: No need to store pelmask in vga_modes[] stdvgamodes: Improve naming of dac palette tables stdvga: Rename CGA palette functions stdvga: Add comments to interface functions in stdvga.c stdvga: Rename stdvga_toggle_intensity() to stdvga_set_palette_blinking() stdvga: Rework stdvga palette index paging interface functions stdvga: Rename stdvga_set_text_block_specifier() to stdvga_set_font_location() stdvga: Rename stdvga_set_scan_lines() to stdvga_set_character_height() stdvga: Rename stdvga_get_vde() to stdvga_get_vertical_size() stdvga: Add stdvga_set_vertical_size() helper function stdvgaio: Only read/write one color palette entry at a time docs: Note v1.17.0 release Mark Cave-Ayland (5): esp-scsi: flush FIFO before sending SCSI command esp-scsi: check for INTR_BS/INTR_FC instead of STAT_TC for command completion esp-scsi: handle non-DMA SCSI commands with no data phase esp-scsi: terminate DMA transfer when ESP data transfer completes esp-scsi: indicate acceptance of MESSAGE IN phase data Daniel Verkamp (3): vbe: Add VBE 2.0+ OemData field to struct vbe_info vgasrc: round up save/restore size vbe: implement function 09h (get/set palette data) Daniel Khodabakhsh (2): boot: Force display of the boot menu when boot-menu-wait is a negative number usb-hid: Support multiple USB HID devices by storing them in a linked list Igor Mammedov (2): acpi: parse Alias object fix smbios blob length overflow Volker Rümelin (2): pci: refactor the pci_config_*() functions reset: force standard PCI configuration access Xuan Zhuo (2): virtio-mmio: read/write the hi 32 features for mmio virtio: finalize features before using device Andrej Kruták (1): Add AHCI Power ON + ICC_ACTIVE into port setup code Daniil Tatianin (1): pciinit: don't misalign large BARs David Woodhouse (1): xen: require Xen info structure at 0x1000 to detect Xen Jiaxun Yang (1): ahci: Fix hangs due to controller reset José Martínez (1): Fix high memory zone initialization in CSM mode Lukas Stockner via SeaBIOS (1): virtio-blk: Fix integer overflow for large max IO sizes Max Tottenham (1): Add LBA 64bit support for reads beyond 2TB. Niklas Cassel via SeaBIOS (1): ahci: handle TFES irq correctly Qi Zhou (1): usb: fix wrong init of keyboard/mouse's if first interface is not boot protocol Steven Price (1): vgabios: Fix generating modes list for static_functionality Tony Titus via SeaBIOS (1): Increase BUILD_MAX_E820 to 128 Xiaofei Lee (1): virtio-blk: Fix incorrect type conversion in virtio_blk_op() nikolar via SeaBIOS (1): kconfig: fix the check-lxdialog.sh to work with gcc 14+

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[PATCH v2 0/2] add guest hint for memory layout, take three
by Gerd Hoffmann June 3, 2025

June 3, 2025

Gerd Hoffmann (2): add romfile_loadbool() update pci_pad_mem64 handling src/romfile.h | 1 + src/fw/pciinit.c | 13 ++++++++++--- src/romfile.c | 23 +++++++++++++++++++++++ 3 files changed, 34 insertions(+), 3 deletions(-) -- 2.47.0

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[PATCH RESEND 0/7] Build system improvements
by Jiaxun Yang June 2, 2025

June 2, 2025

Hi all, This series improved SeaBIOS build system in various aspects. Most notably, it makes cross compiling on MacOS Arm64 with x86_64-elf- toolchain possible. It also fixed various issues exposed when I was trying to clang build work. Although I eventually give up. Thanks Signed-off-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com> --- Jiaxun Yang (7): Remove remaining ACPI tooling bits Makefile: Don't use $(CC) as default hostcc Makefile: Invoke AS, CPP and LD via CC Makefile: Allow more linux style knobs asm-offset: Refresh definations from Linux scripts: Use python3 as python Clear clang warnings Makefile | 47 ++--- scripts/acpi_extract.py | 366 ------------------------------------- scripts/acpi_extract_preprocess.py | 41 ----- scripts/buildrom.py | 2 +- scripts/buildversion.py | 2 +- scripts/checkrom.py | 2 +- scripts/checkstack.py | 2 +- scripts/checksum.py | 2 +- scripts/encodeint.py | 2 +- scripts/gen-offsets.sh | 7 +- scripts/kconfig/Makefile | 6 +- scripts/layoutrom.py | 2 +- scripts/ldnoexec.py | 2 +- scripts/readserial.py | 2 +- scripts/test-build.sh | 12 +- scripts/transdump.py | 2 +- scripts/vgafixup.py | 2 +- src/gen-defs.h | 8 +- src/hw/serialio.c | 1 + src/hw/usb-ohci.c | 2 +- src/hw/virtio-blk.c | 2 +- src/std/LegacyBios.h | 4 +- 22 files changed, 59 insertions(+), 459 deletions(-) --- base-commit: 9029a010ec413e6c3c0eb52c29c252a5b9a9f774 change-id: 20250528-build-eb5b4a8830b7 Best regards, -- Jiaxun Yang <jiaxun.yang(a)flygoat.com>

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[PATCH v2] ahci: Fix hangs due to controller reset
by Jiaxun Yang June 2, 2025

June 2, 2025

After adding AHCI controller reset functionality there are multiple reports on AHCI booting regression. As per my experiments on various machines, to reset controller properly it is necessary to poll HOST_CTL_RESET bit until it's clear. It is also required to read back HOST_CTL after changing HOST_CTL_AHCI_EN bits to ensure the controller has accepted write. Tested on ASMedia ASM1061, Intel H61 native SATA and AMD Phoenix native SATA. Link: https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/RDNRKW… Link: https://github.com/FlyGoat/csmwrap/issues/14 Fixes: 8863cbbd15a7 ("ahci: add controller reset") Signed-off-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com> Acked-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- To: seabios(a)seabios.org --- Changes in v2: - Commit message (Paul Menzel) - Link to v1: https://lore.kernel.org/r/20250522-ahci-v1-1-a9de195854f5@flygoat.com --- src/hw/ahci.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/src/hw/ahci.c b/src/hw/ahci.c index 2285d33d4ae21335e5222ab04608685b5bff3763..7e7a03ddd010d53fa439c8ca49505a2da00241f4 100644 --- a/src/hw/ahci.c +++ b/src/hw/ahci.c @@ -660,8 +660,23 @@ ahci_controller_setup(struct pci_device *pci) pci_enable_busmaster(pci); - ahci_ctrl_writel(ctrl, HOST_CTL, HOST_CTL_RESET); - ahci_ctrl_writel(ctrl, HOST_CTL, HOST_CTL_AHCI_EN); + u32 val = ahci_ctrl_readl(ctrl, HOST_CTL); + ahci_ctrl_writel(ctrl, HOST_CTL, val | HOST_CTL_RESET); + u32 end = timer_calc(AHCI_RESET_TIMEOUT); + for (;;) { + val = ahci_ctrl_readl(ctrl, HOST_CTL); + if (!(val & HOST_CTL_RESET)) + break; + if (timer_check(end)) { + warn_timeout(); + dprintf(1, "AHCI: controller reset failed\n"); + free(ctrl); + return; + } + yield(); + } + ahci_ctrl_writel(ctrl, HOST_CTL, val | HOST_CTL_AHCI_EN); + (void)ahci_ctrl_readl(ctrl, HOST_CTL); /* Flush */ ctrl->caps = ahci_ctrl_readl(ctrl, HOST_CAP); ctrl->ports = ahci_ctrl_readl(ctrl, HOST_PORTS_IMPL); --- base-commit: 9029a010ec413e6c3c0eb52c29c252a5b9a9f774 change-id: 20250522-ahci-8ac63999b084 Best regards, -- Jiaxun Yang <jiaxun.yang(a)flygoat.com>

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