May 2025 - SeaBIOS - mail.coreboot.org

[PATCH v2 0/2] add guest hint for memory layout, take three
by Gerd Hoffmann June 3, 2025

June 3, 2025

Gerd Hoffmann (2): add romfile_loadbool() update pci_pad_mem64 handling src/romfile.h | 1 + src/fw/pciinit.c | 13 ++++++++++--- src/romfile.c | 23 +++++++++++++++++++++++ 3 files changed, 34 insertions(+), 3 deletions(-) -- 2.47.0

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[PATCH RESEND 0/7] Build system improvements
by Jiaxun Yang June 2, 2025

June 2, 2025

Hi all, This series improved SeaBIOS build system in various aspects. Most notably, it makes cross compiling on MacOS Arm64 with x86_64-elf- toolchain possible. It also fixed various issues exposed when I was trying to clang build work. Although I eventually give up. Thanks Signed-off-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com> --- Jiaxun Yang (7): Remove remaining ACPI tooling bits Makefile: Don't use $(CC) as default hostcc Makefile: Invoke AS, CPP and LD via CC Makefile: Allow more linux style knobs asm-offset: Refresh definations from Linux scripts: Use python3 as python Clear clang warnings Makefile | 47 ++--- scripts/acpi_extract.py | 366 ------------------------------------- scripts/acpi_extract_preprocess.py | 41 ----- scripts/buildrom.py | 2 +- scripts/buildversion.py | 2 +- scripts/checkrom.py | 2 +- scripts/checkstack.py | 2 +- scripts/checksum.py | 2 +- scripts/encodeint.py | 2 +- scripts/gen-offsets.sh | 7 +- scripts/kconfig/Makefile | 6 +- scripts/layoutrom.py | 2 +- scripts/ldnoexec.py | 2 +- scripts/readserial.py | 2 +- scripts/test-build.sh | 12 +- scripts/transdump.py | 2 +- scripts/vgafixup.py | 2 +- src/gen-defs.h | 8 +- src/hw/serialio.c | 1 + src/hw/usb-ohci.c | 2 +- src/hw/virtio-blk.c | 2 +- src/std/LegacyBios.h | 4 +- 22 files changed, 59 insertions(+), 459 deletions(-) --- base-commit: 9029a010ec413e6c3c0eb52c29c252a5b9a9f774 change-id: 20250528-build-eb5b4a8830b7 Best regards, -- Jiaxun Yang <jiaxun.yang(a)flygoat.com>

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[PATCH v2] ahci: Fix hangs due to controller reset
by Jiaxun Yang June 2, 2025

June 2, 2025

After adding AHCI controller reset functionality there are multiple reports on AHCI booting regression. As per my experiments on various machines, to reset controller properly it is necessary to poll HOST_CTL_RESET bit until it's clear. It is also required to read back HOST_CTL after changing HOST_CTL_AHCI_EN bits to ensure the controller has accepted write. Tested on ASMedia ASM1061, Intel H61 native SATA and AMD Phoenix native SATA. Link: https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/RDNRKW… Link: https://github.com/FlyGoat/csmwrap/issues/14 Fixes: 8863cbbd15a7 ("ahci: add controller reset") Signed-off-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com> Acked-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- To: seabios(a)seabios.org --- Changes in v2: - Commit message (Paul Menzel) - Link to v1: https://lore.kernel.org/r/20250522-ahci-v1-1-a9de195854f5@flygoat.com --- src/hw/ahci.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/src/hw/ahci.c b/src/hw/ahci.c index 2285d33d4ae21335e5222ab04608685b5bff3763..7e7a03ddd010d53fa439c8ca49505a2da00241f4 100644 --- a/src/hw/ahci.c +++ b/src/hw/ahci.c @@ -660,8 +660,23 @@ ahci_controller_setup(struct pci_device *pci) pci_enable_busmaster(pci); - ahci_ctrl_writel(ctrl, HOST_CTL, HOST_CTL_RESET); - ahci_ctrl_writel(ctrl, HOST_CTL, HOST_CTL_AHCI_EN); + u32 val = ahci_ctrl_readl(ctrl, HOST_CTL); + ahci_ctrl_writel(ctrl, HOST_CTL, val | HOST_CTL_RESET); + u32 end = timer_calc(AHCI_RESET_TIMEOUT); + for (;;) { + val = ahci_ctrl_readl(ctrl, HOST_CTL); + if (!(val & HOST_CTL_RESET)) + break; + if (timer_check(end)) { + warn_timeout(); + dprintf(1, "AHCI: controller reset failed\n"); + free(ctrl); + return; + } + yield(); + } + ahci_ctrl_writel(ctrl, HOST_CTL, val | HOST_CTL_AHCI_EN); + (void)ahci_ctrl_readl(ctrl, HOST_CTL); /* Flush */ ctrl->caps = ahci_ctrl_readl(ctrl, HOST_CAP); ctrl->ports = ahci_ctrl_readl(ctrl, HOST_PORTS_IMPL); --- base-commit: 9029a010ec413e6c3c0eb52c29c252a5b9a9f774 change-id: 20250522-ahci-8ac63999b084 Best regards, -- Jiaxun Yang <jiaxun.yang(a)flygoat.com>

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[PATCH] ahci: Controller reset fixes
by Jiaxun Yang May 26, 2025

May 26, 2025

After adding AHCI controller functionality there are multiple reports on AHCI booting regression. As per my experiments on various machines, to reset controller properly it is necessary to poll HOST_CTL_RESET bit until it's clear. It is also required to read back HOST_CTL after changing HOST_CTL_AHCI_EN bits to ensure the controller has accepted write. Tested on ASMedia ASM1061, Intel H61 native SATA and AMD Phoenix native SATA. Link: https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/RDNRKW… Link: https://github.com/FlyGoat/csmwrap/issues/14 Fixes: 8863cbbd15a7 ("ahci: add controller reset") Signed-off-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com> --- To: seabios(a)seabios.org --- src/hw/ahci.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/src/hw/ahci.c b/src/hw/ahci.c index 2285d33d4ae21335e5222ab04608685b5bff3763..7e7a03ddd010d53fa439c8ca49505a2da00241f4 100644 --- a/src/hw/ahci.c +++ b/src/hw/ahci.c @@ -660,8 +660,23 @@ ahci_controller_setup(struct pci_device *pci) pci_enable_busmaster(pci); - ahci_ctrl_writel(ctrl, HOST_CTL, HOST_CTL_RESET); - ahci_ctrl_writel(ctrl, HOST_CTL, HOST_CTL_AHCI_EN); + u32 val = ahci_ctrl_readl(ctrl, HOST_CTL); + ahci_ctrl_writel(ctrl, HOST_CTL, val | HOST_CTL_RESET); + u32 end = timer_calc(AHCI_RESET_TIMEOUT); + for (;;) { + val = ahci_ctrl_readl(ctrl, HOST_CTL); + if (!(val & HOST_CTL_RESET)) + break; + if (timer_check(end)) { + warn_timeout(); + dprintf(1, "AHCI: controller reset failed\n"); + free(ctrl); + return; + } + yield(); + } + ahci_ctrl_writel(ctrl, HOST_CTL, val | HOST_CTL_AHCI_EN); + (void)ahci_ctrl_readl(ctrl, HOST_CTL); /* Flush */ ctrl->caps = ahci_ctrl_readl(ctrl, HOST_CAP); ctrl->ports = ahci_ctrl_readl(ctrl, HOST_PORTS_IMPL); --- base-commit: 9029a010ec413e6c3c0eb52c29c252a5b9a9f774 change-id: 20250522-ahci-8ac63999b084 Best regards, -- Jiaxun Yang <jiaxun.yang(a)flygoat.com>

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[PATCH] ahci: Controller reset fixes
by Jiaxun Yang May 22, 2025

May 22, 2025

After adding AHCI controller functionality there are multiple reports on AHCI booting regression. As per my experiments on various machines, to reset controller properly it is necessary to poll HOST_CTL_RESET bit until it's clear. It is also required to read back HOST_CTL after changing HOST_CTL_AHCI_EN bits to ensure the controller has accepted write. Tested on ASMedia ASM1061, Intel H61 native SATA and AMD Phoenix native SATA. Link: https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/RDNRKW… Link: https://github.com/FlyGoat/csmwrap/issues/14 Fixes: 8863cbbd15a7 ("ahci: add controller reset") Signed-off-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com> --- To: seabios(a)seabios.org --- src/hw/ahci.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/src/hw/ahci.c b/src/hw/ahci.c index 2285d33d4ae21335e5222ab04608685b5bff3763..7e7a03ddd010d53fa439c8ca49505a2da00241f4 100644 --- a/src/hw/ahci.c +++ b/src/hw/ahci.c @@ -660,8 +660,23 @@ ahci_controller_setup(struct pci_device *pci) pci_enable_busmaster(pci); - ahci_ctrl_writel(ctrl, HOST_CTL, HOST_CTL_RESET); - ahci_ctrl_writel(ctrl, HOST_CTL, HOST_CTL_AHCI_EN); + u32 val = ahci_ctrl_readl(ctrl, HOST_CTL); + ahci_ctrl_writel(ctrl, HOST_CTL, val | HOST_CTL_RESET); + u32 end = timer_calc(AHCI_RESET_TIMEOUT); + for (;;) { + val = ahci_ctrl_readl(ctrl, HOST_CTL); + if (!(val & HOST_CTL_RESET)) + break; + if (timer_check(end)) { + warn_timeout(); + dprintf(1, "AHCI: controller reset failed\n"); + free(ctrl); + return; + } + yield(); + } + ahci_ctrl_writel(ctrl, HOST_CTL, val | HOST_CTL_AHCI_EN); + (void)ahci_ctrl_readl(ctrl, HOST_CTL); /* Flush */ ctrl->caps = ahci_ctrl_readl(ctrl, HOST_CAP); ctrl->ports = ahci_ctrl_readl(ctrl, HOST_PORTS_IMPL); --- base-commit: 9029a010ec413e6c3c0eb52c29c252a5b9a9f774 change-id: 20250522-ahci-8ac63999b084 Best regards, -- Jiaxun Yang <jiaxun.yang(a)flygoat.com>

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PATCH: Fix AHCI init regression on the coreboot payload
by Leah Rowe May 22, 2025

May 22, 2025

Hello SeaBIOS community, Please look at the patch I've attached to this email. It fixes a regression recently introduced in SeaBIOS, introduced by SeaBIOS git commit ID 8863cbbd. I request that this patch by merged, and I will now explain why. A recent SeaBIOS patch (commit 8863cbbd) adds AHCI controller reset prior to enablement, as a way to make SeaBIOS's AHCI driver work correctly on CSM-based setups. However, that commit (commit 8863cbbd) broke AHCI initialisation on the Lenovo ThinkPad T420 when testing SeaBIOS as a coreboot payload. It caused an AHCI timeout. I tried to include these logs on the mailing list but it came back telling me my message was too big. Anyways To mitigate this, I have provided for SeaBIOS a patch to this email (0004-ahci-Only-reset-controller-on-CSM.patch). My patch retains the new behaviour, resetting the AHCI controller prior to enablement, so that it will continue to function correctly on CSM, but it *only* applies that new behaviour on CSM setups. With my patch, the *old* behaviour is used (enable the controller from its current state), if a CSM is not in use. This was confirmed to work correctly, fixing the issue when re-tested on the same ThinkPad T420. I am also using this fix in Libreboot, see: https://browse.libreboot.org/lbmk.git/commit/?id=c073ee9d4fc4a631c16ff681bb… That's where the patch is from. I put it there first. SeaBIOS devs are welcome to merge this if they wish. -- Company director, Minifree Ltd Registered in England, No. 9361826 | VAT No. GB202190462 Registered Office: 19 Hilton Road, Canvey Island, Essex SS8 9QA, UK

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PATCH: Fix AHCI init regression on the coreboot payload
by Leah Rowe May 1, 2025

May 1, 2025

Hello SeaBIOS community, Please look at the patch I've attached to this email. It fixes a regression recently introduced in SeaBIOS, introduced by SeaBIOS git commit ID 8863cbbd. I request that this patch by merged, and I will now explain why. A recent SeaBIOS patch (commit 8863cbbd) adds AHCI controller reset prior to enablement, as a way to make SeaBIOS's AHCI driver work correctly on CSM-based setups. However, this patch (commit 8863cbbd) broke AHCI initialisation on the Lenovo ThinkPad T420 when testing SeaBIOS as a coreboot payload. To mitigate this, I have provided for SeaBIOS a patch to this email (0004-ahci-Only-reset-controller-on-CSM.patch). My patch retains the new behaviour, resetting the AHCI controller prior to enablement, so that it will continue to function correctly on CSM, but it *only* applies that new behaviour on CSM setups. With my patch, the *old* behaviour is used (enable the controller from its current state), if a CSM is not in use. This was confirmed to work correctly, fixing the issue when re-tested on the same ThinkPad T420. In addition to the .patch file, I've attached three log files, showing coreboot's cbmem log which includes the SeaBIOS debug output. I will say what each of the files are: Bug fix: 0004-ahci-Only-reset-controller-on-CSM.patch broken.log is SeaBIOS at revision 9029a010, which includes commit 8863cbbd that broke AHCI init on coreboot with seabios payload. working.log is SeaBIOS, rolled back to commit ID df9dd418, which is just before the offending commit 8863cbbd; at df9dd418, AHCI init on T420 with seabios coreboot payload works fine, but this would of course break the CSM setup. withpatch.log is SeaBIOS at 8863cbbd, but with my fix applied. With "broken.log", you can see that the AHCI init times out and fails. On working.log and withpatch.log, AHCI init works perfectly. withpatch.log is what you get with my .patch file applied. Finally, the "libgfxinit" file is the SeaBIOS configuration file in use. This config file is the same, on each of the three SeaBIOS revisions: old one prior to AHCI reset patch, and then the one with the AHCI reset patch, and then finally with the reset patch and my patch on top. I am also using this fix in Libreboot, see: https://browse.libreboot.org/lbmk.git/commit/?id=c073ee9d4fc4a631c16ff681bb… The patch file and config attached are pulled from Libreboot lbmk.git, which patches SeaBIOS. The logs were provided to me by a tester of a recent Libreboot release, where I've now fixed this bug. -- Company director, Minifree Ltd Registered in England, No. 9361826 | VAT No. GB202190462 Registered Office: 19 Hilton Road, Canvey Island, Essex SS8 9QA, UK

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