January 2025 - SeaBIOS - mail.coreboot.org

regression: cannot boot from nvme anymore, disabling 64bit pci io window helps
by Marek Marczykowski-Górecki July 7, 2026

July 7, 2026

Hi, After an update some time ago, a VM wit 8GB RAM cannot boot from nvme anymore. QEMU cmdline: /usr/bin/qemu-system-x86_64 \ -chardev ringbuf,id=serial0,logfile=serial0,logappend=on \ -serial chardev:serial0 \ -m 8192 \ -enable-kvm \ -vnc :2,share=force-shared \ -blockdev driver=file,node-name=hd0-file,filename=disk.qcow2,cache.no-flush=on,discard=unmap \ -blockdev driver=qcow2,node-name=hd0,file=hd0-file,cache.no-flush=on,discard=unmap \ -device nvme,id=hd0-device,drive=hd0,serial=hd0 \ -chardev stdio,id=seabios -device isa-debugcon,iobase=0x402,chardev=seabios \ -bios /home/user/seabios/out/bios.bin There is nothing fancy on the disk, just standard grub2 setup, but also I believe it doesn't matter, as it doesn't even reach grub. When it fails, the seabios log contains: PCI: 64: 0000038000000000 - 0000038040000000 PCI: map device bdf=00:04.0 bar 0, addr 38000000000, size 00004000 [mem] ... Searching bootorder for: /pci@i0cf8/isa@1/fdc@03f0/floppy@0 ATA controller 1 at 1f0/3f4/0 (irq 14 dev 9) ATA controller 2 at 170/374/0 (irq 15 dev 9) Searching bootorder for: HALT Can not map memory bar over 4Gig ... Boot failed: could not read the boot disk Working version has this instead: PCI: map device bdf=00:04.0 bar 0, addr febf0000, size 00004000 [mem] ... Booting from Hard Disk... Booting from 0000:7c00 00:04.0 is the nvme. I'm attaching full logs for both cases. Bisect shows: 96a8d130a8c2e908e357ce62cd713f2cc0b0a2eb is the first bad commit commit 96a8d130a8c2e908e357ce62cd713f2cc0b0a2eb (HEAD) Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Fri Sep 9 10:17:15 2022 +0200 be less conservative with the 64bit pci io window Current seabios code will only enable and use the 64bit pci io window in case it runs out of space in the 32bit pci mmio window below 4G. This patch will also enable the 64bit pci io window when (a) RAM above 4G is present, and (b) the physical address space size is known, and (c) seabios is running on a 64bit capable processor. This operates with the assumption that guests which are ok with memory above 4G most likely can handle mmio above 4G too. In case the 64bit pci io window is enabled also assign more memory to prefetchable pci bridge windows and the complete 64bit pci io window. The total mmio window size is 1/8 of the physical address space. Minimum bridge windows size is 1/256 of the total mmio window size. Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> I've tried the recent "[PATCH] limit address space used for pci devices, part two" patch from the ML, but it doesn't help. OTOH, the series with "only enable 64bit pci io window when RAM >64G" does help. -- Best Regards, Marek Marczykowski-Górecki Invisible Things Lab

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[PATCH v2 0/2] add guest hint for memory layout, take three
by Gerd Hoffmann June 3, 2025

June 3, 2025

Gerd Hoffmann (2): add romfile_loadbool() update pci_pad_mem64 handling src/romfile.h | 1 + src/fw/pciinit.c | 13 ++++++++++--- src/romfile.c | 23 +++++++++++++++++++++++ 3 files changed, 34 insertions(+), 3 deletions(-) -- 2.47.0

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[PATCH] Fix AHCI Disk Detection when using EDK2 CSM
by Christopher Lentocha March 10, 2025

March 10, 2025

For whatever reason, when you compile SeaBIOS in Csm16 mode, and use it under EDK2's OvmfPkg, the ATA_CMD_IDENTIFY_PACKET_DEVICE command doesn't work properly, therefore, SeaBIOS detects the "SATA HARDDISK" as a "SATA CDROM" device, in QEMU. Despite the Tianocore developers seem to have removed support for Csm16 some time ago, if we decide to remove Csm16 mode in SeaBIOS in favor of that, at least we have the last commit of Csm16 working properly and not half-broken. In order to fix this bug, I decided to add another command, that command being ATA_CMD_DEVICE_RESET, right before the ATA_CMD_IDENTIFY_PACKET_DEVICE command is called. Signed-off-by: Christopher Lentocha <christopherericlentocha(a)gmail.com> --- src/hw/ahci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/hw/ahci.c b/src/hw/ahci.c index 4f0f640..e0864fa 100644 --- a/src/hw/ahci.c +++ b/src/hw/ahci.c @@ -484,7 +484,8 @@ static int ahci_port_setup(struct ahci_port_s *port) /* start device */ cmd |= PORT_CMD_START; ahci_port_writel(ctrl, pnr, PORT_CMD, cmd); - + sata_prep_simple(&port->cmd->fis, ATA_CMD_DEVICE_RESET); + ahci_command(port, 0, 0, buffer, sizeof(buffer)); sata_prep_simple(&port->cmd->fis, ATA_CMD_IDENTIFY_PACKET_DEVICE); rc = ahci_command(port, 0, 0, buffer, sizeof(buffer)); if (rc == 0) { -- 2.38.1

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[PATCH] NVRAM bootorder
by Timothy Kenno Handojo Feb. 13, 2025

Feb. 13, 2025

Revision from a previous patch. Sorry it took so long. This change allows seabios to load bootorder not only from CBFS but also from the NVRAM as well, making use of coreboot's cmos.layout. Tested on QEMU Q35 From 3aee65ff1a9d5926ff18fa0770362e59e8b52257 Mon Sep 17 00:00:00 2001 From: Timothy Kenno Handojo <timkenhan(a)mailbox.org> Date: Wed, 22 Jan 2025 14:40:18 +0700 Subject: [PATCH] boot: Allow setting bootorder from CMOS entry The original bootorder from CBFS remains, but takes lower priority. Signed-off-by: Timothy Kenno Handojo <timkenhan(a)mailbox.org> --- Makefile | 2 +- src/boot.c | 9 +++- src/nvram.c | 144 ++++++++++++++++++++++++++++++++++++++++++++++++++++ src/nvram.h | 46 +++++++++++++++++ 4 files changed, 199 insertions(+), 2 deletions(-) create mode 100644 src/nvram.c create mode 100644 src/nvram.h diff --git a/Makefile b/Makefile index d3341870..48f0b9ac 100644 --- a/Makefile +++ b/Makefile @@ -46,7 +46,7 @@ SRC32FLAT=$(SRCBOTH) post.c e820map.c malloc.c romfile.c x86.c \ fw/mtrr.c fw/xen.c fw/acpi.c fw/mptable.c fw/pirtable.c \ fw/smbios.c fw/romfile_loader.c fw/dsdt_parser.c hw/virtio-ring.c \ hw/virtio-pci.c hw/virtio-mmio.c hw/virtio-blk.c hw/virtio-scsi.c \ - hw/tpm_drivers.c hw/nvme.c sha256.c sha512.c + hw/tpm_drivers.c hw/nvme.c sha256.c sha512.c nvram.c SRC32SEG=string.c output.c pcibios.c apm.c stacks.c hw/pci.c hw/serialio.c DIRS=src src/hw src/fw vgasrc diff --git a/src/boot.c b/src/boot.c index 5c37dafd..c5e102cf 100644 --- a/src/boot.c +++ b/src/boot.c @@ -21,6 +21,8 @@ #include "string.h" // memset #include "util.h" // irqtimer_calc #include "tcgbios.h" // tpm_* +#include "nvram.h" // get_nvram_bootorder + /**************************************************************** * Helper search functions @@ -250,8 +252,13 @@ loadBootOrder(void) { if (!CONFIG_BOOTORDER) return; + char *f = NULL; + + f = get_nvram_bootorder(); + + if (!f) + f = romfile_loadfile("bootorder", NULL); - char *f = romfile_loadfile("bootorder", NULL); if (!f) return; diff --git a/src/nvram.c b/src/nvram.c new file mode 100644 index 00000000..145a062d --- /dev/null +++ b/src/nvram.c @@ -0,0 +1,144 @@ +// Code to manipulate NVRAM configuration +// +// Copyright (C) 2024-2025 Timothy Kenno Handojo <timkenhan(a)mailbox.org> +// Taken and adapted from coreboot's libpayload +// +// This file may be distributed under the terms of the GNU LGPLv3 license. + +/* NOTE: +To avoid confusion, it is important to keep in mind that in this file, +the term CMOS does NOT refer to the RTC, but instead the NVRAM as a whole. +While this technically includes the RTC part, the main focus wouldn't be it, +and instead be the configurable parts (i.e. BIOS settings). +*/ + +#include "nvram.h" +#include "string.h" // memcmp, strlen +#include "malloc.h" // malloc_low +#include "x86.h" // inb, outb +#include "output.h" // dprintf +#include "util.h" // cb_header, find_cb_table, find_cb_subtable + +#define CB_TAG_CMOS_OPTION_TABLE 0x00c8 +#define CB_TAG_OPTION 0x00c9 +#define CB_TAG_OPTION_CHECKSUM 0x00cc + + +u8 nvram_read(u8 addr){ + u16 rtc_port = addr < 128 ? RTC_PORT_STANDARD : RTC_PORT_EXTENDED; + + outb(addr, rtc_port); + return inb(rtc_port + 1); +} + +void nvram_write(u8 val, u8 addr) +{ + u16 rtc_port = addr < 128 ? RTC_PORT_STANDARD : RTC_PORT_EXTENDED; + + outb(addr, rtc_port); + outb(val, rtc_port + 1); +} + +struct nvram_accessor { + u8 (*read)(u8 reg); + void (*write)(u8 val, u8 reg); +}; + +struct nvram_accessor *use_nvram = &(struct nvram_accessor) { + nvram_read, + nvram_write +}; + +static struct cb_cmos_entries *lookup_cmos_entry(struct cb_cmos_option_table *option_table, const char *name) +{ + struct cb_cmos_entries *cmos_entry, *next; + int len = name ? strlen(name) : 0; + + /* CMOS entries are located right after the option table */ + cmos_entry = (struct cb_cmos_entries*)((unsigned char *)option_table + option_table->header_length); + while (cmos_entry) { + if (memcmp((const char*)cmos_entry->name, name, len) == 0) + return cmos_entry; + next = (struct cb_cmos_entries*)((unsigned char *)cmos_entry + cmos_entry->size); + cmos_entry = (next->tag == CB_TAG_OPTION) ? next : NULL; + } + + dprintf(1, "ERROR: No such CMOS option (%s)\n", name); + return NULL; +} + +static int get_cmos_value(const struct nvram_accessor *nvram, u32 bitnum, u32 len, void *valptr) +{ + u8 *value = valptr; + int offs = 0; + u32 addr, bit; + u8 reg8; + + /* Convert to byte borders */ + addr=(bitnum / 8); + bit=(bitnum % 8); + + /* Handle single byte or less */ + if(len <= 8) { + reg8 = nvram->read(addr); + reg8 >>= bit; + value[0] = reg8 & ((1 << len) -1); + return 0; + } + + /* When handling more than a byte, copy whole bytes */ + while (len > 0) { + len -= 8; + value[offs++]=nvram->read(addr++); + } + + return 0; +} + +int options_checksum_valid(const struct nvram_accessor *nvram, struct cb_cmos_checksum *option_checksum) +{ + int i; + int checksum_location = option_checksum->location / 8; + u16 checksum = 0, checksum_old; + + for(i = option_checksum->range_start; i <= option_checksum->range_end; i++) { + checksum += nvram->read(i); + } + + checksum_old = ((nvram->read(checksum_location)<<8) | nvram->read(checksum_location+1)); + + return (checksum_old == checksum); +} + +void *get_nvram_bootorder() +{ + const char *name = "bootorder"; + struct cb_header *cbh = find_cb_table(); + + if (!cbh) + return NULL; + struct cb_cmos_option_table *option_table = find_cb_subtable(cbh, CB_TAG_CMOS_OPTION_TABLE); + struct cb_cmos_checksum *option_checksum = find_cb_subtable(cbh, CB_TAG_OPTION_CHECKSUM); + if (option_table == NULL) { + dprintf(1, "Could not find coreboot option table.\n"); + return NULL; + } + + struct cb_cmos_entries *cmos_entry = lookup_cmos_entry(option_table, name); + + if (!cmos_entry) + return NULL; + int cmos_length = cmos_entry->length; + + /* extra byte to ensure 0-terminated strings */ + void *buf = malloc_low(cmos_length+1); + memset(buf, 0, cmos_length+1); + + if(!options_checksum_valid(use_nvram, option_checksum)) { + dprintf(1, "Invalid option checksum.\n"); + return NULL; + } + get_cmos_value(use_nvram, cmos_entry->bit, cmos_entry->length, buf); + + return buf; +} diff --git a/src/nvram.h b/src/nvram.h new file mode 100644 index 00000000..e57b9e1c --- /dev/null +++ b/src/nvram.h @@ -0,0 +1,46 @@ +// Definitions for NVRAM configuration + +/* NOTE: +To avoid confusion, it is important to keep in mind that in this file, +the term CMOS does NOT refer to the RTC, but instead the NVRAM as a whole. +While this technically includes the RTC part, the main focus wouldn't be it, +and instead be the configurable parts (i.e. BIOS settings). +*/ + +#ifndef __NVRAM_H +#define __NVRAM_H + +#include "types.h" // u32, u8 + +#define RTC_PORT_STANDARD 0x70 +#define RTC_PORT_EXTENDED 0x72 + +struct cb_cmos_option_table { + u32 tag; + u32 size; + u32 header_length; +}; + +#define CB_CMOS_MAX_NAME_LENGTH 32 +struct cb_cmos_entries { + u32 tag; + u32 size; + u32 bit; + u32 length; + u32 config; + u32 config_id; + u8 name[CB_CMOS_MAX_NAME_LENGTH]; +}; + +struct cb_cmos_checksum { + u32 tag; + u32 size; + u32 range_start; + u32 range_end; + u32 location; + u32 type; +}; + +void *get_nvram_bootorder(); + +#endif \ No newline at end of file -- 2.39.5

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Re: [PATCH] NVRAM bootorder
by Kevin O'Connor Jan. 22, 2025

Jan. 22, 2025

On Wed, Jan 22, 2025 at 02:46:09PM +0700, Timothy Kenno Handojo wrote: > Revision from a previous patch. Sorry it took so long. > > This change allows seabios to load bootorder not only from CBFS but > also from the NVRAM as well, making use of coreboot's cmos.layout. Thanks. However, I don't think it's a good idea to use the "CMOS" chip (aka nvram, aka rtc) to communicate settings to SeaBIOS. There's already a well defined mechanism to pass settings via the "romfile" system (fw_cfg on qemu, cbfs on coreboot). I think we should continue to use that "romfile" system instead of adding new mechanisms. I'm also leery of using the NVRAM part of the RTC chip in general, as it has been notoriously finicky - batteries often die causing random values to be reported and many legacy applications have undocumented expectations about the layout of the NVRAM. SeaBIOS has historically not used the NVRAM settings in the RTC chip for any purpose when on coreboot (and only using it for the bare minimum when on qemu). Cheers, -Kevin > > Tested on QEMU Q35 > > From 3aee65ff1a9d5926ff18fa0770362e59e8b52257 Mon Sep 17 00:00:00 2001 > From: Timothy Kenno Handojo <timkenhan(a)mailbox.org> > Date: Wed, 22 Jan 2025 14:40:18 +0700 > Subject: [PATCH] boot: Allow setting bootorder from CMOS entry > > The original bootorder from CBFS remains, but takes lower priority. > > Signed-off-by: Timothy Kenno Handojo <timkenhan(a)mailbox.org> > --- > Makefile | 2 +- > src/boot.c | 9 +++- > src/nvram.c | 144 ++++++++++++++++++++++++++++++++++++++++++++++++++++ > src/nvram.h | 46 +++++++++++++++++ > 4 files changed, 199 insertions(+), 2 deletions(-) > create mode 100644 src/nvram.c > create mode 100644 src/nvram.h > > diff --git a/Makefile b/Makefile > index d3341870..48f0b9ac 100644 > --- a/Makefile > +++ b/Makefile > @@ -46,7 +46,7 @@ SRC32FLAT=$(SRCBOTH) post.c e820map.c malloc.c > romfile.c x86.c \ > fw/mtrr.c fw/xen.c fw/acpi.c fw/mptable.c fw/pirtable.c \ > fw/smbios.c fw/romfile_loader.c fw/dsdt_parser.c hw/virtio-ring.c \ > hw/virtio-pci.c hw/virtio-mmio.c hw/virtio-blk.c hw/virtio-scsi.c \ > - hw/tpm_drivers.c hw/nvme.c sha256.c sha512.c > + hw/tpm_drivers.c hw/nvme.c sha256.c sha512.c nvram.c > SRC32SEG=string.c output.c pcibios.c apm.c stacks.c hw/pci.c hw/serialio.c > DIRS=src src/hw src/fw vgasrc > diff --git a/src/boot.c b/src/boot.c > index 5c37dafd..c5e102cf 100644 > --- a/src/boot.c > +++ b/src/boot.c > @@ -21,6 +21,8 @@ > #include "string.h" // memset > #include "util.h" // irqtimer_calc > #include "tcgbios.h" // tpm_* > +#include "nvram.h" // get_nvram_bootorder > + > /**************************************************************** > * Helper search functions > @@ -250,8 +252,13 @@ loadBootOrder(void) > { > if (!CONFIG_BOOTORDER) > return; > + char *f = NULL; > + > + f = get_nvram_bootorder(); > + > + if (!f) > + f = romfile_loadfile("bootorder", NULL); > - char *f = romfile_loadfile("bootorder", NULL); > if (!f) > return; > diff --git a/src/nvram.c b/src/nvram.c > new file mode 100644 > index 00000000..145a062d > --- /dev/null > +++ b/src/nvram.c > @@ -0,0 +1,144 @@ > +// Code to manipulate NVRAM configuration > +// > +// Copyright (C) 2024-2025 Timothy Kenno Handojo <timkenhan(a)mailbox.org> > +// Taken and adapted from coreboot's libpayload > +// > +// This file may be distributed under the terms of the GNU LGPLv3 license. > + > +/* NOTE: > +To avoid confusion, it is important to keep in mind that in this file, > +the term CMOS does NOT refer to the RTC, but instead the NVRAM as a whole. > +While this technically includes the RTC part, the main focus wouldn't be it, > +and instead be the configurable parts (i.e. BIOS settings). > +*/ > + > +#include "nvram.h" > +#include "string.h" // memcmp, strlen > +#include "malloc.h" // malloc_low > +#include "x86.h" // inb, outb > +#include "output.h" // dprintf > +#include "util.h" // cb_header, find_cb_table, find_cb_subtable > + > +#define CB_TAG_CMOS_OPTION_TABLE 0x00c8 > +#define CB_TAG_OPTION 0x00c9 > +#define CB_TAG_OPTION_CHECKSUM 0x00cc > + > + > +u8 nvram_read(u8 addr){ > + u16 rtc_port = addr < 128 ? RTC_PORT_STANDARD : RTC_PORT_EXTENDED; > + > + outb(addr, rtc_port); > + return inb(rtc_port + 1); > +} > + > +void nvram_write(u8 val, u8 addr) > +{ > + u16 rtc_port = addr < 128 ? RTC_PORT_STANDARD : RTC_PORT_EXTENDED; > + > + outb(addr, rtc_port); > + outb(val, rtc_port + 1); > +} > + > +struct nvram_accessor { > + u8 (*read)(u8 reg); > + void (*write)(u8 val, u8 reg); > +}; > + > +struct nvram_accessor *use_nvram = &(struct nvram_accessor) { > + nvram_read, > + nvram_write > +}; > + > +static struct cb_cmos_entries *lookup_cmos_entry(struct > cb_cmos_option_table *option_table, const char *name) > +{ > + struct cb_cmos_entries *cmos_entry, *next; > + int len = name ? strlen(name) : 0; > + > + /* CMOS entries are located right after the option table */ > + cmos_entry = (struct cb_cmos_entries*)((unsigned char *)option_table > + option_table->header_length); > + while (cmos_entry) { > + if (memcmp((const char*)cmos_entry->name, name, len) == 0) > + return cmos_entry; > + next = (struct cb_cmos_entries*)((unsigned char *)cmos_entry + > cmos_entry->size); > + cmos_entry = (next->tag == CB_TAG_OPTION) ? next : NULL; > + } > + > + dprintf(1, "ERROR: No such CMOS option (%s)\n", name); > + return NULL; > +} > + > +static int get_cmos_value(const struct nvram_accessor *nvram, u32 > bitnum, u32 len, void *valptr) > +{ > + u8 *value = valptr; > + int offs = 0; > + u32 addr, bit; > + u8 reg8; > + > + /* Convert to byte borders */ > + addr=(bitnum / 8); > + bit=(bitnum % 8); > + > + /* Handle single byte or less */ > + if(len <= 8) { > + reg8 = nvram->read(addr); > + reg8 >>= bit; > + value[0] = reg8 & ((1 << len) -1); > + return 0; > + } > + > + /* When handling more than a byte, copy whole bytes */ > + while (len > 0) { > + len -= 8; > + value[offs++]=nvram->read(addr++); > + } > + > + return 0; > +} > + > +int options_checksum_valid(const struct nvram_accessor *nvram, struct > cb_cmos_checksum *option_checksum) > +{ > + int i; > + int checksum_location = option_checksum->location / 8; > + u16 checksum = 0, checksum_old; > + > + for(i = option_checksum->range_start; i <= option_checksum->range_end; i++) { > + checksum += nvram->read(i); > + } > + > + checksum_old = ((nvram->read(checksum_location)<<8) | > nvram->read(checksum_location+1)); > + > + return (checksum_old == checksum); > +} > + > +void *get_nvram_bootorder() > +{ > + const char *name = "bootorder"; > + struct cb_header *cbh = find_cb_table(); > + > + if (!cbh) > + return NULL; > + struct cb_cmos_option_table *option_table = find_cb_subtable(cbh, > CB_TAG_CMOS_OPTION_TABLE); > + struct cb_cmos_checksum *option_checksum = find_cb_subtable(cbh, > CB_TAG_OPTION_CHECKSUM); > + if (option_table == NULL) { > + dprintf(1, "Could not find coreboot option table.\n"); > + return NULL; > + } > + > + struct cb_cmos_entries *cmos_entry = lookup_cmos_entry(option_table, name); > + > + if (!cmos_entry) > + return NULL; > + int cmos_length = cmos_entry->length; > + > + /* extra byte to ensure 0-terminated strings */ > + void *buf = malloc_low(cmos_length+1); > + memset(buf, 0, cmos_length+1); > + > + if(!options_checksum_valid(use_nvram, option_checksum)) { > + dprintf(1, "Invalid option checksum.\n"); > + return NULL; > + } > + get_cmos_value(use_nvram, cmos_entry->bit, cmos_entry->length, buf); > + > + return buf; > +} > diff --git a/src/nvram.h b/src/nvram.h > new file mode 100644 > index 00000000..e57b9e1c > --- /dev/null > +++ b/src/nvram.h > @@ -0,0 +1,46 @@ > +// Definitions for NVRAM configuration > + > +/* NOTE: > +To avoid confusion, it is important to keep in mind that in this file, > +the term CMOS does NOT refer to the RTC, but instead the NVRAM as a whole. > +While this technically includes the RTC part, the main focus wouldn't be it, > +and instead be the configurable parts (i.e. BIOS settings). > +*/ > + > +#ifndef __NVRAM_H > +#define __NVRAM_H > + > +#include "types.h" // u32, u8 > + > +#define RTC_PORT_STANDARD 0x70 > +#define RTC_PORT_EXTENDED 0x72 > + > +struct cb_cmos_option_table { > + u32 tag; > + u32 size; > + u32 header_length; > +}; > + > +#define CB_CMOS_MAX_NAME_LENGTH 32 > +struct cb_cmos_entries { > + u32 tag; > + u32 size; > + u32 bit; > + u32 length; > + u32 config; > + u32 config_id; > + u8 name[CB_CMOS_MAX_NAME_LENGTH]; > +}; > + > +struct cb_cmos_checksum { > + u32 tag; > + u32 size; > + u32 range_start; > + u32 range_end; > + u32 location; > + u32 type; > +}; > + > +void *get_nvram_bootorder(); > + > +#endif > \ No newline at end of file > -- > 2.39.5 > _______________________________________________ > SeaBIOS mailing list -- seabios(a)seabios.org > To unsubscribe send an email to seabios-leave(a)seabios.org

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[PATCH] Fix AHCI Disk Detection when using EDK2 CSM
by Christopher Lentocha Jan. 21, 2025

Jan. 21, 2025

For whatever reason, when you compile SeaBIOS in Csm16 mode, and use it under EDK2's OvmfPkg, the ATA_CMD_IDENTIFY_PACKET_DEVICE command doesn't work properly, therefore, SeaBIOS detects the "SATA HARDDISK" as a "SATA CDROM" device, in QEMU. Despite the Tianocore developers seem to have removed support for Csm16 some time ago, if we decide to remove Csm16 mode in SeaBIOS in favor of that, at least we have the last commit of Csm16 working properly and not half-broken. In order to fix this bug, I decided to move the "detected as a disk" function to be a goto, so code isn't sloppy, by being copied and pasted 1:1 (though this can be changed back later if needed), and in the detected as CDROM function, when it fails at its point, assume its a harddisk, make sure it is with the ATA_CMD_IDENTIFY_DEVICE (which works fine in my testing) command, and continue from there. Signed-off-by: Christopher Lentocha <christopherericlentocha(a)gmail.com> --- src/hw/ahci.c | 191 ++++++++++++++++++++++++++------------------------ 1 file changed, 101 insertions(+), 90 deletions(-) diff --git a/src/hw/ahci.c b/src/hw/ahci.c index 4f0f640a..e53c26be 100644 --- a/src/hw/ahci.c +++ b/src/hw/ahci.c @@ -501,89 +501,7 @@ static int ahci_port_setup(struct ahci_port_s *port) port->drive.removable = (buffer[0] & 0x80) ? 1 : 0; if (!port->atapi) { - // found disk (ata) - port->drive.type = DTYPE_AHCI; - port->drive.blksize = DISK_SECTOR_SIZE; - port->drive.pchs.cylinder = buffer[1]; - port->drive.pchs.head = buffer[3]; - port->drive.pchs.sector = buffer[6]; - - u64 sectors; - if (buffer[83] & (1 << 10)) // word 83 - lba48 support - sectors = *(u64*)&buffer[100]; // word 100-103 - else - sectors = *(u32*)&buffer[60]; // word 60 and word 61 - port->drive.sectors = sectors; - u64 adjsize = sectors >> 11; - char adjprefix = 'M'; - if (adjsize >= (1 << 16)) { - adjsize >>= 10; - adjprefix = 'G'; - } - port->desc = znprintf(MAXDESCSIZE - , "AHCI/%d: %s ATA-%d Hard-Disk (%u %ciBytes)" - , port->pnr - , ata_extract_model(model, MAXMODEL, buffer) - , ata_extract_version(buffer) - , (u32)adjsize, adjprefix); - port->prio = bootprio_find_ata_device(ctrl->pci_tmp, pnr, 0); - - s8 multi_dma = -1; - s8 pio_mode = -1; - s8 udma_mode = -1; - // If bit 2 in word 53 is set, udma information is valid in word 88. - if (buffer[53] & 0x04) { - udma_mode = 6; - while ((udma_mode >= 0) && - !((buffer[88] & 0x7f) & ( 1 << udma_mode ))) { - udma_mode--; - } - } - // If bit 1 in word 53 is set, multiword-dma and advanced pio modes - // are available in words 63 and 64. - if (buffer[53] & 0x02) { - pio_mode = 4; - multi_dma = 3; - while ((multi_dma >= 0) && - !((buffer[63] & 0x7) & ( 1 << multi_dma ))) { - multi_dma--; - } - while ((pio_mode >= 3) && - !((buffer[64] & 0x3) & ( 1 << ( pio_mode - 3 ) ))) { - pio_mode--; - } - } - dprintf(2, "AHCI/%d: supported modes: udma %d, multi-dma %d, pio %d\n", - port->pnr, udma_mode, multi_dma, pio_mode); - - sata_prep_simple(&port->cmd->fis, ATA_CMD_SET_FEATURES); - port->cmd->fis.feature = ATA_SET_FEATRUE_TRANSFER_MODE; - // Select used mode. UDMA first, then Multi-DMA followed by - // advanced PIO modes 3 or 4. If non, set default PIO. - if (udma_mode >= 0) { - dprintf(1, "AHCI/%d: Set transfer mode to UDMA-%d\n", - port->pnr, udma_mode); - port->cmd->fis.sector_count = ATA_TRANSFER_MODE_ULTRA_DMA - | udma_mode; - } else if (multi_dma >= 0) { - dprintf(1, "AHCI/%d: Set transfer mode to Multi-DMA-%d\n", - port->pnr, multi_dma); - port->cmd->fis.sector_count = ATA_TRANSFER_MODE_MULTIWORD_DMA - | multi_dma; - } else if (pio_mode >= 3) { - dprintf(1, "AHCI/%d: Set transfer mode to PIO-%d\n", - port->pnr, pio_mode); - port->cmd->fis.sector_count = ATA_TRANSFER_MODE_PIO_FLOW_CTRL - | pio_mode; - } else { - dprintf(1, "AHCI/%d: Set transfer mode to default PIO\n", - port->pnr); - port->cmd->fis.sector_count = ATA_TRANSFER_MODE_DEFAULT_PIO; - } - rc = ahci_command(port, 1, 0, 0, 0); - if (rc < 0) { - dprintf(1, "AHCI/%d: Set transfer mode failed.\n", port->pnr); - } + goto is_ata_disk; } else { // found cdrom (atapi) port->drive.type = DTYPE_AHCI_ATAPI; @@ -592,14 +510,107 @@ static int ahci_port_setup(struct ahci_port_s *port) u8 iscd = ((buffer[0] >> 8) & 0x1f) == 0x05; if (!iscd) { dprintf(1, "AHCI/%d: atapi device isn't a cdrom\n", port->pnr); - return -1; + port->atapi = 0; + sata_prep_simple(&port->cmd->fis, ATA_CMD_IDENTIFY_DEVICE); + rc = ahci_command(port, 0, 0, buffer, sizeof(buffer)); + if (rc < 0) + return -1; + goto is_ata_disk; + } else { + port->desc = znprintf(MAXDESCSIZE + , "DVD/CD [AHCI/%d: %s ATAPI-%d DVD/CD]" + , port->pnr + , ata_extract_model(model, MAXMODEL, buffer) + , ata_extract_version(buffer)); + port->prio = bootprio_find_ata_device(ctrl->pci_tmp, pnr, 0); + boot_lchs_find_ata_device(ctrl->pci_tmp, pnr, 0, &(port->drive.lchs)); } - port->desc = znprintf(MAXDESCSIZE - , "DVD/CD [AHCI/%d: %s ATAPI-%d DVD/CD]" - , port->pnr - , ata_extract_model(model, MAXMODEL, buffer) - , ata_extract_version(buffer)); - port->prio = bootprio_find_ata_device(ctrl->pci_tmp, pnr, 0); + } + return 0; + +is_ata_disk: + // found disk (ata) + port->drive.type = DTYPE_AHCI; + port->drive.blksize = DISK_SECTOR_SIZE; + port->drive.pchs.cylinder = buffer[1]; + port->drive.pchs.head = buffer[3]; + port->drive.pchs.sector = buffer[6]; + + u64 sectors; + if (buffer[83] & (1 << 10)) // word 83 - lba48 support + sectors = *(u64*)&buffer[100]; // word 100-103 + else + sectors = *(u32*)&buffer[60]; // word 60 and word 61 + port->drive.sectors = sectors; + u64 adjsize = sectors >> 11; + char adjprefix = 'M'; + if (adjsize >= (1 << 16)) { + adjsize >>= 10; + adjprefix = 'G'; + } + port->desc = znprintf(MAXDESCSIZE + , "AHCI/%d: %s ATA-%d Hard-Disk (%u %ciBytes)" + , port->pnr + , ata_extract_model(model, MAXMODEL, buffer) + , ata_extract_version(buffer) + , (u32)adjsize, adjprefix); + port->prio = bootprio_find_ata_device(ctrl->pci_tmp, pnr, 0); + + s8 multi_dma = -1; + s8 pio_mode = -1; + s8 udma_mode = -1; + // If bit 2 in word 53 is set, udma information is valid in word 88. + if (buffer[53] & 0x04) { + udma_mode = 6; + while ((udma_mode >= 0) && + !((buffer[88] & 0x7f) & ( 1 << udma_mode ))) { + udma_mode--; + } + } + // If bit 1 in word 53 is set, multiword-dma and advanced pio modes + // are available in words 63 and 64. + if (buffer[53] & 0x02) { + pio_mode = 4; + multi_dma = 3; + while ((multi_dma >= 0) && + !((buffer[63] & 0x7) & ( 1 << multi_dma ))) { + multi_dma--; + } + while ((pio_mode >= 3) && + !((buffer[64] & 0x3) & ( 1 << ( pio_mode - 3 ) ))) { + pio_mode--; + } + } + dprintf(2, "AHCI/%d: supported modes: udma %d, multi-dma %d, pio %d\n", + port->pnr, udma_mode, multi_dma, pio_mode); + + sata_prep_simple(&port->cmd->fis, ATA_CMD_SET_FEATURES); + port->cmd->fis.feature = ATA_SET_FEATRUE_TRANSFER_MODE; + // Select used mode. UDMA first, then Multi-DMA followed by + // advanced PIO modes 3 or 4. If non, set default PIO. + if (udma_mode >= 0) { + dprintf(1, "AHCI/%d: Set transfer mode to UDMA-%d\n", + port->pnr, udma_mode); + port->cmd->fis.sector_count = ATA_TRANSFER_MODE_ULTRA_DMA + | udma_mode; + } else if (multi_dma >= 0) { + dprintf(1, "AHCI/%d: Set transfer mode to Multi-DMA-%d\n", + port->pnr, multi_dma); + port->cmd->fis.sector_count = ATA_TRANSFER_MODE_MULTIWORD_DMA + | multi_dma; + } else if (pio_mode >= 3) { + dprintf(1, "AHCI/%d: Set transfer mode to PIO-%d\n", + port->pnr, pio_mode); + port->cmd->fis.sector_count = ATA_TRANSFER_MODE_PIO_FLOW_CTRL + | pio_mode; + } else { + dprintf(1, "AHCI/%d: Set transfer mode to default PIO\n", + port->pnr); + port->cmd->fis.sector_count = ATA_TRANSFER_MODE_DEFAULT_PIO; + } + rc = ahci_command(port, 1, 0, 0, 0); + if (rc < 0) { + dprintf(1, "AHCI/%d: Set transfer mode failed.\n", port->pnr); } boot_lchs_find_ata_device(ctrl->pci_tmp, pnr, 0, &(port->drive.lchs)); return 0; -- 2.38.1

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[PATCH 0/2] drop acpi support for qemu 1.6 and older.
by Gerd Hoffmann Jan. 16, 2025

Jan. 16, 2025

Gerd Hoffmann (2): drop obsolete acpi table code drop acpi tables and hex includes Makefile | 15 - src/fw/acpi.c | 668 +------------------------------ src/Kconfig | 10 - src/fw/acpi-dsdt-cpu-hotplug.dsl | 78 ---- src/fw/acpi-dsdt-dbug.dsl | 26 -- src/fw/acpi-dsdt-hpet.dsl | 36 -- src/fw/acpi-dsdt-isa.dsl | 102 ----- src/fw/acpi-dsdt-pci-crs.dsl | 90 ----- src/fw/acpi-dsdt.dsl | 342 ---------------- src/fw/acpi-dsdt.hex | 554 ------------------------- src/fw/q35-acpi-dsdt.dsl | 450 --------------------- src/fw/ssdt-misc.dsl | 104 ----- src/fw/ssdt-misc.hex | 88 ---- src/fw/ssdt-pcihp.dsl | 36 -- src/fw/ssdt-pcihp.hex | 38 -- src/fw/ssdt-proc.dsl | 48 --- src/fw/ssdt-proc.hex | 35 -- 17 files changed, 1 insertion(+), 2719 deletions(-) delete mode 100644 src/fw/acpi-dsdt-cpu-hotplug.dsl delete mode 100644 src/fw/acpi-dsdt-dbug.dsl delete mode 100644 src/fw/acpi-dsdt-hpet.dsl delete mode 100644 src/fw/acpi-dsdt-isa.dsl delete mode 100644 src/fw/acpi-dsdt-pci-crs.dsl delete mode 100644 src/fw/acpi-dsdt.dsl delete mode 100644 src/fw/acpi-dsdt.hex delete mode 100644 src/fw/q35-acpi-dsdt.dsl delete mode 100644 src/fw/ssdt-misc.dsl delete mode 100644 src/fw/ssdt-misc.hex delete mode 100644 src/fw/ssdt-pcihp.dsl delete mode 100644 src/fw/ssdt-pcihp.hex delete mode 100644 src/fw/ssdt-proc.dsl delete mode 100644 src/fw/ssdt-proc.hex -- 2.47.0

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[PATCH] Support multiple USB HID keyboards/mice
by Daniel Khodabakhsh Jan. 7, 2025

Jan. 7, 2025

This change allows the use of multiple USB HID keyboards and mice. It's similar to the change by Stef van Os from this thread: https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/O6Y4LU… however this new change uses the linked list approach instead of a fixed array. Tested on QEMU and an Asus KGPE-D16 with 2 keyboards and one mice

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BUG REPORT: PCI-e address window overlaps with AMD_HT_START
by Li, Yunxiang (Teddy) Jan. 2, 2025

Jan. 2, 2025

[Public] Hi all, I've ran into an issue where the 64 bit address window allocated for one of the PCI-e host devices overlaps with a BIOS reserved range of fd00000000-ffffffffff, making that device unusable. 4000000000-7bfffffffff : PCI Bus 0000:00 4000000000-bfffffffff : PCI Bus 0000:0c 4000000000-7fffffffff : 0000:0c:00.0 8000000000-80001fffff : 0000:0c:00.0 c000000000-13fffffffff : PCI Bus 0000:0b c000000000-ffffffffff : 0000:0b:00.0 fd00000000-ffffffffff : Reserved 10000000000-100001fffff : 0000:0b:00.0 8000000000-7ffffffffff : PCI Bus 0000:00 8000000000-ffffffffff : PCI Bus 0000:0c 8000000000-bfffffffff : 0000:0c:00.0 c000000000-c0001fffff : 0000:0c:00.0 fd00000000-ffffffffff : Reserved 10000000000-17fffffffff : PCI Bus 0000:0b 10000000000-13fffffffff : 0000:0b:00.0 14000000000-140001fffff : 0000:0b:00.0 I found that increasing the system ram of the VM to ~256G changes the address window and avoids the issue, and with some digging I think I found the root cause To begin, QEMU set this address range to be reserved here, and this is passed to Seabios via "etc/e820". https://gitlab.com/qemu-project/qemu/-/blob/master/hw/i386/pc.c#L865 Separately QEMU pass to Seabios "etc/reserved-memory-end" here which is derived from machine->device_memory https://gitlab.com/qemu-project/qemu/-/blob/master/hw/i386/pc.c#L1007 In Seabios, "etc/e820" is consumed here, which sets RamSizeOver4G only using the E820_RAM entries, ignoring any E820_RESERVED entries. https://gitlab.com/qemu-project/seabios/-/blob/master/src/fw/paravirt.c#L782 Later "etc/reserved-memory-end" and RamSizeOver4G is used to determine the start of the PCI-e address window. https://gitlab.com/qemu-project/seabios/-/blob/master/src/fw/pciinit.c#L1138 I think either QEMU should set etc/reserved-memory-end to be after both physical memory and the reserved ranges, or Seabios need to check both etc/820 and etc/reserved-memory-end. But I'm not sure which would be the correct move and indeed how to patch them. Regards, Yunxiang Li (Teddy)

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[PATCH] pciinit: use the 32-bit MMIO address space preferred
by Hulang Jan. 2, 2025

Jan. 2, 2025

Currently, pci region on busses[0] may be migrate to 64-bit mmio space. this will cause a mistake to read/write device config space example: A modern virtio device map to 64-bit mmio space will set mode to VP_ACCESS_PCICFG, But the real device cap is VIRTIO_PCI_CAP_COMMON_CFG, we can not access the cap rightly. If this is a virtio blk/scsi device as system disk, VM will not be booted on the device. A simple solution is make device use the 32-bit address space as much as possible. This patch changes the placement of the PCI bars. [1] commit 0e21548b15e2 ("virtio: pci cfg access") Signed-off-by: hulang <hulang13(a)huawei.com> --- src/fw/pciinit.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index b3e359d7..2e9544dc 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -1100,8 +1100,12 @@ static void pci_region_map_entries(struct pci_bus *busses, struct pci_region *r) { struct hlist_node *n; struct pci_region_entry *entry; + u64 r_end = r->base + pci_region_sum(r) + hlist_for_each_entry_safe(entry, n, &r->list, node) { u64 addr = r->base; + if (addr + entry->size >= r_end) + continue; r->base += entry->size; if (entry->bar == -1) // Update bus base address if entry is a bridge region @@ -1114,6 +1118,8 @@ static void pci_region_map_entries(struct pci_bus *busses, struct pci_region *r) static void pci_bios_map_devices(struct pci_bus *busses) { + int bus; + if (pci_bios_init_root_regions_io(busses)) panic("PCI: out of I/O address space\n"); @@ -1122,6 +1128,15 @@ static void pci_bios_map_devices(struct pci_bus *busses) struct pci_region r64_mem, r64_pref; r64_mem.list.first = NULL; r64_pref.list.first = NULL; + + // try map pci region to 32bit + for (bus = 0; bus<=MaxPCIBus; bus++) { + int type; + for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) + pci_region_map_entries(busses, &busses[bus].r[type]); + } + + // map remaining pci region to 64bit pci_region_migrate_64bit_entries(&busses[0].r[PCI_REGION_TYPE_MEM], &r64_mem); pci_region_migrate_64bit_entries(&busses[0].r[PCI_REGION_TYPE_PREFMEM], @@ -1166,7 +1181,6 @@ static void pci_bios_map_devices(struct pci_bus *busses) pcimem64_start = 0; } // Map regions on each device. - int bus; for (bus = 0; bus<=MaxPCIBus; bus++) { int type; for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) -- 2.33.0 Best Regards！胡浪 Hu Lang 华为云计算公司德科软件开发工程师 Espace：h30028282 Mobile：+86 18212092054 E-mail： hulang11(a)huawei.com<mailto:jinmeng11@huawei.com> www.fescoadecco.com<http://www.fescoadecco.com/> 办公地址：杭州市滨江区江淑路华为研究所Z6-4-B06R-087S

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