April 2024 - SeaBIOS - mail.coreboot.org

Regression 32bit Kernel + Virtio-scsi
by Max Tottenham June 13, 2024

June 13, 2024

Hi Folks The commits between be848676..a6ed6b701 appear to break QEMU guests using a 32bit kernel when booting from virtio_scsi devices. I end up seeing the following in dmesg: [ 2.016642] virtio_scsi: probe of virtio0 failed with error -2 Notably - I've tried modifying the amount of RAM the geust boots with, based on the comments in the commit messages, PAE *is* also enabled in the guest kernel (the kernel v6.1.76). qemu-system-x86_64 .... -m 2048M - Guest boots fine qemu-system-x86_64 .... -m 4095M - Guest does not boot. In the latter case I still see the 64 bit address space being used in the BIOS debug log in the latter case: 00.006: === PCI bus & bridge init === 00.006: PCI: pci_bios_init_bus_rec bus = 0x0 00.007: === PCI device probing === 00.007: Found 8 PCI devices (max PCI bus is 00) 00.008: PCIe: using q35 mmconfig at 0xb0000000 00.008: === PCI new allocation pass #1 === 00.008: PCI: check devices 00.009: === PCI new allocation pass #2 === 00.009: PCI: IO: c000 - c11f 00.009: PCI: 32: 00000000c0000000 - 00000000fec00000 00.009: PCI: 64: 0000380000000000 - 0000380040000000 00.009: PCI: map device bdf=00:02.0 bar 4, addr 380000000000, size 00004000 [prefmem] 00.010: PCI: map device bdf=00:03.0 bar 4, addr 380000004000, size 00004000 [prefmem] 00.010: PCI: map device bdf=00:04.0 bar 4, addr 380000008000, size 00004000 [prefmem] 00.010: PCI: map device bdf=00:02.0 bar 0, addr 0000c000, size 00000040 [io] 00.011: PCI: map device bdf=00:03.0 bar 0, addr 0000c040, size 00000040 [io] 00.011: PCI: map device bdf=00:04.0 bar 0, addr 0000c080, size 00000040 [io] 00.011: PCI: map device bdf=00:1f.3 bar 4, addr 0000c0c0, size 00000040 [io] 00.011: PCI: map device bdf=00:1f.2 bar 4, addr 0000c100, size 00000020 [io] 00.012: PCI: map device bdf=00:04.0 bar 6, addr feb80000, size 00040000 [mem] 00.012: PCI: map device bdf=00:01.0 bar 6, addr febc0000, size 00010000 [mem] 00.012: PCI: map device bdf=00:01.0 bar 2, addr febd0000, size 00001000 [mem] 00.012: PCI: map device bdf=00:02.0 bar 1, addr febd1000, size 00001000 [mem] 00.013: PCI: map device bdf=00:03.0 bar 1, addr febd2000, size 00001000 [mem] 00.013: PCI: map device bdf=00:04.0 bar 1, addr febd3000, size 00001000 [mem] 00.013: PCI: map device bdf=00:1f.2 bar 5, addr febd4000, size 00001000 [mem] 00.013: PCI: map device bdf=00:01.0 bar 0, addr fd000000, size 01000000 [prefmem] 00.014: PCI: init bdf=00:00.0 id=8086:29c0 00.014: PCI: init bdf=00:01.0 id=1234:1111 00.014: PCI: init bdf=00:02.0 id=1af4:1004 00.015: PCI: init bdf=00:03.0 id=1af4:1004 00.016: PCI: init bdf=00:04.0 id=1af4:1000 I'm happy to help test/provide more logs if they are useful. -- Max Tottenham | Senior Software Engineer /(* Akamai Technologies

3 7

[RESEND PATCH] fw/pciinit: don't misalign large BARs
by Daniil Tatianin April 15, 2024

April 15, 2024

Previously we would unconditionally lower the alignment for large BARs in case their alignment was greater than "pci_mem64_top >> 11", this would make it impossible to use these devices by the kernel: [ 13.821108] pci 0000:9c:00.0: can't claim BAR 1 [mem 0x66000000000-0x67fffffffff 64bit pref]: no compatible bridge window [ 13.823492] pci 0000:9d:00.0: can't claim BAR 1 [mem 0x64000000000-0x65fffffffff 64bit pref]: no compatible bridge window [ 13.824218] pci 0000:9e:00.0: can't claim BAR 1 [mem 0x62000000000-0x63fffffffff 64bit pref]: no compatible bridge window [ 13.828322] pci 0000:8a:00.0: can't claim BAR 1 [mem 0x6e000000000-0x6ffffffffff 64bit pref]: no compatible bridge window [ 13.830691] pci 0000:8b:00.0: can't claim BAR 1 [mem 0x6c000000000-0x6dfffffffff 64bit pref]: no compatible bridge window [ 13.832218] pci 0000:8c:00.0: can't claim BAR 1 [mem 0x6a000000000-0x6bfffffffff 64bit pref]: no compatible bridge window Fix it by only overwriting the alignment in case it's actually greater than the desired by the BAR window. Fixes: 96a8d130a8c ("be less conservative with the 64bit pci io window") Signed-off-by: Daniil Tatianin <d-tatianin(a)yandex-team.ru> Reviewed-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/fw/pciinit.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index 6b13cd5b..bb44dc29 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -970,9 +970,11 @@ static int pci_bios_check_devices(struct pci_bus *busses) int resource_optional = 0; if (hotplug_support == HOTPLUG_PCIE) resource_optional = pcie_cap && (type == PCI_REGION_TYPE_IO); + + u64 top_align = pci_mem64_top >> 11; if (hotplug_support && pci_pad_mem64 && is64 - && (type == PCI_REGION_TYPE_PREFMEM)) - align = pci_mem64_top >> 11; + && (type == PCI_REGION_TYPE_PREFMEM) && (top_align > align)) + align = top_align; if (align > sum && hotplug_support && !resource_optional) sum = align; /* reserve min size for hot-plug */ if (size > sum) { -- 2.34.1

3 3

[PATCH] stdvgaio: Only read/write one color palette entry at a time
by Kevin O'Connor April 15, 2024

April 15, 2024

Introduce stdvga_dac_read_many() and stdvga_dac_write_many() for writing multiple dac palette entries. Convert the stdvga_dac_read() and stdvga_dac_write() low-level IO access functions in stdvgaio.c to access just one color palette entry. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> -- There should not be any functional change resulting from this patch. However, during mode switches (and a few other rare calls) there will likely be a few more outb() calls due to additional writes to the dac index register. In theory this could adversely impact performance, but in practice I think it is unlikely it will be noticeable. The original code was also not optimized (it already makes a large number of redundant writes to the dac index register), and performance sensitve code already avoids using the vgabios. --- src/std/vbe.h | 7 +++++++ vgasrc/stdvga.c | 50 +++++++++++++++++++++++++++++++++++++------- vgasrc/stdvga.h | 26 +++++++++++++++++++++++ vgasrc/stdvgaio.c | 37 ++++++++++++-------------------- vgasrc/stdvgamodes.c | 8 +++---- vgasrc/vbe.c | 16 +++++--------- vgasrc/vgabios.c | 22 +++++++++---------- vgasrc/vgautil.h | 23 -------------------- 8 files changed, 109 insertions(+), 80 deletions(-) diff --git a/src/std/vbe.h b/src/std/vbe.h index fe96f5e..fddaa4f 100644 --- a/src/std/vbe.h +++ b/src/std/vbe.h @@ -88,6 +88,13 @@ struct vbe_crtc_info { u8 reserved[40]; } PACKED; +struct vbe_palette_entry { + u8 blue; + u8 green; + u8 red; + u8 align; +} PACKED; + /* VBE Return Status Info */ /* AL */ #define VBE_RETURN_STATUS_SUPPORTED 0x4F diff --git a/vgasrc/stdvga.c b/vgasrc/stdvga.c index afe26db..aeab9d4 100644 --- a/vgasrc/stdvga.c +++ b/vgasrc/stdvga.c @@ -9,6 +9,7 @@ #include "farptr.h" // SET_FARVAR #include "stdvga.h" // stdvga_setup #include "string.h" // memset_far +#include "std/vbe.h" // vbe_palette_entry #include "vgabios.h" // struct vgamode_s #include "vgautil.h" // stdvga_attr_write #include "x86.h" // outb @@ -128,6 +129,41 @@ stdvga_get_palette_page(u8 *pal_pagesize, u8 *pal_page) * DAC control ****************************************************************/ +// Store dac colors into memory in 3-byte rgb format +void +stdvga_dac_read_many(u16 seg, u8 *data_far, u8 start, int count) +{ + while (count) { + struct vbe_palette_entry rgb = stdvga_dac_read(start); + SET_FARVAR(seg, *data_far, rgb.red); + data_far++; + SET_FARVAR(seg, *data_far, rgb.green); + data_far++; + SET_FARVAR(seg, *data_far, rgb.blue); + data_far++; + start++; + count--; + } +} + +// Load dac colors from memory in 3-byte rgb format +void +stdvga_dac_write_many(u16 seg, u8 *data_far, u8 start, int count) +{ + while (count) { + u8 r = GET_FARVAR(seg, *data_far); + data_far++; + u8 g = GET_FARVAR(seg, *data_far); + data_far++; + u8 b = GET_FARVAR(seg, *data_far); + data_far++; + struct vbe_palette_entry rgb = { .red=r, .green=g, .blue=b }; + stdvga_dac_write(start, rgb); + start++; + count--; + } +} + // Convert all loaded colors to shades of gray void stdvga_perform_gray_scale_summing(u16 start, u16 count) @@ -135,16 +171,16 @@ stdvga_perform_gray_scale_summing(u16 start, u16 count) stdvga_attrindex_write(0x00); int i; for (i = start; i < start+count; i++) { - u8 rgb[3]; - stdvga_dac_read(GET_SEG(SS), rgb, i, 1); + struct vbe_palette_entry rgb = stdvga_dac_read(i); // intensity = ( 0.3 * Red ) + ( 0.59 * Green ) + ( 0.11 * Blue ) - u16 intensity = ((77 * rgb[0] + 151 * rgb[1] + 28 * rgb[2]) + 0x80) >> 8; + u16 intensity = ((77 * rgb.red + 151 * rgb.green + + 28 * rgb.blue) + 0x80) >> 8; if (intensity > 0x3f) intensity = 0x3f; - rgb[0] = rgb[1] = rgb[2] = intensity; + rgb.red = rgb.green = rgb.blue = intensity; - stdvga_dac_write(GET_SEG(SS), rgb, i, 1); + stdvga_dac_write(i, rgb); } stdvga_attrindex_write(0x20); } @@ -474,7 +510,7 @@ stdvga_save_dac_state(u16 seg, struct saveDACcolors *info) SET_FARVAR(seg, info->rwmode, inb(VGAREG_DAC_STATE)); SET_FARVAR(seg, info->peladdr, inb(VGAREG_DAC_WRITE_ADDRESS)); SET_FARVAR(seg, info->pelmask, stdvga_pelmask_read()); - stdvga_dac_read(seg, info->dac, 0, 256); + stdvga_dac_read_many(seg, info->dac, 0, 256); SET_FARVAR(seg, info->color_select, 0); } @@ -482,7 +518,7 @@ static void stdvga_restore_dac_state(u16 seg, struct saveDACcolors *info) { stdvga_pelmask_write(GET_FARVAR(seg, info->pelmask)); - stdvga_dac_write(seg, info->dac, 0, 256); + stdvga_dac_write_many(seg, info->dac, 0, 256); outb(GET_FARVAR(seg, info->peladdr), VGAREG_DAC_WRITE_ADDRESS); } diff --git a/vgasrc/stdvga.h b/vgasrc/stdvga.h index ce5a80a..55ad76e 100644 --- a/vgasrc/stdvga.h +++ b/vgasrc/stdvga.h @@ -2,6 +2,7 @@ #define __STDVGA_H #include "types.h" // u8 +#include "std/vbe.h" // struct vbe_palette_entry // VGA registers #define VGAREG_ACTL_ADDRESS 0x3c0 @@ -55,6 +56,8 @@ void stdvga_set_palette_blinking(u8 enable_blink); void stdvga_set_palette_pagesize(u8 pal_pagesize); void stdvga_set_palette_page(u8 pal_page); void stdvga_get_palette_page(u8 *pal_pagesize, u8 *pal_page); +void stdvga_dac_read_many(u16 seg, u8 *data_far, u8 start, int count); +void stdvga_dac_write_many(u16 seg, u8 *data_far, u8 start, int count); void stdvga_perform_gray_scale_summing(u16 start, u16 count); void stdvga_planar4_plane(int plane); void stdvga_set_font_location(u8 spec); @@ -81,4 +84,27 @@ int stdvga_save_restore(int cmd, u16 seg, void *data); void stdvga_enable_video_addressing(u8 disable); int stdvga_setup(void); +// stdvgaio.c +u8 stdvga_pelmask_read(void); +void stdvga_pelmask_write(u8 val); +u8 stdvga_misc_read(void); +void stdvga_misc_write(u8 value); +void stdvga_misc_mask(u8 off, u8 on); +u8 stdvga_sequ_read(u8 index); +void stdvga_sequ_write(u8 index, u8 value); +void stdvga_sequ_mask(u8 index, u8 off, u8 on); +u8 stdvga_grdc_read(u8 index); +void stdvga_grdc_write(u8 index, u8 value); +void stdvga_grdc_mask(u8 index, u8 off, u8 on); +u8 stdvga_crtc_read(u16 crtc_addr, u8 index); +void stdvga_crtc_write(u16 crtc_addr, u8 index, u8 value); +void stdvga_crtc_mask(u16 crtc_addr, u8 index, u8 off, u8 on); +u8 stdvga_attr_read(u8 index); +void stdvga_attr_write(u8 index, u8 value); +void stdvga_attr_mask(u8 index, u8 off, u8 on); +u8 stdvga_attrindex_read(void); +void stdvga_attrindex_write(u8 value); +struct vbe_palette_entry stdvga_dac_read(u8 color); +void stdvga_dac_write(u8 color, struct vbe_palette_entry rgb); + #endif // stdvga.h diff --git a/vgasrc/stdvgaio.c b/vgasrc/stdvgaio.c index 77fcecd..0fbff1a 100644 --- a/vgasrc/stdvgaio.c +++ b/vgasrc/stdvgaio.c @@ -155,32 +155,21 @@ stdvga_attrindex_write(u8 value) } -void -stdvga_dac_read(u16 seg, u8 *data_far, u8 start, int count) +struct vbe_palette_entry +stdvga_dac_read(u8 color) { - outb(start, VGAREG_DAC_READ_ADDRESS); - while (count) { - SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA)); - data_far++; - SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA)); - data_far++; - SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA)); - data_far++; - count--; - } + outb(color, VGAREG_DAC_READ_ADDRESS); + u8 r = inb(VGAREG_DAC_DATA); + u8 g = inb(VGAREG_DAC_DATA); + u8 b = inb(VGAREG_DAC_DATA); + return (struct vbe_palette_entry){ .red=r, .green=g, .blue=b }; } void -stdvga_dac_write(u16 seg, u8 *data_far, u8 start, int count) -{ - outb(start, VGAREG_DAC_WRITE_ADDRESS); - while (count) { - outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA); - data_far++; - outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA); - data_far++; - outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA); - data_far++; - count--; - } +stdvga_dac_write(u8 color, struct vbe_palette_entry rgb) +{ + outb(color, VGAREG_DAC_WRITE_ADDRESS); + outb(rgb.red, VGAREG_DAC_DATA); + outb(rgb.green, VGAREG_DAC_DATA); + outb(rgb.blue, VGAREG_DAC_DATA); } diff --git a/vgasrc/stdvgamodes.c b/vgasrc/stdvgamodes.c index c1d9722..b1d0ef6 100644 --- a/vgasrc/stdvgamodes.c +++ b/vgasrc/stdvgamodes.c @@ -471,11 +471,11 @@ stdvga_set_mode(struct vgamode_s *vmode_g, int flags) u16 palsize = GET_GLOBAL(stdmode_g->dacsize) / 3; // Always 256*3 values - stdvga_dac_write(get_global_seg(), palette_g, 0, palsize); + stdvga_dac_write_many(get_global_seg(), palette_g, 0, palsize); int i; for (i = palsize; i < 0x0100; i++) { - static u8 rgb[3] VAR16; - stdvga_dac_write(get_global_seg(), rgb, i, 1); + struct vbe_palette_entry rgb = { }; + stdvga_dac_write(i, rgb); } if (flags & MF_GRAYSUM) @@ -535,5 +535,5 @@ stdvga_set_mode(struct vgamode_s *vmode_g, int flags) void stdvga_set_packed_palette(void) { - stdvga_dac_write(get_global_seg(), pal_vga, 0, sizeof(pal_vga) / 3); + stdvga_dac_write_many(get_global_seg(), pal_vga, 0, sizeof(pal_vga) / 3); } diff --git a/vgasrc/vbe.c b/vgasrc/vbe.c index d2aaace..2ae0a98 100644 --- a/vgasrc/vbe.c +++ b/vgasrc/vbe.c @@ -403,26 +403,20 @@ vbe_104f09(struct bregs *regs) if (start + count > max_colors) goto fail; u16 seg = regs->es; - u8 *data_far = (void*)(regs->di+0); - u8 rgb[3]; + struct vbe_palette_entry *data_far = (void*)(regs->di+0); int i; switch (regs->bl) { case 0x80: case 0x00: for (i = 0; i < count; i++) { - rgb[0] = GET_FARVAR(seg, data_far[i*4 + 2]); - rgb[1] = GET_FARVAR(seg, data_far[i*4 + 1]); - rgb[2] = GET_FARVAR(seg, data_far[i*4 + 0]); - stdvga_dac_write(GET_SEG(SS), rgb, start + i, 1); + struct vbe_palette_entry rgb = GET_FARVAR(seg, data_far[i]); + stdvga_dac_write(start + i, rgb); } break; case 0x01: for (i = 0; i < count; i++) { - stdvga_dac_read(GET_SEG(SS), rgb, start + i, 1); - SET_FARVAR(seg, data_far[i*4 + 0], rgb[2]); - SET_FARVAR(seg, data_far[i*4 + 1], rgb[1]); - SET_FARVAR(seg, data_far[i*4 + 2], rgb[0]); - SET_FARVAR(seg, data_far[i*4 + 3], 0); + struct vbe_palette_entry rgb = stdvga_dac_read(start + i); + SET_FARVAR(seg, data_far[i], rgb); } break; default: diff --git a/vgasrc/vgabios.c b/vgasrc/vgabios.c index 3659f01..44fb26c 100644 --- a/vgasrc/vgabios.c +++ b/vgasrc/vgabios.c @@ -567,17 +567,18 @@ handle_101009(struct bregs *regs) stdvga_get_all_palette_reg(regs->es, (u8*)(regs->dx + 0)); } -static void noinline +static void handle_101010(struct bregs *regs) { - u8 rgb[3] = {regs->dh, regs->ch, regs->cl}; - stdvga_dac_write(GET_SEG(SS), rgb, regs->bx, 1); + struct vbe_palette_entry rgb = { + .red=regs->dh, .green=regs->ch, .blue=regs->cl }; + stdvga_dac_write(regs->bx, rgb); } static void handle_101012(struct bregs *regs) { - stdvga_dac_write(regs->es, (u8*)(regs->dx + 0), regs->bx, regs->cx); + stdvga_dac_write_many(regs->es, (u8*)(regs->dx + 0), regs->bx, regs->cx); } static void @@ -589,20 +590,19 @@ handle_101013(struct bregs *regs) stdvga_set_palette_page(regs->bh); } -static void noinline +static void handle_101015(struct bregs *regs) { - u8 rgb[3]; - stdvga_dac_read(GET_SEG(SS), rgb, regs->bx, 1); - regs->dh = rgb[0]; - regs->ch = rgb[1]; - regs->cl = rgb[2]; + struct vbe_palette_entry rgb = stdvga_dac_read(regs->bx); + regs->dh = rgb.red; + regs->ch = rgb.green; + regs->cl = rgb.blue; } static void handle_101017(struct bregs *regs) { - stdvga_dac_read(regs->es, (u8*)(regs->dx + 0), regs->bx, regs->cx); + stdvga_dac_read_many(regs->es, (u8*)(regs->dx + 0), regs->bx, regs->cx); } static void diff --git a/vgasrc/vgautil.h b/vgasrc/vgautil.h index ce307c9..ea1ac77 100644 --- a/vgasrc/vgautil.h +++ b/vgasrc/vgautil.h @@ -48,29 +48,6 @@ void ati_list_modes(u16 seg, u16 *dest, u16 *last); int ati_set_mode(struct vgamode_s *vmode_g, int flags); int ati_setup(void); -// stdvgaio.c -u8 stdvga_pelmask_read(void); -void stdvga_pelmask_write(u8 val); -u8 stdvga_misc_read(void); -void stdvga_misc_write(u8 value); -void stdvga_misc_mask(u8 off, u8 on); -u8 stdvga_sequ_read(u8 index); -void stdvga_sequ_write(u8 index, u8 value); -void stdvga_sequ_mask(u8 index, u8 off, u8 on); -u8 stdvga_grdc_read(u8 index); -void stdvga_grdc_write(u8 index, u8 value); -void stdvga_grdc_mask(u8 index, u8 off, u8 on); -u8 stdvga_crtc_read(u16 crtc_addr, u8 index); -void stdvga_crtc_write(u16 crtc_addr, u8 index, u8 value); -void stdvga_crtc_mask(u16 crtc_addr, u8 index, u8 off, u8 on); -u8 stdvga_attr_read(u8 index); -void stdvga_attr_write(u8 index, u8 value); -void stdvga_attr_mask(u8 index, u8 off, u8 on); -u8 stdvga_attrindex_read(void); -void stdvga_attrindex_write(u8 value); -void stdvga_dac_read(u16 seg, u8 *data_far, u8 start, int count); -void stdvga_dac_write(u16 seg, u8 *data_far, u8 start, int count); - // stdvgamodes.c struct vgamode_s *stdvga_find_mode(int mode); void stdvga_list_modes(u16 seg, u16 *dest, u16 *last); -- 2.44.0

2 2

[PATCH v4] Add basic MXM 3.0 interrupt support
by Riku Viitanen April 14, 2024

April 14, 2024

VGAROMs on MXM graphics cards need certain int15h functions present to function properly. On HP EliteBook 8560w with coreboot and Quadro 2000M, this warning is displayed for 30 seconds, making every boot extremely slow: ERROR: Valid MXM Structure not found POST halted for 30 seconds, P-state limited to P10... This patch implements the minimum functionality to get rid of it: the functions 0 and 1, version 3.0 of the specification [1]. Older version 2.1 is not implemented. Functions are enabled only if romfile "mxm-30-sis" exists. These functions are specific to the MXM revision, but not the board or GPU. Some boards might require more of the optional functions to be implemented, however. - Function 0 returns information about supported functions and revision. - Function 1 returns a pointer to a MXM configuration structure in low memory. This is copied from romfile "mxm-30-sis". It can be extracted from vendor BIOS, by using this same interrupt. I wrote a tool [2] to do that from Linux. TEST: HP EliteBook 8560w boots without error and delay, graphics work. [1]: MXM Graphics Module Software Specification Version 3.0, Revision 1.1 [2]: https://codeberg.org/Riku_V/mxmdump/ Signed-off-by: Riku Viitanen riku.viitanen(a)protonmail.com --- src/vgahooks.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/src/vgahooks.c b/src/vgahooks.c index 1f149532..6adf5b9b 100644 --- a/src/vgahooks.c +++ b/src/vgahooks.c @@ -11,13 +11,16 @@ #include "hw/pcidevice.h" // pci_find_device #include "hw/pci_ids.h" // PCI_VENDOR_ID_VIA #include "hw/pci_regs.h" // PCI_VENDOR_ID +#include "malloc.h" // malloc_low #include "output.h" // dprintf +#include "romfile.h" // struct romfile_s, romfile_find #include "string.h" // strcmp #include "util.h" // handle_155f, handle_157f #define VH_VIA 1 #define VH_INTEL 2 #define VH_SMI 3 +#define VH_MXM30 4 int VGAHookHandlerType VARFSEG; @@ -296,6 +299,77 @@ winent_mb6047_setup(struct pci_device *pci) SmiBootDisplay = 0x02; } +/**************************************************************** + * MXM 3.0 hooks + ****************************************************************/ + +void *MXM30SIS VARFSEG; + +/* Function 0: Return Specification Support Level */ +static void +mxm30_F00(struct bregs *regs) +{ + regs->ax = 0x005f; /* Success */ + regs->bl = 0x30; /* MXM version 3.0 */ + regs->cx = (1<<0) | (1<<1); /* Supported functions */ + set_success(regs); +} + +/* Function 1: Return Pointer to MXM System Information Structure */ +static void +mxm30_F01(struct bregs *regs) +{ + switch (regs->cx) { + case 0x0030: + regs->ax = 0x005f; /* Success */ + regs->es = (u32)GET_GLOBAL(MXM30SIS)/16; + regs->di = (u32)GET_GLOBAL(MXM30SIS)%16; + set_success(regs); + break; + default: + handle_155fXX(regs); + break; + } +} + +static void +mxm30_155f80(struct bregs *regs) +{ + switch (regs->bx) { + case 0xff00: mxm30_F00(regs); break; + case 0xff01: mxm30_F01(regs); break; + default: handle_155fXX(regs); break; + } +} + +static void +mxm30_155f(struct bregs *regs) +{ + switch (regs->al) { + case 0x80: mxm30_155f80(regs); break; + default: handle_155fXX(regs); break; + } +} + +static void +mxm30_setup(struct romfile_s *sis_file) +{ + /* Load MXM System Information Structure into low memory */ + MXM30SIS = malloc_low(sis_file->size); + if (!MXM30SIS) { + warn_noalloc(); + return; + } + int ret = sis_file->copy(sis_file, MXM30SIS, sis_file->size); + if (ret < 0) { + free(MXM30SIS); + MXM30SIS = NULL; + return; + } + + VGAHookHandlerType = VH_MXM30; +} + /**************************************************************** * Entry and setup ****************************************************************/ @@ -313,6 +387,7 @@ handle_155f(struct bregs *regs) switch (htype) { case VH_VIA: via_155f(regs); break; case VH_INTEL: intel_155f(regs); break; + case VH_MXM30: mxm30_155f(regs); break; default: handle_155fXX(regs); break; } } @@ -340,6 +415,8 @@ vgahook_setup(struct pci_device *pci) if (!CONFIG_VGAHOOKS) return; + struct romfile_s *mxm30sis = romfile_find("mxm-30-sis"); + if (strcmp(CBvendor, "KONTRON") == 0 && strcmp(CBpart, "986LCD-M") == 0) kontron_setup(pci); else if (strcmp(CBvendor, "GETAC") == 0 && strcmp(CBpart, "P470") == 0) @@ -352,4 +429,6 @@ vgahook_setup(struct pci_device *pci) via_setup(pci); else if (pci->vendor == PCI_VENDOR_ID_INTEL) intel_setup(pci); + else if (mxm30sis != NULL) + mxm30_setup(mxm30sis); } -- 2.44.0

2 6

Floppy drive configuration
by Eduardo Batalha April 11, 2024

April 11, 2024

Hi all, I own an ASUS P5Q and had the same problem that Petr Cvek mentioned in his previous emails. I was configuring the floppy type using the the etc/floppy0 value in cbfs but took me quite a while to figure out that why linux was not showing it. I haven't tested it myself yet, but I think the solution to the floppy configuration issue may be to continue using etc/floppyX and change these lines in floppy.c from } else { u8 type = romfile_loadint("etc/floppy0", 0); if (type) addFloppy(0, type); type = romfile_loadint("etc/floppy1", 0); if (type) addFloppy(1, type); } to } else { u8 type0 = romfile_loadint("etc/floppy0", 0); if (type0) addFloppy(0, type); u8 type1 = romfile_loadint("etc/floppy1", 0); if (type1) addFloppy(1, type1); if (type0 || type 1) rtc_write(CMOS_FLOPPY_DRIVE_TYPE, type0 <<4 | type1); } Quoting from osdev.org : "The first 14 CMOS registers access and control the Real-Time Clock. In fact, the only truly useful registers remaining in CMOS are the Real-Time Clock registers, and register 0x10. All other registers in CMOS are almost entirely obsolete (or are not standardized), and are therefore useless. " So, register 0x10, the floppy drive type, is, conversely, pretty much standardised... Hope this makes sense... Cheers, Ed

4 8

Re: [PATCH] fw/pciinit: don't misalign large BARs
by Gerd Hoffmann April 11, 2024

April 11, 2024

On Wed, Apr 10, 2024 at 11:01:34AM +0300, Daniil Tatianin wrote: > Previously we would unconditionally lower the alignment for large BARs > in case their alignment was greater than "pci_mem64_top >> 11", this > would make it impossible to use these devices by the kernel: > [ 13.821108] pci 0000:9c:00.0: can't claim BAR 1 [mem 0x66000000000-0x67fffffffff 64bit pref]: no compatible bridge window 128G bar. Wow. May I ask what device this is? > + u64 top_align = pci_mem64_top >> 11; > if (hotplug_support && pci_pad_mem64 && is64 > - && (type == PCI_REGION_TYPE_PREFMEM)) > - align = pci_mem64_top >> 11; > + && (type == PCI_REGION_TYPE_PREFMEM) && (top_align > align)) > + align = top_align; Makes sense. Reviewed-by: Gerd Hoffmann <kraxel(a)redhat.com> take care, Gerd

2 1

[PATCH] stdvga: Add stdvga_set_vertical_size() helper function
by Kevin O'Connor April 9, 2024

April 9, 2024

Add helper function and update the bochsvga.c code to use it. This emphasizes the relationship between stdvga_get_vertical_size() and stdvga_set_vertical_size() code. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> -- This patch is on top of the recent "Improve comments in stdvga.c" series. -Kevin --- vgasrc/bochsvga.c | 8 +------- vgasrc/stdvga.c | 11 +++++++++++ vgasrc/stdvga.h | 1 + 3 files changed, 13 insertions(+), 7 deletions(-) diff --git a/vgasrc/bochsvga.c b/vgasrc/bochsvga.c index ab8f25e..3ef0f18 100644 --- a/vgasrc/bochsvga.c +++ b/vgasrc/bochsvga.c @@ -275,13 +275,7 @@ bochsvga_set_mode(struct vgamode_s *vmode_g, int flags) stdvga_crtc_write(crtc_addr, 0x11, 0x00); stdvga_crtc_write(crtc_addr, 0x01, width / 8 - 1); stdvga_set_linelength(vmode_g, width); - stdvga_crtc_write(crtc_addr, 0x12, height - 1); - u8 v = 0; - if ((height - 1) & 0x0100) - v |= 0x02; - if ((height - 1) & 0x0200) - v |= 0x40; - stdvga_crtc_mask(crtc_addr, 0x07, 0x42, v); + stdvga_set_vertical_size(height); stdvga_crtc_write(crtc_addr, 0x09, 0x00); stdvga_crtc_mask(crtc_addr, 0x17, 0x00, 0x03); diff --git a/vgasrc/stdvga.c b/vgasrc/stdvga.c index 4bfa101..afe26db 100644 --- a/vgasrc/stdvga.c +++ b/vgasrc/stdvga.c @@ -286,6 +286,17 @@ stdvga_get_vertical_size(void) return vde + 1; } +// Set vertical screen size (number of horizontal lines in the display) +void +stdvga_set_vertical_size(int lines) +{ + u16 crtc_addr = stdvga_get_crtc(); + u16 vde = lines - 1; + stdvga_crtc_write(crtc_addr, 0x12, vde); + u8 ovl = ((vde >> 7) & 0x02) + ((vde >> 3) & 0x40); + stdvga_crtc_mask(crtc_addr, 0x07, 0x42, ovl); +} + // Get offset into framebuffer accessible from real-mode 64K segment int stdvga_get_window(struct vgamode_s *curmode_g, int window) diff --git a/vgasrc/stdvga.h b/vgasrc/stdvga.h index 1828585..ce5a80a 100644 --- a/vgasrc/stdvga.h +++ b/vgasrc/stdvga.h @@ -67,6 +67,7 @@ void stdvga_set_cursor_shape(u16 cursor_type); void stdvga_set_cursor_pos(int address); void stdvga_set_character_height(u8 lines); u16 stdvga_get_vertical_size(void); +void stdvga_set_vertical_size(int lines); int stdvga_get_window(struct vgamode_s *curmode_g, int window); int stdvga_set_window(struct vgamode_s *curmode_g, int window, int val); int stdvga_minimum_linelength(struct vgamode_s *vmode_g); -- 2.44.0

1 1

[PATCH 0/9] Improve comments in stdvga.c
by Kevin O'Connor April 9, 2024

April 9, 2024

This series adds comments to vgasrc/stdvga.c along with some variable and function renaming. The goal is to make it a little easier to understand this legacy code. There should be no functionality changes with this patch series. -Kevin Kevin O'Connor (9): stdvgamodes: No need to store pelmask in vga_modes[] stdvgamodes: Improve naming of dac palette tables stdvga: Rename CGA palette functions stdvga: Add comments to interface functions in stdvga.c stdvga: Rename stdvga_toggle_intensity() to stdvga_set_palette_blinking() stdvga: Rework stdvga palette index paging interface functions stdvga: Rename stdvga_set_text_block_specifier() to stdvga_set_font_location() stdvga: Rename stdvga_set_scan_lines() to stdvga_set_character_height() stdvga: Rename stdvga_get_vde() to stdvga_get_vertical_size() vgasrc/stdvga.c | 103 ++++++++++++++++++++++++++++--------------- vgasrc/stdvga.h | 17 +++---- vgasrc/stdvgamodes.c | 95 +++++++++++++++++++++------------------ vgasrc/vgabios.c | 31 +++++++------ 4 files changed, 144 insertions(+), 102 deletions(-) -- 2.44.0

2 13

Can I set a password to SeaBIOS?
by seabios.stagegenre＠erine.email April 1, 2024

April 1, 2024

Hello. In typical BIOS, you can set a password to protect your computer at boot-up. Noone can boot up an operating system or even access the boot menu or BIO settings without said password. So I wonder if SeaBIOS has incorporated this feature. Thank you.

1 0