November 2024 - SeaBIOS - mail.coreboot.org

[PATCH v2 0/2] add guest hint for memory layout, take three
by Gerd Hoffmann June 3, 2025

June 3, 2025

Gerd Hoffmann (2): add romfile_loadbool() update pci_pad_mem64 handling src/romfile.h | 1 + src/fw/pciinit.c | 13 ++++++++++--- src/romfile.c | 23 +++++++++++++++++++++++ 3 files changed, 34 insertions(+), 3 deletions(-) -- 2.47.0

3 10

[PATCH 0/2] drop acpi support for qemu 1.6 and older.
by Gerd Hoffmann Jan. 16, 2025

Jan. 16, 2025

Gerd Hoffmann (2): drop obsolete acpi table code drop acpi tables and hex includes Makefile | 15 - src/fw/acpi.c | 668 +------------------------------ src/Kconfig | 10 - src/fw/acpi-dsdt-cpu-hotplug.dsl | 78 ---- src/fw/acpi-dsdt-dbug.dsl | 26 -- src/fw/acpi-dsdt-hpet.dsl | 36 -- src/fw/acpi-dsdt-isa.dsl | 102 ----- src/fw/acpi-dsdt-pci-crs.dsl | 90 ----- src/fw/acpi-dsdt.dsl | 342 ---------------- src/fw/acpi-dsdt.hex | 554 ------------------------- src/fw/q35-acpi-dsdt.dsl | 450 --------------------- src/fw/ssdt-misc.dsl | 104 ----- src/fw/ssdt-misc.hex | 88 ---- src/fw/ssdt-pcihp.dsl | 36 -- src/fw/ssdt-pcihp.hex | 38 -- src/fw/ssdt-proc.dsl | 48 --- src/fw/ssdt-proc.hex | 35 -- 17 files changed, 1 insertion(+), 2719 deletions(-) delete mode 100644 src/fw/acpi-dsdt-cpu-hotplug.dsl delete mode 100644 src/fw/acpi-dsdt-dbug.dsl delete mode 100644 src/fw/acpi-dsdt-hpet.dsl delete mode 100644 src/fw/acpi-dsdt-isa.dsl delete mode 100644 src/fw/acpi-dsdt-pci-crs.dsl delete mode 100644 src/fw/acpi-dsdt.dsl delete mode 100644 src/fw/acpi-dsdt.hex delete mode 100644 src/fw/q35-acpi-dsdt.dsl delete mode 100644 src/fw/ssdt-misc.dsl delete mode 100644 src/fw/ssdt-misc.hex delete mode 100644 src/fw/ssdt-pcihp.dsl delete mode 100644 src/fw/ssdt-pcihp.hex delete mode 100644 src/fw/ssdt-proc.dsl delete mode 100644 src/fw/ssdt-proc.hex -- 2.47.0

3 7

[PATCH] Support multiple USB HID keyboards/mice
by Daniel Khodabakhsh Jan. 7, 2025

Jan. 7, 2025

This change allows the use of multiple USB HID keyboards and mice. It's similar to the change by Stef van Os from this thread: https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/O6Y4LU… however this new change uses the linked list approach instead of a fixed array. Tested on QEMU and an Asus KGPE-D16 with 2 keyboards and one mice

3 13

[PATCH] Add force-boot-menu runtime configuration
by Daniel Khodabakhsh Dec. 24, 2024

Dec. 24, 2024

This change adds a 'force-boot-menu' runtime configuration such that if a non-zero value is set and 'show-boot-menu' is also non-zero, SeaBIOS will show the boot menu without a timeout. This is similar to GRUB having a timeout set to '-1' and originally I wanted to implement it that way but the function to retrieve an integer retrieves an unsigned one so I thought this "boolean" configuration is a good way to implement it. Tested on ASUS KGPE-D16. From b1d69c8da90ab9ec25cc3f35ed5ee651e8405ff1 Mon Sep 17 00:00:00 2001 From: Daniel Khodabakhsh <d.khodabakhsh(a)gmail.com> Date: Thu, 7 Nov 2024 18:46:16 -0800 Subject: [PATCH] Add force-boot-menu runtime configuration. --- docs/Runtime_config.md | 1 + src/boot.c | 32 +++++++++++++++++++------------- 2 files changed, 20 insertions(+), 13 deletions(-) diff --git a/docs/Runtime_config.md b/docs/Runtime_config.md index 5795382b..af4da96a 100644 --- a/docs/Runtime_config.md +++ b/docs/Runtime_config.md @@ -177,6 +177,7 @@ There are several additional configuration options available in the | boot-menu-message | Customize the text boot menu message. Normally, when in text mode SeaBIOS will report the string "\\nPress ESC for boot menu.\\n\\n". This field allows the string to be changed. (This is a string field, and is added as a file containing the raw string.) | boot-menu-key | Controls which key activates the boot menu. The value stored is the DOS scan code (eg, 0x86 for F12, 0x01 for Esc). If this field is set, be sure to also customize the **boot-menu-message** field above. | boot-menu-wait | Amount of time (in milliseconds) to wait at the boot menu prompt before selecting the default boot. +| force-boot-menu | Forces the display of the boot menu unless the value is 0. **show-boot-menu** must also be set to 1. The default is 0. | boot-fail-wait | If no boot devices are found SeaBIOS will reboot after 60 seconds. Set this to the amount of time (in milliseconds) to customize the reboot delay or set to -1 to disable rebooting when no boot devices are found | extra-pci-roots | If the target machine has multiple independent root buses set this to a positive value. The SeaBIOS PCI probe will then search for the given number of extra root buses. | ps2-keyboard-spinup | Some laptops that emulate PS2 keyboards don't respond to keyboard commands immediately after powering on. One may specify the amount of time (in milliseconds) here to allow as additional time for the keyboard to become responsive. When this field is set, SeaBIOS will repeatedly attempt to detect the keyboard until the keyboard is found or the specified timeout is reached. diff --git a/src/boot.c b/src/boot.c index 1effd802..9bcb2480 100644 --- a/src/boot.c +++ b/src/boot.c @@ -708,20 +708,26 @@ interactive_bootmenu(void) return; } - while (get_keystroke(0) >= 0) - ; - - char *bootmsg = romfile_loadfile("etc/boot-menu-message", NULL); + // Show boot splash and proceed with booting if force_boot_menu == 0 (default), + // otherwise force display menu + int force_boot_menu = romfile_loadint("etc/force-boot-menu", 0); int menukey = romfile_loadint("etc/boot-menu-key", 1); - printf("%s", bootmsg ?: "\nPress ESC for boot menu.\n\n"); - free(bootmsg); - - u32 menutime = romfile_loadint("etc/boot-menu-wait", DEFAULT_BOOTMENU_WAIT); - enable_bootsplash(); - int scan_code = get_keystroke(menutime); - disable_bootsplash(); - if (scan_code != menukey) - return; + int scan_code; + if (force_boot_menu == 0) { + while (get_keystroke(0) >= 0) + ; + + char *bootmsg = romfile_loadfile("etc/boot-menu-message", NULL); + printf("%s", bootmsg ?: "\nPress ESC for boot menu.\n\n"); + free(bootmsg); + + u32 menutime = romfile_loadint("etc/boot-menu-wait", DEFAULT_BOOTMENU_WAIT); + enable_bootsplash(); + scan_code = get_keystroke(menutime); + disable_bootsplash(); + if (scan_code != menukey) + return; + } while (get_keystroke(0) >= 0) ; -- 2.46.0

3 6

[PATCH 2/2] resume: move mmconfig reset to pci_resume
by Omar Berrow Nov. 29, 2024

Nov. 29, 2024

--- src/fw/pciinit.c | 3 +++ src/resume.c | 9 --------- 2 files changed, 3 insertions(+), 9 deletions(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index b3e359d7..6727546d 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -382,6 +382,9 @@ void pci_resume(void) if (!CONFIG_QEMU) { return; } + make_bios_writable(); + extern volatile u32 mmconfig; + mmconfig = 0; if (PiixPmBDF >= 0) { piix4_pm_config_setup(PiixPmBDF); diff --git a/src/resume.c b/src/resume.c index 10b873c3..fb0b8a89 100644 --- a/src/resume.c +++ b/src/resume.c @@ -96,15 +96,6 @@ s3_resume(void) return; } - make_bios_writable(); - // reset mmconfig to make sure that we don't use PCIe to - // resume PCIe - dprintf(1, "resetting mmconfig\n"); - extern volatile u32 mmconfig; - mmconfig = 0; - dprintf(1, "mmconfig: 0x%x\n", mmconfig); -// make_bios_readonly(); - pic_setup(); smm_setup(); smp_resume(); -- 2.45.2

2 1

[PATCH 1/2] resume: reset mmconfig to zero
by Omar Berrow Nov. 28, 2024

Nov. 28, 2024

On wake it would attempt use the ECAM space to restore access to ECAM, which wouldn't work because ECAM is disabled after reset. Signed-off-by: Omar Berrow <omarkberrow(a)gmail.com> --- src/hw/pci.c | 2 +- src/resume.c | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/hw/pci.c b/src/hw/pci.c index 8eda84b2..dfe4d92a 100644 --- a/src/hw/pci.c +++ b/src/hw/pci.c @@ -14,7 +14,7 @@ #define PORT_PCI_CMD 0x0cf8 #define PORT_PCI_DATA 0x0cfc -static u32 mmconfig; +volatile u32 mmconfig; static void *mmconfig_addr(u16 bdf, u32 addr) { diff --git a/src/resume.c b/src/resume.c index fb0b8a89..10b873c3 100644 --- a/src/resume.c +++ b/src/resume.c @@ -96,6 +96,15 @@ s3_resume(void) return; } + make_bios_writable(); + // reset mmconfig to make sure that we don't use PCIe to + // resume PCIe + dprintf(1, "resetting mmconfig\n"); + extern volatile u32 mmconfig; + mmconfig = 0; + dprintf(1, "mmconfig: 0x%x\n", mmconfig); +// make_bios_readonly(); + pic_setup(); smm_setup(); smp_resume(); -- 2.45.2

1 0

[PATCH] resume: reset mmconfig to zero
by Omar Berrow Nov. 25, 2024

Nov. 25, 2024

I apologize for the previous thing sent on the mailing list. On wake it would attempt to use the ECAM space to restore access to ECAM, which wouldn't work because ECAM is disabled after reset. Signed-off-by: Omar Berrow <omarkberrow(a)gmail.com> --- src/hw/pci.c | 2 +- src/resume.c | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/hw/pci.c b/src/hw/pci.c index 8eda84b2..dfe4d92a 100644 --- a/src/hw/pci.c +++ b/src/hw/pci.c @@ -14,7 +14,7 @@ #define PORT_PCI_CMD 0x0cf8 #define PORT_PCI_DATA 0x0cfc -static u32 mmconfig; +volatile u32 mmconfig; static void *mmconfig_addr(u16 bdf, u32 addr) { diff --git a/src/resume.c b/src/resume.c index fb0b8a89..10b873c3 100644 --- a/src/resume.c +++ b/src/resume.c @@ -96,6 +96,15 @@ s3_resume(void) return; } + make_bios_writable(); + // reset mmconfig to make sure that we don't use PCIe to + // resume PCIe + dprintf(1, "resetting mmconfig\n"); + extern volatile u32 mmconfig; + mmconfig = 0; + dprintf(1, "mmconfig: 0x%x\n", mmconfig); +// make_bios_readonly(); + pic_setup(); smm_setup(); smp_resume(); -- 2.45.2

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[PATCH 0/2] add guest hint for memory layout, take two
by Gerd Hoffmann Nov. 22, 2024

Nov. 22, 2024

Gerd Hoffmann (2): update pci_pad_mem64 handling add fwcfg override for pci_pad_mem64 src/util.h | 1 + src/fw/paravirt.c | 13 +++++++++++++ src/fw/pciinit.c | 11 ++++++++--- 3 files changed, 22 insertions(+), 3 deletions(-) -- 2.47.0

2 4

[PATCH] NVRAM bootorder
by Timothy Kenno Handojo Nov. 22, 2024

Nov. 22, 2024

This change allows seabios to load bootorder not only from CBFS but also from the NVRAM as well, making use of coreboot's cmos.layout. Tested on QEMU Q35 From 055a831ed9872b99bf6d060c70b495e286ded1ba Mon Sep 17 00:00:00 2001 From: Timothy Kenno Handojo <timkenhan(a)mailbox.org> Date: Thu, 31 Oct 2024 08:11:38 +0700 Subject: [PATCH] boot: Allow setting bootorder from CMOS entry The original bootorder from CBFS remains, but takes lower priority. Signed-off-by: Timothy Kenno Handojo <timkenhan(a)mailbox.org> --- Makefile | 2 +- src/boot.c | 9 +++- src/nvram.c | 130 ++++++++++++++++++++++++++++++++++++++++++++++++++++ src/nvram.h | 37 +++++++++++++++ 4 files changed, 176 insertions(+), 2 deletions(-) create mode 100644 src/nvram.c create mode 100644 src/nvram.h diff --git a/Makefile b/Makefile index d3341870..48f0b9ac 100644 --- a/Makefile +++ b/Makefile @@ -46,7 +46,7 @@ SRC32FLAT=$(SRCBOTH) post.c e820map.c malloc.c romfile.c x86.c \ fw/mtrr.c fw/xen.c fw/acpi.c fw/mptable.c fw/pirtable.c \ fw/smbios.c fw/romfile_loader.c fw/dsdt_parser.c hw/virtio-ring.c \ hw/virtio-pci.c hw/virtio-mmio.c hw/virtio-blk.c hw/virtio-scsi.c \ - hw/tpm_drivers.c hw/nvme.c sha256.c sha512.c + hw/tpm_drivers.c hw/nvme.c sha256.c sha512.c nvram.c SRC32SEG=string.c output.c pcibios.c apm.c stacks.c hw/pci.c hw/serialio.c DIRS=src src/hw src/fw vgasrc diff --git a/src/boot.c b/src/boot.c index 1effd802..0689d7de 100644 --- a/src/boot.c +++ b/src/boot.c @@ -21,6 +21,8 @@ #include "string.h" // memset #include "util.h" // irqtimer_calc #include "tcgbios.h" // tpm_* +#include "nvram.h" // get_nvram_bootorder + /**************************************************************** * Helper search functions @@ -250,8 +252,13 @@ loadBootOrder(void) { if (!CONFIG_BOOTORDER) return; + char *f = NULL; + + f = get_nvram_bootorder(); + + if (!f) + f = romfile_loadfile("bootorder", NULL); - char *f = romfile_loadfile("bootorder", NULL); if (!f) return; diff --git a/src/nvram.c b/src/nvram.c new file mode 100644 index 00000000..0634cf9c --- /dev/null +++ b/src/nvram.c @@ -0,0 +1,130 @@ +#include "nvram.h" +#include "string.h" // memcmp, strlen +#include "malloc.h" // malloc_low +#include "x86.h" // inb, outb +#include "output.h" // dprintf +#include "util.h" // cb_header, find_cb_table, find_cb_subtable + +#define CB_TAG_CMOS_OPTION_TABLE 0x00c8 +#define CB_TAG_OPTION 0x00c9 +#define CB_TAG_OPTION_CHECKSUM 0x00cc + + +u8 nvram_read(u8 addr){ + u16 rtc_port = addr < 128 ? RTC_PORT_STANDARD : RTC_PORT_EXTENDED; + + outb(addr, rtc_port); + return inb(rtc_port + 1); +} + +void nvram_write(u8 val, u8 addr) +{ + u16 rtc_port = addr < 128 ? RTC_PORT_STANDARD : RTC_PORT_EXTENDED; + + outb(addr, rtc_port); + outb(val, rtc_port + 1); +} + +struct nvram_accessor { + u8 (*read)(u8 reg); + void (*write)(u8 val, u8 reg); +}; + +struct nvram_accessor *use_nvram = &(struct nvram_accessor) { + nvram_read, + nvram_write +}; + +static struct cb_cmos_entries *lookup_cmos_entry(struct cb_cmos_option_table *option_table, const char *name) +{ + struct cb_cmos_entries *cmos_entry, *next; + int len = name ? strlen(name) : 0; + + /* CMOS entries are located right after the option table */ + cmos_entry = (struct cb_cmos_entries*)((unsigned char *)option_table + option_table->header_length); + while (cmos_entry) { + if (memcmp((const char*)cmos_entry->name, name, len) == 0) + return cmos_entry; + next = (struct cb_cmos_entries*)((unsigned char *)cmos_entry + cmos_entry->size); + cmos_entry = (next->tag == CB_TAG_OPTION) ? next : NULL; + } + + dprintf(1, "ERROR: No such CMOS option (%s)\n", name); + return NULL; +} + +static int get_cmos_value(const struct nvram_accessor *nvram, u32 bitnum, u32 len, void *valptr) +{ + u8 *value = valptr; + int offs = 0; + u32 addr, bit; + u8 reg8; + + /* Convert to byte borders */ + addr=(bitnum / 8); + bit=(bitnum % 8); + + /* Handle single byte or less */ + if(len <= 8) { + reg8 = nvram->read(addr); + reg8 >>= bit; + value[0] = reg8 & ((1 << len) -1); + return 0; + } + + /* When handling more than a byte, copy whole bytes */ + while (len > 0) { + len -= 8; + value[offs++]=nvram->read(addr++); + } + + return 0; +} + +int options_checksum_valid(const struct nvram_accessor *nvram, struct cb_cmos_checksum *option_checksum) +{ + int i; + int checksum_location = option_checksum->location / 8; + u16 checksum = 0, checksum_old; + + for(i = option_checksum->range_start; i <= option_checksum->range_end; i++) { + checksum += nvram->read(i); + } + + checksum_old = ((nvram->read(checksum_location)<<8) | nvram->read(checksum_location+1)); + + return (checksum_old == checksum); +} + +void *get_nvram_bootorder() +{ + const char *name = "bootorder"; + struct cb_header *cbh = find_cb_table(); + + if (!cbh) + return NULL; + struct cb_cmos_option_table *option_table = find_cb_subtable(cbh, CB_TAG_CMOS_OPTION_TABLE); + struct cb_cmos_checksum *option_checksum = find_cb_subtable(cbh, CB_TAG_OPTION_CHECKSUM); + if (option_table == NULL) { + dprintf(1, "Could not find coreboot option table.\n"); + return NULL; + } + + struct cb_cmos_entries *cmos_entry = lookup_cmos_entry(option_table, name); + + if (!cmos_entry) + return NULL; + int cmos_length = cmos_entry->length; + + /* extra byte to ensure 0-terminated strings */ + void *buf = malloc_low(cmos_length+1); + memset(buf, 0, cmos_length+1); + + if(!options_checksum_valid(use_nvram, option_checksum)) { + dprintf(1, "Invalid option checksum.\n"); + return NULL; + } + get_cmos_value(use_nvram, cmos_entry->bit, cmos_entry->length, buf); + + return buf; +} diff --git a/src/nvram.h b/src/nvram.h new file mode 100644 index 00000000..4c9d559e --- /dev/null +++ b/src/nvram.h @@ -0,0 +1,37 @@ +#ifndef __NVRAM_H +#define __NVRAM_H + +#include "types.h" // u32, u8 + +#define RTC_PORT_STANDARD 0x70 +#define RTC_PORT_EXTENDED 0x72 + +struct cb_cmos_option_table { + u32 tag; + u32 size; + u32 header_length; +}; + +#define CB_CMOS_MAX_NAME_LENGTH 32 +struct cb_cmos_entries { + u32 tag; + u32 size; + u32 bit; + u32 length; + u32 config; + u32 config_id; + u8 name[CB_CMOS_MAX_NAME_LENGTH]; +}; + +struct cb_cmos_checksum { + u32 tag; + u32 size; + u32 range_start; + u32 range_end; + u32 location; + u32 type; +}; + +void *get_nvram_bootorder(); + +#endif \ No newline at end of file -- 2.39.5

2 3

[PATCH] Clarify license headers for dsdt and ssdt tables.
by Robert Spier Nov. 18, 2024

Nov. 18, 2024

From 7c84cde99ec50d80f4a1b327fcb80d25f617e636 Mon Sep 17 00:00:00 2001 From: Robert Spier <rspier(a)google.com> Date: Tue, 9 Jul 2024 10:32:56 -0700 Subject: [PATCH] Add LGPLv2 header back to files derived from acpi-dsdt.dsl which came from Bochs/QEMU. The original code was licensed under LGPLv2 *without* an "or later" affordance. --- src/fw/acpi-dsdt-cpu-hotplug.dsl | 19 +++++++++++++++++++ src/fw/acpi-dsdt-dbug.dsl | 19 +++++++++++++++++++ src/fw/acpi-dsdt-hpet.dsl | 19 +++++++++++++++++++ src/fw/acpi-dsdt-isa.dsl | 19 +++++++++++++++++++ src/fw/acpi-dsdt-pci-crs.dsl | 19 +++++++++++++++++++ src/fw/ssdt-misc.dsl | 19 +++++++++++++++++++ src/fw/ssdt-pcihp.dsl | 19 +++++++++++++++++++ src/fw/ssdt-proc.dsl | 19 +++++++++++++++++++ 8 files changed, 152 insertions(+) diff --git a/src/fw/acpi-dsdt-cpu-hotplug.dsl b/src/fw/acpi-dsdt-cpu-hotplug.dsl index 0f3e83b1..cc94c228 100644 --- a/src/fw/acpi-dsdt-cpu-hotplug.dsl +++ b/src/fw/acpi-dsdt-cpu-hotplug.dsl @@ -1,3 +1,22 @@ +/* + * Bochs/QEMU ACPI DSDT ASL definition + * + * Copyright (c) 2006 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License version 2 as published by the Free Software Foundation. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + /**************************************************************** * CPU hotplug ****************************************************************/ diff --git a/src/fw/acpi-dsdt-dbug.dsl b/src/fw/acpi-dsdt-dbug.dsl index 276321f6..2d6d2b82 100644 --- a/src/fw/acpi-dsdt-dbug.dsl +++ b/src/fw/acpi-dsdt-dbug.dsl @@ -1,3 +1,22 @@ +/* + * Bochs/QEMU ACPI DSDT ASL definition + * + * Copyright (c) 2006 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License version 2 as published by the Free Software Foundation. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + /**************************************************************** * Debugging ****************************************************************/ diff --git a/src/fw/acpi-dsdt-hpet.dsl b/src/fw/acpi-dsdt-hpet.dsl index f33e5279..a1edac7e 100644 --- a/src/fw/acpi-dsdt-hpet.dsl +++ b/src/fw/acpi-dsdt-hpet.dsl @@ -1,3 +1,22 @@ +/* + * Bochs/QEMU ACPI DSDT ASL definition + * + * Copyright (c) 2006 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License version 2 as published by the Free Software Foundation. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + /**************************************************************** * HPET ****************************************************************/ diff --git a/src/fw/acpi-dsdt-isa.dsl b/src/fw/acpi-dsdt-isa.dsl index 23761dbb..72e5ac42 100644 --- a/src/fw/acpi-dsdt-isa.dsl +++ b/src/fw/acpi-dsdt-isa.dsl @@ -1,3 +1,22 @@ +/* + * Bochs/QEMU ACPI DSDT ASL definition + * + * Copyright (c) 2006 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License version 2 as published by the Free Software Foundation. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + /* Common legacy ISA style devices. */ Scope(\_SB.PCI0.ISA) { diff --git a/src/fw/acpi-dsdt-pci-crs.dsl b/src/fw/acpi-dsdt-pci-crs.dsl index d4218914..e87c6e19 100644 --- a/src/fw/acpi-dsdt-pci-crs.dsl +++ b/src/fw/acpi-dsdt-pci-crs.dsl @@ -1,3 +1,22 @@ +/* + * Bochs/QEMU ACPI DSDT ASL definition + * + * Copyright (c) 2006 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License version 2 as published by the Free Software Foundation. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + /* PCI CRS (current resources) definition. */ Scope(\_SB.PCI0) { diff --git a/src/fw/ssdt-misc.dsl b/src/fw/ssdt-misc.dsl index d1d2c9e3..1d62e187 100644 --- a/src/fw/ssdt-misc.dsl +++ b/src/fw/ssdt-misc.dsl @@ -1,3 +1,22 @@ +/* + * Bochs/QEMU ACPI DSDT ASL definition + * + * Copyright (c) 2006 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License version 2 as published by the Free Software Foundation. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + ACPI_EXTRACT_ALL_CODE ssdp_misc_aml DefinitionBlock ("ssdt-misc.aml", "SSDT", 0x01, "BXPC", "BXSSDTSU", 0x1) diff --git a/src/fw/ssdt-pcihp.dsl b/src/fw/ssdt-pcihp.dsl index 518a5ebf..11a36966 100644 --- a/src/fw/ssdt-pcihp.dsl +++ b/src/fw/ssdt-pcihp.dsl @@ -1,3 +1,22 @@ +/* + * Bochs/QEMU ACPI DSDT ASL definition + * + * Copyright (c) 2006 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License version 2 as published by the Free Software Foundation. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + ACPI_EXTRACT_ALL_CODE ssdp_pcihp_aml DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPC", 0x1) diff --git a/src/fw/ssdt-proc.dsl b/src/fw/ssdt-proc.dsl index 407d61ea..00690e66 100644 --- a/src/fw/ssdt-proc.dsl +++ b/src/fw/ssdt-proc.dsl @@ -1,3 +1,22 @@ +/* + * Bochs/QEMU ACPI DSDT ASL definition + * + * Copyright (c) 2006 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License version 2 as published by the Free Software Foundation. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + /* This file is the basis for the ssdt table generated in src/acpi.c. * It defines the contents of the per-cpu Processor() object. At * runtime, a dynamically generated SSDT will contain one copy of this -- 2.45.2.803.g4e1b14247a-goog

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[PATCH 0/4] add guest hint for memory layout (pci bar placement)
by Gerd Hoffmann Nov. 15, 2024

Nov. 15, 2024

This series adds an option to set the memory layout preference, both at compile time (via kconfig) and runtime (via fwcfg). Gerd Hoffmann (4): add guest hint variable use guest hint as additional condition add guest hint default kconfig add guest hint fw_cfg override src/fw/paravirt.h | 1 + src/fw/paravirt.c | 9 +++++++++ src/fw/pciinit.c | 2 +- src/Kconfig | 7 +++++++ 4 files changed, 18 insertions(+), 1 deletion(-) -- 2.47.0

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[PATCH v2 1/4] add debug when we set pci_pad_mem64
by John Levon Nov. 14, 2024

Nov. 14, 2024

This is an interesting enough setting to add a dprintf() for. Signed-off-by: John Levon <john.levon(a)nutanix.com> --- src/fw/pciinit.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index bb44dc29..0395fdbf 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -1197,8 +1197,10 @@ pci_setup(void) } } - if (CPUPhysBits >= 36 && CPULongMode && RamSizeOver4G) + if (CPUPhysBits >= 36 && CPULongMode && RamSizeOver4G) { + dprintf(1, "enabling 64-bit pci mmio window\n"); pci_pad_mem64 = 1; + } dprintf(1, "=== PCI bus & bridge init ===\n"); if (pci_probe_host() != 0) { -- 2.34.1

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Fwd: [PATCH] resume: reset mmconfig to zero
by Omar Berrow Nov. 3, 2024

Nov. 3, 2024

---------- Forwarded message --------- From: Omar Berrow <omarkberrow(a)gmail.com> Date: Sun, Nov 3, 2024 at 7:11 AM Subject: Re: [SeaBIOS] [PATCH] resume: reset mmconfig to zero To: Paul Menzel <pmenzel(a)molgen.mpg.de> > Also maybe mention the new log messages. > Should the log level be increased to 3, or is it important to have it in the logs? I must've forgotten to remove the printf while debugging, it's fine to completely remove it. > What’s the downside of not making the BIOS read-only? The BIOS does later write to mmconfig while resuming, it does indeed assume that the bios is writable, which, if I made it read-only again, would make this assumption false. > Nice find. Is there a way to reproduce your issue, for example with QEMU? Indeed: - Put QEMU into the S3 sleeping state. - When you wake the virtual machine, if you were to add logs in pci_config_writel, you would see that it tries to use ECAM space while access to the ECAM is being restored. Side effects: ECAM access was never truly restored in the BIOS on resume, so when the kernel then goes to access the PCIe bus through ECAM, it finds that no changes are going through. If you guys need a kernel that has S3 to verify this, I will link my kernel below https://github.com/OBOS-dev/obos/tree/b26e062af2c53ee6c3364a88784d22225ee27… (for the best performance, use CMAKE_BUILD_TYPE=Release and KVM) It should suspend right after printing: > [ LOG ] oboskrnl: Suspend requested Sincerely, Omar

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[PATCH] resume: reset mmconfig to zero
by Omar Berrow Nov. 2, 2024

Nov. 2, 2024

Signed-off-by: Omar Berrow <omarkberrow(a)gmail.com> --- src/hw/pci.c | 2 +- src/resume.c | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/hw/pci.c b/src/hw/pci.c index 8eda84b2..dfe4d92a 100644 --- a/src/hw/pci.c +++ b/src/hw/pci.c @@ -14,7 +14,7 @@ #define PORT_PCI_CMD 0x0cf8 #define PORT_PCI_DATA 0x0cfc -static u32 mmconfig; +volatile u32 mmconfig; static void *mmconfig_addr(u16 bdf, u32 addr) { diff --git a/src/resume.c b/src/resume.c index fb0b8a89..10b873c3 100644 --- a/src/resume.c +++ b/src/resume.c @@ -96,6 +96,15 @@ s3_resume(void) return; } + make_bios_writable(); + // reset mmconfig to make sure that we don't use PCIe to + // resume PCIe + dprintf(1, "resetting mmconfig\n"); + extern volatile u32 mmconfig; + mmconfig = 0; + dprintf(1, "mmconfig: 0x%x\n", mmconfig); +// make_bios_readonly(); + pic_setup(); smm_setup(); smp_resume(); -- 2.45.2

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feature patch: NVRAM bootorder
by Timothy Kenno Handojo Oct. 31, 2024

Oct. 31, 2024

Dear Maintainers, I hope this message finds you well. Attached is the patch containing some of my changes I'm proposing: 0001-boot-Allow-setting-bootorder-from-CMOS-entry.patch The change allows seabios to load bootorder not only from CBFS but also from the NVRAM as well, making use of coreboot's cmos.layout. To prepare testing environment: - Prepare the coreboot source code with coreboot-qemu-q35-cmos.layout-test.patch. Configure coreboot for QEMU Q35 platform. For the payload, you can select anything (I simply choose SeaBIOS for simplicity), with secondary payloads of coreinfo and nvramcui. I've attached the qemu-q35-defconfig to eliminate possible ambiguity. - Compile a coreboot.rom. - Prepare the SeaBIOS source code with 0001-boot-Allow-setting-bootorder-from-CMOS-entry.patch, and compile it. - On the newly compiled coreboot.rom, use cbfstool (which gets compiled along with the coreboot.rom) to remove fallback/payload, then add the newly compiled bios.bin.elf as the new fallback/payload. - Prepare a Linux bootable. In general, any Linux system would do as long as you can run the required software. I go with Alpine Linux live disk as its ISO image is only 64MB. Any additional files go in a secondary disk, including its overlay system. I simply created a 16MB image using dd command and then formatted it with FAT. - Compile cbmem and nvramtool from coreboot's util directory. For my Alpine Linux setup, I need to make sure to compile with musl instead of glibc (e.g. in an Alpine chroot) - Include cbmem and nvramtool to the Linux bootable. For my Alpine setup, I simply have a secondary disk image (also where I put the overlay). - For convenience, I'd put everything in the same directory. To actually test: - Run QEMU with `qemu-system-x86_64 -enable-kvm -cpu host -M q35 -bios coreboot-qemu.rom -m 1G <disks>` - For the QEMU options, serial output can be used as well, however it tends to break when loading coreinfo & nvramcui. Regardless, it's useful when all I have to do is debug with cbmem output. - On the BIOS screen, press Esc to see the menu. Note the disks should be on top. Boot to the disk. - Once your Linux system boots on QEMU, login to CLI as root, use nvramtool to modify the 'bootorder' entry. I myself ran `nvramtool -w bootorder="/rom@img/coreinfo"` to make it boot coreinfo first thing. - Reboot the QEMU system (do NOT kill the QEMU), press Esc again and see that coreinfo now jumps to the top. You can also not press Esc and see it loads coreinfo. Feel free to replace coreinfo with something else! Some todo - Create a tool to modify bootorder more properly (i.e. loading from file would be nice, for starters) -- in progress - Make bootorder a reserved section on cmos.layout to prevent unintended changes. - Test on a read hardware, I have a Thinkpad X230 eager to try it Do let me know if you have any feedback! Warm regards, Timothy Kenno Handojo

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