November 2024 - SeaBIOS - mail.coreboot.org

regression: cannot boot from nvme anymore, disabling 64bit pci io window helps
by Marek Marczykowski-Górecki July 7, 2026

July 7, 2026

Hi, After an update some time ago, a VM wit 8GB RAM cannot boot from nvme anymore. QEMU cmdline: /usr/bin/qemu-system-x86_64 \ -chardev ringbuf,id=serial0,logfile=serial0,logappend=on \ -serial chardev:serial0 \ -m 8192 \ -enable-kvm \ -vnc :2,share=force-shared \ -blockdev driver=file,node-name=hd0-file,filename=disk.qcow2,cache.no-flush=on,discard=unmap \ -blockdev driver=qcow2,node-name=hd0,file=hd0-file,cache.no-flush=on,discard=unmap \ -device nvme,id=hd0-device,drive=hd0,serial=hd0 \ -chardev stdio,id=seabios -device isa-debugcon,iobase=0x402,chardev=seabios \ -bios /home/user/seabios/out/bios.bin There is nothing fancy on the disk, just standard grub2 setup, but also I believe it doesn't matter, as it doesn't even reach grub. When it fails, the seabios log contains: PCI: 64: 0000038000000000 - 0000038040000000 PCI: map device bdf=00:04.0 bar 0, addr 38000000000, size 00004000 [mem] ... Searching bootorder for: /pci@i0cf8/isa@1/fdc@03f0/floppy@0 ATA controller 1 at 1f0/3f4/0 (irq 14 dev 9) ATA controller 2 at 170/374/0 (irq 15 dev 9) Searching bootorder for: HALT Can not map memory bar over 4Gig ... Boot failed: could not read the boot disk Working version has this instead: PCI: map device bdf=00:04.0 bar 0, addr febf0000, size 00004000 [mem] ... Booting from Hard Disk... Booting from 0000:7c00 00:04.0 is the nvme. I'm attaching full logs for both cases. Bisect shows: 96a8d130a8c2e908e357ce62cd713f2cc0b0a2eb is the first bad commit commit 96a8d130a8c2e908e357ce62cd713f2cc0b0a2eb (HEAD) Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Fri Sep 9 10:17:15 2022 +0200 be less conservative with the 64bit pci io window Current seabios code will only enable and use the 64bit pci io window in case it runs out of space in the 32bit pci mmio window below 4G. This patch will also enable the 64bit pci io window when (a) RAM above 4G is present, and (b) the physical address space size is known, and (c) seabios is running on a 64bit capable processor. This operates with the assumption that guests which are ok with memory above 4G most likely can handle mmio above 4G too. In case the 64bit pci io window is enabled also assign more memory to prefetchable pci bridge windows and the complete 64bit pci io window. The total mmio window size is 1/8 of the physical address space. Minimum bridge windows size is 1/256 of the total mmio window size. Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> I've tried the recent "[PATCH] limit address space used for pci devices, part two" patch from the ML, but it doesn't help. OTOH, the series with "only enable 64bit pci io window when RAM >64G" does help. -- Best Regards, Marek Marczykowski-Górecki Invisible Things Lab

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[PATCH v2 0/2] add guest hint for memory layout, take three
by Gerd Hoffmann June 3, 2025

June 3, 2025

Gerd Hoffmann (2): add romfile_loadbool() update pci_pad_mem64 handling src/romfile.h | 1 + src/fw/pciinit.c | 13 ++++++++++--- src/romfile.c | 23 +++++++++++++++++++++++ 3 files changed, 34 insertions(+), 3 deletions(-) -- 2.47.0

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[PATCH 0/2] drop acpi support for qemu 1.6 and older.
by Gerd Hoffmann Jan. 16, 2025

Jan. 16, 2025

Gerd Hoffmann (2): drop obsolete acpi table code drop acpi tables and hex includes Makefile | 15 - src/fw/acpi.c | 668 +------------------------------ src/Kconfig | 10 - src/fw/acpi-dsdt-cpu-hotplug.dsl | 78 ---- src/fw/acpi-dsdt-dbug.dsl | 26 -- src/fw/acpi-dsdt-hpet.dsl | 36 -- src/fw/acpi-dsdt-isa.dsl | 102 ----- src/fw/acpi-dsdt-pci-crs.dsl | 90 ----- src/fw/acpi-dsdt.dsl | 342 ---------------- src/fw/acpi-dsdt.hex | 554 ------------------------- src/fw/q35-acpi-dsdt.dsl | 450 --------------------- src/fw/ssdt-misc.dsl | 104 ----- src/fw/ssdt-misc.hex | 88 ---- src/fw/ssdt-pcihp.dsl | 36 -- src/fw/ssdt-pcihp.hex | 38 -- src/fw/ssdt-proc.dsl | 48 --- src/fw/ssdt-proc.hex | 35 -- 17 files changed, 1 insertion(+), 2719 deletions(-) delete mode 100644 src/fw/acpi-dsdt-cpu-hotplug.dsl delete mode 100644 src/fw/acpi-dsdt-dbug.dsl delete mode 100644 src/fw/acpi-dsdt-hpet.dsl delete mode 100644 src/fw/acpi-dsdt-isa.dsl delete mode 100644 src/fw/acpi-dsdt-pci-crs.dsl delete mode 100644 src/fw/acpi-dsdt.dsl delete mode 100644 src/fw/acpi-dsdt.hex delete mode 100644 src/fw/q35-acpi-dsdt.dsl delete mode 100644 src/fw/ssdt-misc.dsl delete mode 100644 src/fw/ssdt-misc.hex delete mode 100644 src/fw/ssdt-pcihp.dsl delete mode 100644 src/fw/ssdt-pcihp.hex delete mode 100644 src/fw/ssdt-proc.dsl delete mode 100644 src/fw/ssdt-proc.hex -- 2.47.0

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[PATCH] Support multiple USB HID keyboards/mice
by Daniel Khodabakhsh Jan. 7, 2025

Jan. 7, 2025

This change allows the use of multiple USB HID keyboards and mice. It's similar to the change by Stef van Os from this thread: https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/O6Y4LU… however this new change uses the linked list approach instead of a fixed array. Tested on QEMU and an Asus KGPE-D16 with 2 keyboards and one mice

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[PATCH] Add force-boot-menu runtime configuration
by Daniel Khodabakhsh Dec. 24, 2024

Dec. 24, 2024

This change adds a 'force-boot-menu' runtime configuration such that if a non-zero value is set and 'show-boot-menu' is also non-zero, SeaBIOS will show the boot menu without a timeout. This is similar to GRUB having a timeout set to '-1' and originally I wanted to implement it that way but the function to retrieve an integer retrieves an unsigned one so I thought this "boolean" configuration is a good way to implement it. Tested on ASUS KGPE-D16. From b1d69c8da90ab9ec25cc3f35ed5ee651e8405ff1 Mon Sep 17 00:00:00 2001 From: Daniel Khodabakhsh <d.khodabakhsh(a)gmail.com> Date: Thu, 7 Nov 2024 18:46:16 -0800 Subject: [PATCH] Add force-boot-menu runtime configuration. --- docs/Runtime_config.md | 1 + src/boot.c | 32 +++++++++++++++++++------------- 2 files changed, 20 insertions(+), 13 deletions(-) diff --git a/docs/Runtime_config.md b/docs/Runtime_config.md index 5795382b..af4da96a 100644 --- a/docs/Runtime_config.md +++ b/docs/Runtime_config.md @@ -177,6 +177,7 @@ There are several additional configuration options available in the | boot-menu-message | Customize the text boot menu message. Normally, when in text mode SeaBIOS will report the string "\\nPress ESC for boot menu.\\n\\n". This field allows the string to be changed. (This is a string field, and is added as a file containing the raw string.) | boot-menu-key | Controls which key activates the boot menu. The value stored is the DOS scan code (eg, 0x86 for F12, 0x01 for Esc). If this field is set, be sure to also customize the **boot-menu-message** field above. | boot-menu-wait | Amount of time (in milliseconds) to wait at the boot menu prompt before selecting the default boot. +| force-boot-menu | Forces the display of the boot menu unless the value is 0. **show-boot-menu** must also be set to 1. The default is 0. | boot-fail-wait | If no boot devices are found SeaBIOS will reboot after 60 seconds. Set this to the amount of time (in milliseconds) to customize the reboot delay or set to -1 to disable rebooting when no boot devices are found | extra-pci-roots | If the target machine has multiple independent root buses set this to a positive value. The SeaBIOS PCI probe will then search for the given number of extra root buses. | ps2-keyboard-spinup | Some laptops that emulate PS2 keyboards don't respond to keyboard commands immediately after powering on. One may specify the amount of time (in milliseconds) here to allow as additional time for the keyboard to become responsive. When this field is set, SeaBIOS will repeatedly attempt to detect the keyboard until the keyboard is found or the specified timeout is reached. diff --git a/src/boot.c b/src/boot.c index 1effd802..9bcb2480 100644 --- a/src/boot.c +++ b/src/boot.c @@ -708,20 +708,26 @@ interactive_bootmenu(void) return; } - while (get_keystroke(0) >= 0) - ; - - char *bootmsg = romfile_loadfile("etc/boot-menu-message", NULL); + // Show boot splash and proceed with booting if force_boot_menu == 0 (default), + // otherwise force display menu + int force_boot_menu = romfile_loadint("etc/force-boot-menu", 0); int menukey = romfile_loadint("etc/boot-menu-key", 1); - printf("%s", bootmsg ?: "\nPress ESC for boot menu.\n\n"); - free(bootmsg); - - u32 menutime = romfile_loadint("etc/boot-menu-wait", DEFAULT_BOOTMENU_WAIT); - enable_bootsplash(); - int scan_code = get_keystroke(menutime); - disable_bootsplash(); - if (scan_code != menukey) - return; + int scan_code; + if (force_boot_menu == 0) { + while (get_keystroke(0) >= 0) + ; + + char *bootmsg = romfile_loadfile("etc/boot-menu-message", NULL); + printf("%s", bootmsg ?: "\nPress ESC for boot menu.\n\n"); + free(bootmsg); + + u32 menutime = romfile_loadint("etc/boot-menu-wait", DEFAULT_BOOTMENU_WAIT); + enable_bootsplash(); + scan_code = get_keystroke(menutime); + disable_bootsplash(); + if (scan_code != menukey) + return; + } while (get_keystroke(0) >= 0) ; -- 2.46.0

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[PATCH 2/2] resume: move mmconfig reset to pci_resume
by Omar Berrow Nov. 29, 2024

Nov. 29, 2024

--- src/fw/pciinit.c | 3 +++ src/resume.c | 9 --------- 2 files changed, 3 insertions(+), 9 deletions(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index b3e359d7..6727546d 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -382,6 +382,9 @@ void pci_resume(void) if (!CONFIG_QEMU) { return; } + make_bios_writable(); + extern volatile u32 mmconfig; + mmconfig = 0; if (PiixPmBDF >= 0) { piix4_pm_config_setup(PiixPmBDF); diff --git a/src/resume.c b/src/resume.c index 10b873c3..fb0b8a89 100644 --- a/src/resume.c +++ b/src/resume.c @@ -96,15 +96,6 @@ s3_resume(void) return; } - make_bios_writable(); - // reset mmconfig to make sure that we don't use PCIe to - // resume PCIe - dprintf(1, "resetting mmconfig\n"); - extern volatile u32 mmconfig; - mmconfig = 0; - dprintf(1, "mmconfig: 0x%x\n", mmconfig); -// make_bios_readonly(); - pic_setup(); smm_setup(); smp_resume(); -- 2.45.2

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[PATCH 1/2] resume: reset mmconfig to zero
by Omar Berrow Nov. 28, 2024

Nov. 28, 2024

On wake it would attempt use the ECAM space to restore access to ECAM, which wouldn't work because ECAM is disabled after reset. Signed-off-by: Omar Berrow <omarkberrow(a)gmail.com> --- src/hw/pci.c | 2 +- src/resume.c | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/hw/pci.c b/src/hw/pci.c index 8eda84b2..dfe4d92a 100644 --- a/src/hw/pci.c +++ b/src/hw/pci.c @@ -14,7 +14,7 @@ #define PORT_PCI_CMD 0x0cf8 #define PORT_PCI_DATA 0x0cfc -static u32 mmconfig; +volatile u32 mmconfig; static void *mmconfig_addr(u16 bdf, u32 addr) { diff --git a/src/resume.c b/src/resume.c index fb0b8a89..10b873c3 100644 --- a/src/resume.c +++ b/src/resume.c @@ -96,6 +96,15 @@ s3_resume(void) return; } + make_bios_writable(); + // reset mmconfig to make sure that we don't use PCIe to + // resume PCIe + dprintf(1, "resetting mmconfig\n"); + extern volatile u32 mmconfig; + mmconfig = 0; + dprintf(1, "mmconfig: 0x%x\n", mmconfig); +// make_bios_readonly(); + pic_setup(); smm_setup(); smp_resume(); -- 2.45.2

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[PATCH] resume: reset mmconfig to zero
by Omar Berrow Nov. 25, 2024

Nov. 25, 2024

I apologize for the previous thing sent on the mailing list. On wake it would attempt to use the ECAM space to restore access to ECAM, which wouldn't work because ECAM is disabled after reset. Signed-off-by: Omar Berrow <omarkberrow(a)gmail.com> --- src/hw/pci.c | 2 +- src/resume.c | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/hw/pci.c b/src/hw/pci.c index 8eda84b2..dfe4d92a 100644 --- a/src/hw/pci.c +++ b/src/hw/pci.c @@ -14,7 +14,7 @@ #define PORT_PCI_CMD 0x0cf8 #define PORT_PCI_DATA 0x0cfc -static u32 mmconfig; +volatile u32 mmconfig; static void *mmconfig_addr(u16 bdf, u32 addr) { diff --git a/src/resume.c b/src/resume.c index fb0b8a89..10b873c3 100644 --- a/src/resume.c +++ b/src/resume.c @@ -96,6 +96,15 @@ s3_resume(void) return; } + make_bios_writable(); + // reset mmconfig to make sure that we don't use PCIe to + // resume PCIe + dprintf(1, "resetting mmconfig\n"); + extern volatile u32 mmconfig; + mmconfig = 0; + dprintf(1, "mmconfig: 0x%x\n", mmconfig); +// make_bios_readonly(); + pic_setup(); smm_setup(); smp_resume(); -- 2.45.2

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[PATCH 0/2] add guest hint for memory layout, take two
by Gerd Hoffmann Nov. 22, 2024

Nov. 22, 2024

Gerd Hoffmann (2): update pci_pad_mem64 handling add fwcfg override for pci_pad_mem64 src/util.h | 1 + src/fw/paravirt.c | 13 +++++++++++++ src/fw/pciinit.c | 11 ++++++++--- 3 files changed, 22 insertions(+), 3 deletions(-) -- 2.47.0

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[PATCH] NVRAM bootorder
by Timothy Kenno Handojo Nov. 22, 2024

Nov. 22, 2024

This change allows seabios to load bootorder not only from CBFS but also from the NVRAM as well, making use of coreboot's cmos.layout. Tested on QEMU Q35 From 055a831ed9872b99bf6d060c70b495e286ded1ba Mon Sep 17 00:00:00 2001 From: Timothy Kenno Handojo <timkenhan(a)mailbox.org> Date: Thu, 31 Oct 2024 08:11:38 +0700 Subject: [PATCH] boot: Allow setting bootorder from CMOS entry The original bootorder from CBFS remains, but takes lower priority. Signed-off-by: Timothy Kenno Handojo <timkenhan(a)mailbox.org> --- Makefile | 2 +- src/boot.c | 9 +++- src/nvram.c | 130 ++++++++++++++++++++++++++++++++++++++++++++++++++++ src/nvram.h | 37 +++++++++++++++ 4 files changed, 176 insertions(+), 2 deletions(-) create mode 100644 src/nvram.c create mode 100644 src/nvram.h diff --git a/Makefile b/Makefile index d3341870..48f0b9ac 100644 --- a/Makefile +++ b/Makefile @@ -46,7 +46,7 @@ SRC32FLAT=$(SRCBOTH) post.c e820map.c malloc.c romfile.c x86.c \ fw/mtrr.c fw/xen.c fw/acpi.c fw/mptable.c fw/pirtable.c \ fw/smbios.c fw/romfile_loader.c fw/dsdt_parser.c hw/virtio-ring.c \ hw/virtio-pci.c hw/virtio-mmio.c hw/virtio-blk.c hw/virtio-scsi.c \ - hw/tpm_drivers.c hw/nvme.c sha256.c sha512.c + hw/tpm_drivers.c hw/nvme.c sha256.c sha512.c nvram.c SRC32SEG=string.c output.c pcibios.c apm.c stacks.c hw/pci.c hw/serialio.c DIRS=src src/hw src/fw vgasrc diff --git a/src/boot.c b/src/boot.c index 1effd802..0689d7de 100644 --- a/src/boot.c +++ b/src/boot.c @@ -21,6 +21,8 @@ #include "string.h" // memset #include "util.h" // irqtimer_calc #include "tcgbios.h" // tpm_* +#include "nvram.h" // get_nvram_bootorder + /**************************************************************** * Helper search functions @@ -250,8 +252,13 @@ loadBootOrder(void) { if (!CONFIG_BOOTORDER) return; + char *f = NULL; + + f = get_nvram_bootorder(); + + if (!f) + f = romfile_loadfile("bootorder", NULL); - char *f = romfile_loadfile("bootorder", NULL); if (!f) return; diff --git a/src/nvram.c b/src/nvram.c new file mode 100644 index 00000000..0634cf9c --- /dev/null +++ b/src/nvram.c @@ -0,0 +1,130 @@ +#include "nvram.h" +#include "string.h" // memcmp, strlen +#include "malloc.h" // malloc_low +#include "x86.h" // inb, outb +#include "output.h" // dprintf +#include "util.h" // cb_header, find_cb_table, find_cb_subtable + +#define CB_TAG_CMOS_OPTION_TABLE 0x00c8 +#define CB_TAG_OPTION 0x00c9 +#define CB_TAG_OPTION_CHECKSUM 0x00cc + + +u8 nvram_read(u8 addr){ + u16 rtc_port = addr < 128 ? RTC_PORT_STANDARD : RTC_PORT_EXTENDED; + + outb(addr, rtc_port); + return inb(rtc_port + 1); +} + +void nvram_write(u8 val, u8 addr) +{ + u16 rtc_port = addr < 128 ? RTC_PORT_STANDARD : RTC_PORT_EXTENDED; + + outb(addr, rtc_port); + outb(val, rtc_port + 1); +} + +struct nvram_accessor { + u8 (*read)(u8 reg); + void (*write)(u8 val, u8 reg); +}; + +struct nvram_accessor *use_nvram = &(struct nvram_accessor) { + nvram_read, + nvram_write +}; + +static struct cb_cmos_entries *lookup_cmos_entry(struct cb_cmos_option_table *option_table, const char *name) +{ + struct cb_cmos_entries *cmos_entry, *next; + int len = name ? strlen(name) : 0; + + /* CMOS entries are located right after the option table */ + cmos_entry = (struct cb_cmos_entries*)((unsigned char *)option_table + option_table->header_length); + while (cmos_entry) { + if (memcmp((const char*)cmos_entry->name, name, len) == 0) + return cmos_entry; + next = (struct cb_cmos_entries*)((unsigned char *)cmos_entry + cmos_entry->size); + cmos_entry = (next->tag == CB_TAG_OPTION) ? next : NULL; + } + + dprintf(1, "ERROR: No such CMOS option (%s)\n", name); + return NULL; +} + +static int get_cmos_value(const struct nvram_accessor *nvram, u32 bitnum, u32 len, void *valptr) +{ + u8 *value = valptr; + int offs = 0; + u32 addr, bit; + u8 reg8; + + /* Convert to byte borders */ + addr=(bitnum / 8); + bit=(bitnum % 8); + + /* Handle single byte or less */ + if(len <= 8) { + reg8 = nvram->read(addr); + reg8 >>= bit; + value[0] = reg8 & ((1 << len) -1); + return 0; + } + + /* When handling more than a byte, copy whole bytes */ + while (len > 0) { + len -= 8; + value[offs++]=nvram->read(addr++); + } + + return 0; +} + +int options_checksum_valid(const struct nvram_accessor *nvram, struct cb_cmos_checksum *option_checksum) +{ + int i; + int checksum_location = option_checksum->location / 8; + u16 checksum = 0, checksum_old; + + for(i = option_checksum->range_start; i <= option_checksum->range_end; i++) { + checksum += nvram->read(i); + } + + checksum_old = ((nvram->read(checksum_location)<<8) | nvram->read(checksum_location+1)); + + return (checksum_old == checksum); +} + +void *get_nvram_bootorder() +{ + const char *name = "bootorder"; + struct cb_header *cbh = find_cb_table(); + + if (!cbh) + return NULL; + struct cb_cmos_option_table *option_table = find_cb_subtable(cbh, CB_TAG_CMOS_OPTION_TABLE); + struct cb_cmos_checksum *option_checksum = find_cb_subtable(cbh, CB_TAG_OPTION_CHECKSUM); + if (option_table == NULL) { + dprintf(1, "Could not find coreboot option table.\n"); + return NULL; + } + + struct cb_cmos_entries *cmos_entry = lookup_cmos_entry(option_table, name); + + if (!cmos_entry) + return NULL; + int cmos_length = cmos_entry->length; + + /* extra byte to ensure 0-terminated strings */ + void *buf = malloc_low(cmos_length+1); + memset(buf, 0, cmos_length+1); + + if(!options_checksum_valid(use_nvram, option_checksum)) { + dprintf(1, "Invalid option checksum.\n"); + return NULL; + } + get_cmos_value(use_nvram, cmos_entry->bit, cmos_entry->length, buf); + + return buf; +} diff --git a/src/nvram.h b/src/nvram.h new file mode 100644 index 00000000..4c9d559e --- /dev/null +++ b/src/nvram.h @@ -0,0 +1,37 @@ +#ifndef __NVRAM_H +#define __NVRAM_H + +#include "types.h" // u32, u8 + +#define RTC_PORT_STANDARD 0x70 +#define RTC_PORT_EXTENDED 0x72 + +struct cb_cmos_option_table { + u32 tag; + u32 size; + u32 header_length; +}; + +#define CB_CMOS_MAX_NAME_LENGTH 32 +struct cb_cmos_entries { + u32 tag; + u32 size; + u32 bit; + u32 length; + u32 config; + u32 config_id; + u8 name[CB_CMOS_MAX_NAME_LENGTH]; +}; + +struct cb_cmos_checksum { + u32 tag; + u32 size; + u32 range_start; + u32 range_end; + u32 location; + u32 type; +}; + +void *get_nvram_bootorder(); + +#endif \ No newline at end of file -- 2.39.5

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