November 2019 - SeaBIOS - mail.coreboot.org

[PATCH] advanced_bootmenu: up to 35 entries (2 pages if >18), numpad support (console)
by Mike Banon April 25, 2020

April 25, 2020

Add support for up to 35 boot menu entries (2 pages if >18). To solve the ">10" problem currently experienced by SeaBIOS users (there are no 11, 12, etc. keys on a keyboard - so impossible to choose the last menu entries if you got >10 entries because of multiple hard drives / secondary payloads / floppies) - the boot menu has been extended to the letter keys. NOTE: TPM menu has been moved from T to M letter: it is at the end of keyboard's 3rd row of letters and "Trusted" is adjective while "Module" is a noun; alternatively could press '-'. Also, add support for a numpad. Small USB numpad could be really convenient for choosing the boot entries at coreboot boards used as (maybe headless) servers. '/' char on numpad could be used to open the boot menu or to exit it. If there are >10 boot menu entries - the numpad console interface will be enabled: press one or two digit keys and then ENTER to confirm your choice, or remove a digit by pressing the '.Del' key. Also you could call TPM with '-' key at any moment, or boot with a single key press of your fullsize keyboard. Signed-off-by: Mike Banon <mikebdp2 at gmail.com> (patch body is after the testing instructions below) This "advanced_bootmenu" patch is much more useful when used together with my "multiple_floppies" patch: [SeaBIOS] [PATCH v2] ramdisk: search for all available floppy images instead of one https://mail.coreboot.org/pipermail/seabios/2018-December/012670.html Sadly I haven't done the suggestions by Kevin (I have so many unfinished tasks) so the "multiple_floppies" patch is also not merged yet. But you could install both patches to your coreboot by executing this script while at ./coreboot dir: https://pastebin.com/raw/hv9sSuMU And here is a coreboot image for QEMU with these two patches applied and my collection of wonderful and useful floppies added to popular the entries list: https://github.com/mikebdp2/floparchive/blob/master/coreboot.rom?raw=true Descriptions of the most prominent floppies could be found here: http://dangerousprototypes.com/docs/Lenovo_G505S_hacking#Useful_floppies Run this coreboot.rom by executing this QEMU command: (some floppies are 64-bit) qemu-system-x86_64 -L . -m 768 -localtime -vga vmware -net nic,model=rtl8139 \ -net user -soundhw ac97 -bios ./coreboot.rom -boot menu=on -serial stdio Best regards, Mike Banon diff --git a/src/boot.c b/src/boot.c index 9f82f3c..f94dd27 100644 --- a/src/boot.c +++ b/src/boot.c @@ -463,6 +463,7 @@ get_keystroke(int msec) * Boot menu and BCV execution ****************************************************************/ +#define BOOTMENU_PAGE_SIZE 18 #define DEFAULT_BOOTMENU_WAIT 2500 // Show IPL option menu. @@ -478,59 +479,282 @@ interactive_bootmenu(void) ; char *bootmsg = romfile_loadfile("etc/boot-menu-message", NULL); - int menukey = romfile_loadint("etc/boot-menu-key", 1); - printf("%s", bootmsg ?: "\nPress ESC for boot menu.\n\n"); + int menukey = romfile_loadint("etc/boot-menu-key", 1); // custom menukey + printf("%s", bootmsg ?: "\nPress ESC or \\ / slash for boot menu.\n\n"); free(bootmsg); u32 menutime = romfile_loadint("etc/boot-menu-wait", DEFAULT_BOOTMENU_WAIT); enable_bootsplash(); int scan_code = get_keystroke(menutime); disable_bootsplash(); - if (scan_code != menukey) + if (scan_code != menukey && // custom menukey + scan_code != 1 && // ESC + scan_code != 43 && // '\' char on keyboard + scan_code != 53 && // '/' char on keyboard + scan_code != 98) { // '/' char on numpad + if (scan_code == -1) + printf("No key pressed.\n"); + else + printf("Not a menukey pressed.\n"); return; + } while (get_keystroke(0) >= 0) ; - printf("Select boot device:\n\n"); wait_threads(); - // Show menu items + char keyboard_keys[35] = {'1','2','3','4','5','6','7','8','9','0', + 'q','w','e','r','t','y','u','i','o','p', + 'a','s','d','f','g','h','j','k','l', + 'z','x','c','v','b','n'}; /* m = TPM */ + int numpad_scancodes[10] = { 82, 79, 80, 81, 75, 76, 77, 71, 72, 73 }; + int numpi = 0; // Key index: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9. + int digits = 0; // Numerical length of a current choice number. + int decode = 0; // Decode the current choice number into a letter? + int entry_id = 0; + char desc[77]; + + printf("Select boot device"); + + // Show menu items after counting them and determining a number of pages. + // Only 35 boot menu items (36 if to count a TPM) are supported currently. + int maxmenu = 0; struct bootentry_s *pos; - hlist_for_each_entry(pos, &BootList, node) { - char desc[77]; + hlist_for_each_entry(pos, &BootList, node) maxmenu++; - printf("%d. %s\n", maxmenu + + if (maxmenu > 10) { + if (maxmenu > 35) + maxmenu = 35; + if (maxmenu > BOOTMENU_PAGE_SIZE) + printf(" - page 1 :"); + else + printf(": "); + printf(" // press ENTER after your numpad input"); + if (maxmenu > BOOTMENU_PAGE_SIZE) + printf(" - if any -\n " + " // - or to switch between the pages...\n"); + else + printf(" (if any)\n\n"); + } else { + printf(":\n\n"); + } + + hlist_for_each_entry(pos, &BootList, node) { + if (entry_id == BOOTMENU_PAGE_SIZE) // Show only the first page. + break; + printf("%c. %s\n", keyboard_keys[entry_id] , strtcpy(desc, pos->description, ARRAY_SIZE(desc))); + entry_id++; } + int tpm_cshm = 0; if (tpm_can_show_menu()) { - printf("\nt. TPM Configuration\n"); + tpm_cshm = 1; + printf("\nm-. TPM Configuration"); } - - // Get key press. If the menu key is ESC, do not restart boot unless - // 1.5 seconds have passed. Otherwise users (trained by years of - // repeatedly hitting keys to enter the BIOS) will end up hitting ESC - // multiple times and immediately booting the primary boot device. - int esc_accepted_time = irqtimer_calc(menukey == 1 ? 1500 : 0); + printf("\n> "); + + // Do not restart boot on menukey press, unless DEFAULT_BOOTMENU_WAIT msecs + // have passed. Otherwise users (trained by years of repeatedly hitting keys + // to enter the BIOS) will end up hitting menukey multiple times and + // immediately booting the primary boot device. + int esc_accepted_time = irqtimer_calc(DEFAULT_BOOTMENU_WAIT); + int choice = 0, kb_choice = 0; + int page_num = 1; + int enter = 0; + int backspace = 0; + int tpm_show_menu = 0; for (;;) { scan_code = get_keystroke(1000); - if (scan_code == 1 && !irqtimer_check(esc_accepted_time)) - continue; - if (tpm_can_show_menu() && scan_code == 20 /* t */) { + if (scan_code == menukey || // custom menukey + scan_code == 1 || // ESC + scan_code == 43 || // '\' char on keyboard + scan_code == 53 || // '/' char on keyboard + scan_code == 98) { // '/' char on numpad + if (!irqtimer_check(esc_accepted_time)) + continue; + if (digits == 2) // Remove the decoded "(*)" + printf(" \b\b\b"); + /* Remove the existing input before printing a message. */ + for (; digits > 0; digits--) + printf("\b \b"); + printf("Menukey pressed.\n"); + return; + } + kb_choice = 0; + /* 4 rows of keyboard_keys: 1 row with numbers, 3 rows with letters. + Use any of them to select a boot device (except the TPM 'm-' keys) */ + // 1st range: 1-9 and 0 (10) keys <==> 2-11 scan codes <==> 1-10 choice + if (scan_code >= 2 && scan_code <= 11) kb_choice = scan_code - 1; + // 2nd range: Q-P row of letters <==> 16-25 scan codes <==> 11-20 choice + if (scan_code >= 16 && scan_code <= 25) kb_choice = scan_code - 5; + // 3rd range: A-L row of letters <==> 30-38 scan codes <==> 21-29 choice + if (scan_code >= 30 && scan_code <= 38) kb_choice = scan_code - 9; + // 4th range: Z-N row of letters <==> 44-49 scan codes <==> 30-35 choice + if (scan_code >= 44 && scan_code <= 49) kb_choice = scan_code - 14; + // ENTER: (28) on keyboard, (96) on numpad. + if (scan_code == 28 || scan_code == 96) + enter = 1; + // BCKSPC: '<-'(14) and 'Delete'(111) on keyboard, '.Del'(83) on numpad. + if (scan_code == 14 || scan_code == 111 || scan_code == 83) + backspace = 1; + // TPM keys: 'm'(50) and '-'(12) chars on keyboard, '-'(74) on numpad. + if ((scan_code == 50 || scan_code == 12 || scan_code == 74) && tpm_cshm) + tpm_show_menu = 1; + + if (kb_choice != 0 || tpm_show_menu) { + if (kb_choice > maxmenu) { + if (!tpm_show_menu) + continue; + } else { + choice = kb_choice; + } + if (digits == 2) // Remove the decoded "(*)" + printf(" \b\b\b"); + /* Remove the existing input before printing a choice. */ + for (; digits > 0; digits--) + printf("\b \b"); + if (!tpm_show_menu) { + // Choice is any of the detected boot devices ==> lets boot! + break; + } + } else { + // Internal/USB Numpad console interface. + if (digits < 9) { + for (numpi = 0; numpi < 10; numpi++) { + if (scan_code == numpad_scancodes[numpi]) { + if (maxmenu <= 10) { // Console interface is not needed. + if ((numpi != 0 && numpi <= maxmenu) || + (numpi == 0 && 10 <= maxmenu)) { // 10(0) + choice = numpi; + enter = 1; // Fake ENTER to boot this entry now. + } else { // If no such an entry, don't try to boot. + break; + } + } else { + if (digits == 2) { + printf(" \b\b\b"); // Remove the decoded "(*)" + if (choice == 0) { + printf("\b\b \b\b"); // Remove "10". + digits = 0; + } + } + choice = 10 * choice + numpi; + } + if (choice > 0) { + printf("%d", numpi); // Print the entered digit. + digits++; + } else { + if (10 <= maxmenu) + printf("10(0)\b\b\b"); + else + printf("10(?)\b\b\b"); + digits = 2; + } + if (choice > 9 && digits == 2) // Decode into a letter. + decode = 1; + break; + } + } + } + if (backspace && digits > 0) { + backspace = 0; + choice = choice / 10; + if (digits == 2) { + printf(" \b\b\b"); // Remove the decoded "(*)" + // 0 turned into 10: one more Backspace is needed to remove. + if (choice == 0) { + printf("\b \b"); + digits--; + } + } + printf("\b \b"); // Remove the last entered digit. + digits--; + if (choice > 9 && digits == 2) // Decode into a letter. + decode = 1; + } + if (decode) { // Decode the current choice number into a letter. + decode = 0; + if (choice <= maxmenu) { + printf("(%c)", keyboard_keys[choice-1]); + } else { + if (tpm_cshm && choice == 36) + printf("(m)"); // For TPM. + else + printf("(?)"); // No matching letter found. + } + printf("\b\b\b"); // Move a cursor before the "(*)" + } + } + + if (enter) { + enter = 0; + if (choice == 0) { + if (digits == 2) { // for 0 that turned into 10 + if (10 <= maxmenu) + break; + else + continue; + } + // If there are two pages - switch between them. + if (maxmenu > BOOTMENU_PAGE_SIZE) { + entry_id = 0; + page_num = 3 - page_num; // 3 - 1 = 2; 3 - 2 = 1. + printf("\n\nSelect boot device - page %d :" + " // press ENTER after your numpad input" + " - if any -\n " + " // - or to switch between the pages...\n", + page_num); + hlist_for_each_entry(pos, &BootList, node) { + if ((page_num == 1 && entry_id == BOOTMENU_PAGE_SIZE) || + (page_num == 2 && entry_id == 35)) + break; + if (page_num == 1 || entry_id >= BOOTMENU_PAGE_SIZE) + printf("%c. %s\n", keyboard_keys[entry_id], + strtcpy(desc, pos->description, ARRAY_SIZE(desc))); + entry_id++; + } + if (tpm_cshm) + printf("\nm-. TPM Configuration"); + printf("\n> "); + } + } else { + if (choice > maxmenu) { + if (tpm_cshm && choice == 36) + tpm_show_menu = 1; + } else { + // Choice is any of the detected boot devices ==> lets boot! + break; + } + } + } + + if (tpm_show_menu) { + tpm_show_menu = 0; + choice = 0; + if (digits == 0) + printf("TPM key pressed."); + else + digits = 0; printf("\n"); tpm_menu(); + printf("> "); } - if (scan_code >= 1 && scan_code <= maxmenu+1) - break; + } + + if (choice == 0) // 10(0) + choice = 10; + + if (digits == 0 && choice < 36) { + printf("%c", keyboard_keys[choice-1]); + if (choice > 9) // Decode into a number. + printf("(%d)", choice); } printf("\n"); - if (scan_code == 0x01) - // ESC - return; // Find entry and make top priority. - int choice = scan_code - 1; hlist_for_each_entry(pos, &BootList, node) { if (! --choice) break; diff --git a/src/config.h b/src/config.h index 93c8dbc..f85cc14 100644 --- a/src/config.h +++ b/src/config.h @@ -19,7 +19,7 @@ // Space to reserve in high-memory for tables #define BUILD_MAX_HIGHTABLE (256*1024) // Largest supported externaly facing drive id -#define BUILD_MAX_EXTDRIVE 16 +#define BUILD_MAX_EXTDRIVE 36 // Number of bytes the smbios may be and still live in the f-segment #define BUILD_MAX_SMBIOS_FSEG 600 // Maximum number of bytes the mptable may be and still be copied to f-segment

2 2

Custom-sized, large floppy images?
by Rafael Send April 3, 2020

April 3, 2020

Hi, I'm working on stuffing a bootable Linux distro into coreboot. In QEMU I already succeded by using coreboot's built-in kernel loading mechanism, but that's without SeaBIOS. I'd love to have it as a SeaBIOS payload so I can also boot other things, but I guess I'd have to create a custom-sized floppy image for this or figure out how to create an ELF payload out of a Linux kernel (I'm open to either, but I wasn't able to find any documentation on the ELF method). The guy who put Win 3.1 in coreboot attempted the floppy method, but according to his article he did not find success with this method due to unknown and complex issues in the floppy-side logic of SeaBIOS. So, I'm making the question explicit: What would it take to support custom-sized floppy images? In particular, I'm thinking of a 16MB device... Alternatively, would it be possible to create an ELF file out of a Linux kernel+initrd / bootable image? Cheers, Rafael

4 28

strange behavior (regression?) with SeaBIOS + iPXE + WDSNBP.COM
by Laszlo Ersek Jan. 2, 2020

Jan. 2, 2020

Hi Michael & Lists, I'd like to ask for ideas with the following problem we have. (1) There is a functional iPXE + WDS setup, with iPXE built as a traditional BIOS PCI option ROM, using CONFIG=qemu. Accordingly the platform is qemu, with SeaBIOS, and the NIC is virtio-net-pci. I don't know anything about the particulars of the WDS setup at this point, only that the boot loader program it exposes is WDSNBP.COM. (2) The setup works fine when iPXE is built at commit 4e85b2708fa0 ("[virtio] Use host-specified MTU when available", 2017-01-23). (3) When iPXE is built at commit 133f4c47baef ("[build] Handle R_X86_64_PLT32 from binutils 2.31", 2018-09-17), the setup breaks. The symptom is that iPXE fetches WDSNBP.COM just fine, but WDSNBP.COM, rather than doing whatever it does otherwise, keeps PXE-booting itself (3+ times), and finally aborts. Consider the following log output (my undertanding is that all this is logged by WDSNBP.COM) > Downloaded WDSNBP... > > Press F12 for network service boot > Architecture: x64 > WDSNBP started using DHCP Referral. > Contacting Server: ... (Gateway: ...) > Contacting Server: ... > TFTP Download: boot\x86\wdsnbp.com This block repeats approx. 3 times, after which the following is displayed: > Windows Deployment Services: PXE Boot Aborted. > Could not boot image: Error 0x7f8d8101 (http://ipxe.org/7f8d8101) > No more network devices > > No bootable device My understanding is that the first line from this last block is printed by WDSNBP.COM, the second line by iPXE (in pxe_start_nbp()), the third line also by iPXE, and the last one by SeaBIOS. This seems to indicate that WDSNBP.COM exits with an error code, and pxe_start_nbp() logs it as "Error 0x7f8d8101". (4) Now, after a bit of searching the web, I've found the following articles, which indicate that the WDS (= server side) setup is incorrect: (4a) "disable NetBios over TCPIP, on the WDS server" https://techthoughts.info/pxe-booting-wds-dhcp-scope-vs-ip-helpers/#comment… https://social.technet.microsoft.com/Forums/ie/en-US/f3883e8b-1039-477d-999… (4b) "cover all combinations of forward and backwards slashes in ReadFilter, on the WDS server" http://ipxe.org/appnote/chainload_wds#tftp_loops However: the regression appears to be a function of *only* the git commit at which we build iPXE. It seems so deterministic that we bisected commit range 4e85b2708fa0..133f4c47baef. (Hence we have not captured the network traffic yet, nor have we investigated the WDS server config.) The "culprit" commit is ea29122a70c6 ("[http] Include error messages for 4xx and 5xx response codes", 2017-12-28). (5) Which makes no sense to me, unfortunately. :( Commit ea29122a70c6 adds the "http_errors" array to the code. According to src/include/ipxe/tables.h and the build artifact src/bin/1af41000.rom.tmp.map this new array is placed in a new section called .textdata.tbl.errortab.01 Trying to retro-fit those facts to the symptom encountered, I came up with the idea that *maybe* the new array (or section) causes a memory allocation failure in WDSNBP.COM -- due to increased memory footprint of iPXE. Which then leads to the misbehavior of WDSNBP.COM. After all, WDSNBP.COM is a 16-bit real-mode program: https://support.microsoft.com/en-us/help/4468601/pxe-boot-in-configuration-… so it could be susceptible to the size & fragmentation of the RAM that is under 640KB. (6) Unfortunately, this "low RAM exhaustion" idea doesn't seem to hold water. There are at least two counter-arguments: (6a) if I revert commit ea29122a70c6 on top of commit 133f4c47baef, then the issue does *not* go away. (The issue also does not go away if I remove the "netdev_errors" array, also on top of commit 133f4c47baef -- that's a larger array.) (... In theory anyway, this might not necessarily disprove the memory exhaustion idea. What if the iPXE footprint grows, over the ea29122a70c6..133f4c47baef so much, for independent reasons, that reverting ea29122a70c6 at the end cannot compensate for that increase?) (6b) I added "DEBUG=pxe_call:1" to the "make" command, and compared the debug messages printed by pxe_start_nbp(), between 4e85b2708fa0 and 133f4c47baef. Alas, the debug messages are identical: > PXE NBP starting with netdev net0, code 9c6c:0802, data 9cf0:2ce0 which to me suggests that there is no change in the amount of memory that is made available to WDSNBP.COM -- its code and data continue to start at 0x9_CEC2 and 0x9_FBE0, respectively. Any hints as to what could be going wrong? Thanks! Laszlo

2 5

[PATCH 4/4] serialio: Support for pci serial ports
by Your Real Name Dec. 10, 2019

Dec. 10, 2019

From f65c435b8e3caf7249a3fb25150e7055898ccc12 Mon Sep 17 00:00:00 2001 From: gaobin <gaobin(a)amazon.com> Date: Fri, 18 Oct 2019 23:00:21 -0700 Subject: [PATCH 4/4] serialio: Support for pci serial ports Some Intel PCHs integrate pci uarts which are used for serial port debugging. For compatibility purpose, BIOS implementation may assign 0x3f8 to the pci uart's io bar at PEI stage, later during DXE stage the pci uart's bar is re-assigned to a different address. As a result, we can't use the hard coded IO port 0x3f8 in SeaBIOS for debugging. Instead, we need read the port base address from the pci uart's BAR, either an IO BAR, or a 32bit memory BAR. This patch adds support for pci serial port debugging. Signed-off-by: gaobin <gaobin(a)amazon.com> --- src/Kconfig | 34 +++++++++++++++++++++++++++++++++- src/hw/serialio.c | 29 +++++++++++++++++++++++++++-- 2 files changed, 60 insertions(+), 3 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 6606ce4..6d9ce3b 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -550,8 +550,40 @@ menu "Debugging" default 0x3f8 help Base port for serial - generally 0x3f8, 0x2f8, 0x3e8, or 0x2e8. - config DEBUG_SERIAL_MMIO + config DEBUG_SERIAL_PCI_IO depends on DEBUG_LEVEL != 0 && !DEBUG_SERIAL + bool "Serial port debugging via PCI IO" + default n + help + Send debugging information to PCI serial port. + The base address of the uart is in the PCI device's IO bar. + config DEBUG_SERIAL_PCI_MEM32 + depends on DEBUG_LEVEL != 0 && !DEBUG_SERIAL && !DEBUG_SERIAL_PCI_IO + bool "Serial port debugging via PCI MEM32" + default n + help + Send debugging information to PCI serial port. + The base address of the uart is in the PCI device's MEM32 bar. + config DEBUG_SERIAL_PCI_BDF + depends on DEBUG_SERIAL_PCI_IO || DEBUG_SERIAL_PCI_MEM32 + hex "Serial port PCI bus/device/function" + range 0 ffff + help + 16bit hex of B:D:F of the PCI serial port. + Bit 15:8 - bus, bit 7:3 - device, bit 2:0 - function + E.g. for a PCI device: bus 0x0, dev 0x1a, func 0x1 you + should input 00d1. + config DEBUG_SERIAL_PCI_BAR + depends on DEBUG_SERIAL_PCI_IO || DEBUG_SERIAL_PCI_MEM32 + hex "Serial port PCI BAR index (0 - 5)" + range 0 5 + default 0 + help + The index of the BAR where the base address would be read + from for the PCI serial port. Only IO BAR and 32bit memory + BAR are supported. + config DEBUG_SERIAL_MMIO + depends on DEBUG_LEVEL != 0 && !DEBUG_SERIAL && !DEBUG_SERIAL_PCI_IO && !DEBUG_SERIAL_PCI_MEM32 bool "Serial port debugging via memory mapped IO" default n help diff --git a/src/hw/serialio.c b/src/hw/serialio.c index 3163344..9a8565c 100644 --- a/src/hw/serialio.c +++ b/src/hw/serialio.c @@ -9,6 +9,7 @@ #include "output.h" // dprintf #include "serialio.h" // serial_debug_preinit #include "x86.h" // outb +#include "pci.h" //pci_config_readw /**************************************************************** @@ -23,6 +24,15 @@ serial_debug_write(u8 offset, u8 val) { if (CONFIG_DEBUG_SERIAL) { outb(val, CONFIG_DEBUG_SERIAL_PORT + offset); + } else if (CONFIG_DEBUG_SERIAL_PCI_IO) { + u16 base = pci_config_readw(CONFIG_DEBUG_SERIAL_PCI_BDF, + 0x10 + CONFIG_DEBUG_SERIAL_PCI_BAR*4) & (~0x3); + outb(val, base + offset); + } else if (CONFIG_DEBUG_SERIAL_PCI_MEM32) { + ASSERT32FLAT(); + u32 base = pci_config_readl(CONFIG_DEBUG_SERIAL_PCI_BDF, + 0x10 + CONFIG_DEBUG_SERIAL_PCI_BAR*4) & (~0x7); + writeb((void*)base + 4*offset, val); } else if (CONFIG_DEBUG_SERIAL_MMIO) { ASSERT32FLAT(); writeb((void*)CONFIG_DEBUG_SERIAL_MEM_ADDRESS + 4*offset, val); @@ -35,6 +45,17 @@ serial_debug_read(u8 offset) { if (CONFIG_DEBUG_SERIAL) return inb(CONFIG_DEBUG_SERIAL_PORT + offset); + if (CONFIG_DEBUG_SERIAL_PCI_IO) { + u16 base = pci_config_readw(CONFIG_DEBUG_SERIAL_PCI_BDF, + 0x10 + CONFIG_DEBUG_SERIAL_PCI_BAR*4) & (~0x3); + return inb(base + offset); + } + if (CONFIG_DEBUG_SERIAL_PCI_MEM32) { + ASSERT32FLAT(); + u32 base = pci_config_readl(CONFIG_DEBUG_SERIAL_PCI_BDF, + 0x10 + CONFIG_DEBUG_SERIAL_PCI_BAR*4) & (~0x7); + return readb((void*)base + 4*offset); + } if (CONFIG_DEBUG_SERIAL_MMIO) { ASSERT32FLAT(); return readb((void*)CONFIG_DEBUG_SERIAL_MEM_ADDRESS + 4*offset); @@ -65,7 +86,9 @@ serial_debug_preinit(void) static void serial_debug(char c) { - if (!CONFIG_DEBUG_SERIAL && (!CONFIG_DEBUG_SERIAL_MMIO || MODESEGMENT)) + if (!CONFIG_DEBUG_SERIAL && !CONFIG_DEBUG_SERIAL_PCI_IO && + ((!CONFIG_DEBUG_SERIAL_MMIO && !CONFIG_DEBUG_SERIAL_PCI_MEM32) || + MODESEGMENT)) return; int timeout = DEBUG_TIMEOUT; while ((serial_debug_read(SEROFF_LSR) & 0x20) != 0x20) @@ -87,7 +110,9 @@ serial_debug_putc(char c) void serial_debug_flush(void) { - if (!CONFIG_DEBUG_SERIAL && (!CONFIG_DEBUG_SERIAL_MMIO || MODESEGMENT)) + if (!CONFIG_DEBUG_SERIAL && !CONFIG_DEBUG_SERIAL_PCI_IO && + ((!CONFIG_DEBUG_SERIAL_MMIO && !CONFIG_DEBUG_SERIAL_PCI_MEM32) || + MODESEGMENT)) return; int timeout = DEBUG_TIMEOUT; while ((serial_debug_read(SEROFF_LSR) & 0x60) != 0x60) -- 2.17.1

3 11

[PATCH 3/4] csm: Enable boot from pci option rom
by Your Real Name Dec. 10, 2019

Dec. 10, 2019

From 9ca6590769692b99e98acf48acc3ce700238e451 Mon Sep 17 00:00:00 2001 From: gaobin <gaobin(a)amazon.com> Date: Thu, 19 Sep 2019 22:47:43 -0700 Subject: [PATCH 3/4] csm: Enable boot from pci option rom In csm mode, the bev pointer of the pci option rom was not added to the bootentry list, resulting in failure to boot from pci option rom. This patch fixed it. Signed-off-by: gaobin <gaobin(a)amazon.com> --- src/fw/csm.c | 18 ++++++++++++++++++ src/optionroms.c | 2 +- src/util.h | 1 + 3 files changed, 20 insertions(+), 1 deletion(-) diff --git a/src/fw/csm.c b/src/fw/csm.c index c8111cd..8e2a1aa 100644 --- a/src/fw/csm.c +++ b/src/fw/csm.c @@ -19,6 +19,7 @@ #include "std/acpi.h" // RSDP_SIGNATURE #include "std/bda.h" // struct bios_data_area_s #include "std/optionrom.h" // struct rom_header +#include "std/pnpbios.h" // PNP_SIGNATURE #include "util.h" // copy_smbios #define UINT8 u8 @@ -218,12 +219,16 @@ handle_csm_0003(struct bregs *regs) regs->ax = 1; } +static int rom_instance; + /* Legacy16DispatchOprom */ static void handle_csm_0005(struct bregs *regs) { EFI_DISPATCH_OPROM_TABLE *table = MAKE_FLATPTR(regs->es, regs->bx); struct rom_header *rom; + struct pnp_data *pnp; + u64 sources[(BUILD_BIOS_ADDR - BUILD_ROM_START) / OPTION_ROM_ALIGN]; u16 bdf; if (!CONFIG_OPTIONROMS) { @@ -250,6 +255,19 @@ handle_csm_0005(struct bregs *regs) rom_confirm(rom->size * 512); + // PnP rom - check for BEV and BCV boot capabilities. + pnp = (void*)((u8*)rom + rom->pnpoffset); + if (pnp->signature == PNP_SIGNATURE) { + if (pnp->bev) + boot_add_bev(FLATPTR_TO_SEG(rom), pnp->bev, pnp->productname, + getRomPriority(sources, rom, rom_instance++)); + else if (pnp->bcv) + boot_add_bcv(FLATPTR_TO_SEG(rom), pnp->bcv, pnp->productname, + getRomPriority(sources, rom, rom_instance++)); + } else { + dprintf(1, "rom 0x%p is not PnP rom, no BEV and BCV capability\n", table); + } + regs->bx = 0; // FIXME regs->ax = 0; } diff --git a/src/optionroms.c b/src/optionroms.c index e906ab9..4f3848d 100644 --- a/src/optionroms.c +++ b/src/optionroms.c @@ -153,7 +153,7 @@ setRomSource(u64 *sources, struct rom_header *rom, u64 source) sources[((u32)rom - BUILD_ROM_START) / OPTION_ROM_ALIGN] = source; } -static int +int getRomPriority(u64 *sources, struct rom_header *rom, int instance) { u64 source = sources[((u32)rom - BUILD_ROM_START) / OPTION_ROM_ALIGN]; diff --git a/src/util.h b/src/util.h index b173fa8..0a52338 100644 --- a/src/util.h +++ b/src/util.h @@ -217,6 +217,7 @@ int is_pci_vga(struct pci_device *pci); void optionrom_setup(void); void vgarom_setup(void); void s3_resume_vga(void); +int getRomPriority(u64 *sources, struct rom_header *rom, int instance); extern int ScreenAndDebug; // pcibios.c -- 2.17.1

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[PATCH 2/4] pci: Allow scanning pci bus number up to 255 in CSM mode
by Your Real Name Dec. 4, 2019

Dec. 4, 2019

From 3bf91481863ec504d113aa6b94827bf92840e291 Mon Sep 17 00:00:00 2001 From: gaobin <gaobin(a)amazon.com> Date: Thu, 19 Sep 2019 11:23:04 -0700 Subject: [PATCH 2/4] pci: Allow scanning pci bus number up to 255 in CSM mode On real hardware especially server platforms, there are many pci devices, bridges, either SoC integrated or addon. They can exhaust all the pci bus numbers. So when scanning the pci bus, we need to allow the bus number up to 255. Signed-off-by: gaobin <gaobin(a)amazon.com> --- src/hw/pcidevice.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/hw/pcidevice.c b/src/hw/pcidevice.c index 8853cf7..acf15b4 100644 --- a/src/hw/pcidevice.c +++ b/src/hw/pcidevice.c @@ -26,6 +26,12 @@ pci_probe_devices(void) struct hlist_node **pprev = &PCIDevices.first; int extraroots = romfile_loadint("etc/extra-pci-roots", 0); int bus = -1, lastbus = 0, rootbuses = 0, count=0; + + // On real hardware especially server platforms, the bus number + // could run up to the top value, i.e. 0xff + if (CONFIG_CSM) + extraroots = 0xff; + while (bus < 0xff && (bus < MaxPCIBus || rootbuses < extraroots)) { bus++; int bdf; -- 2.17.1

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csm: Call pci_probe_devices() late until PrepareToBoot is invoked by UEFI
by Your Real Name Dec. 2, 2019

Dec. 2, 2019

From 7dd0e8b98c71254148180b3cc432de1c4936526c Mon Sep 17 00:00:00 2001 From: gaobin <gaobin(a)amazon.com> Date: Thu, 19 Sep 2019 11:17:46 -0700 Subject: [PATCH 1/4] csm: Call pci_probe_devices() late until PrepareToBoot is invoked by UEFI On real hardware, some PCI devices are not detectable when UEFI BIOS invokes our InitializeYourself() function. But they are guaranteed to be available before UEFI invokes our PreparToBoot() function. Signed-off-by: gaobin <gaobin(a)amazon.com> --- src/fw/csm.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/fw/csm.c b/src/fw/csm.c index 8359bcb..c8111cd 100644 --- a/src/fw/csm.c +++ b/src/fw/csm.c @@ -63,7 +63,6 @@ static void csm_maininit(struct bregs *regs) { interface_init(); - pci_probe_devices(); csm_compat_table.PnPInstallationCheckSegment = SEG_BIOS; csm_compat_table.PnPInstallationCheckOffset = get_pnp_offset(); @@ -143,6 +142,12 @@ handle_csm_0002(struct bregs *regs) return; } + // On real hardware, some PCI devices are not detectable when + // UEFI invokes our InitializeYourself() function. But they + // are guaranteed to be available before UEFI invokes our + // PreparToBoot() function. + pci_probe_devices(); + dprintf(3, "PrepareToBoot table %04x:%04x\n", regs->es, regs->bx); struct e820entry *p = (void *)csm_compat_table.E820Pointer; -- 2.17.1

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1.13 release?
by Gerd Hoffmann Nov. 19, 2019

Nov. 19, 2019

Hi, Almost a year since 1.12.0 was tagged (Nov 17th to be exact), time to plan the 1.13 release I think ... How about freeze in a week or two, release by mid-november? Pending stuff I'm aware of is the disk geometry patch series. The corresponding qemu series is still waiting to be merged. There already was a pull request for it though, it only was dropped due to a regression showing up, so I think there is still a chance that it'll be merged shortly given that no objections where raised during review. Anything else which should be considered for 1.13? cheers, Gerd

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[PATCH] ahci: zero-initialize port struct
by Gerd Hoffmann Nov. 15, 2019

Nov. 15, 2019

Specifically port->driver.lchs needs clearing, otherwise seabios will try interpret whatever random crap happens to be there as disk geometry, which may or may not break boot depending on how lucky you are. Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/hw/ahci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/hw/ahci.c b/src/hw/ahci.c index 97a072a1ca81..d45b4307ec68 100644 --- a/src/hw/ahci.c +++ b/src/hw/ahci.c @@ -345,6 +345,7 @@ ahci_port_alloc(struct ahci_ctrl_s *ctrl, u32 pnr) warn_noalloc(); return NULL; } + memset(port, 0, sizeof(*port)); port->pnr = pnr; port->ctrl = ctrl; port->list = memalign_tmp(1024, 1024); -- 2.18.1

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[PATCH 0/2] tpm: Defend against TPM sending unexpected short packets
by Stefan Berger Nov. 13, 2019

Nov. 13, 2019

This series of patches addresses issues that may arise if a TPM sends unexpected short packets. Stefan Stefan Berger (2): tpm: Require a response to have minimum size of a valid response header tcgbios: Check for enough bytes returned from TPM2_GetCapability src/hw/tpm_drivers.c | 3 ++- src/tcgbios.c | 13 +++++++++++-- 2 files changed, 13 insertions(+), 3 deletions(-) -- 2.20.1

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