August 2012 - SeaBIOS - mail.coreboot.org

Re: [SeaBIOS] int10 handling
by Kevin O'Connor Aug. 29, 2012

Aug. 29, 2012

On Wed, Aug 29, 2012 at 09:36:44AM +0200, Christian Gmeiner wrote: > 2012/8/29 Kevin O'Connor <kevin(a)koconnor.net>: > > On Tue, Aug 28, 2012 at 05:11:22PM +0200, Christian Gmeiner wrote: > >> Hi all, > >> > >> I have made some progress in my flat panel work, but I run into a very > >> interesting problem. > >> It looks like that int10 is not handled by VBios but by SeaBios itself. > > > > The SeaBIOS int10 handler is overwritten by the vgabios. So, for some > > reason the vgabios didn't install a handler. The log excerpt you > > included doesn't go far enough back to see what happenend during the > > vgabios execution. Make sure you are running the vgabios from SeaBIOS > > (not coreboot) and add debugging to it to verify where it is failing. > > > > thanks for the hint... I let coreboot load the option rom to 0xc0000 > but let it not > start and in SeaBios I am using CONFIG_OPTIONROMS_DEPLOYED to start > the loaded VBios. But there is lot to do before the bootsplash gets shown :( SeaBIOS needs to be the sole executor of option roms. Things tend to mysteriously break in any other configuration. -Kevin

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Failed flash recovery & dual BIOS support
by Fred . Aug. 29, 2012

Aug. 29, 2012

Add support for "dual BIOS" and failed flash recovery. Many motherboards have 2 firmware ICs. Motherboard manufacturers tend to market this as "dual BIOS". It checks the integrity of the BIOS and if it fails the test, then it boots using the other firmware image on the other circuit.

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Re: [SeaBIOS] int10 handling
by Kevin O'Connor Aug. 29, 2012

Aug. 29, 2012

On Tue, Aug 28, 2012 at 05:11:22PM +0200, Christian Gmeiner wrote: > Hi all, > > I have made some progress in my flat panel work, but I run into a very > interesting problem. > It looks like that int10 is not handled by VBios but by SeaBios itself. The SeaBIOS int10 handler is overwritten by the vgabios. So, for some reason the vgabios didn't install a handler. The log excerpt you included doesn't go far enough back to see what happenend during the vgabios execution. Make sure you are running the vgabios from SeaBIOS (not coreboot) and add debugging to it to verify where it is failing. -Kevin

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int10 handling
by Christian Gmeiner Aug. 28, 2012

Aug. 28, 2012

Hi all, I have made some progress in my flat panel work, but I run into a very interesting problem. It looks like that int10 is not handled by VBios but by SeaBios itself. ... |0f7a0000| send_cmd : read error (status=51 err=04) |0f7a5000| pmm_free 0x0f7bf000 (detail=0x0f7a6690) |0f7a5000| pmm_free 0x0f7bef80 (detail=0x0f7a6660) |0f7a5000| pmm_free 0x0f7bef00 (detail=0x0f7a6630) |0f7a5000| pmm_free 0x0f7a66f0 (detail=0x0f7a6740) |0f7a0000| pmm_free 0x0f7a5000 (detail=0x0f7a66c0) \0f7a5000/ End thread |0f7a0000| ata_pio_transfer id=0x0f7a0f94 write=0 count=1 bs=512 buf=0x0f7a0d94 |0f7a0000| Read sector id=0x0f7a0f94 dest=0x0f7a0d94 |0f7a0000| pmm_malloc zone=0x0f7afe9b handle=ffffffff size=44 align=10 ret=0x000fdb10 (detail=0x0f7a6740) |0f7a0000| pmm_malloc zone=0x0f7afe93 handle=ffffffff size=80 align=10 ret=0x0f7a66c0 (detail=0x0f7a6710) |0f7a0000| ata0-0: SFCF4096H2BI2SA I Q1 311 STD ATA-0 Hard-Disk (3919 MiBytes) |0f7a0000| pmm_malloc zone=0x0f7afe93 handle=ffffffff size=20 align=10 ret=0x0f7a6670 (detail=0x0f7a6690) |0f7a0000| Registering bootable: ata0-0: SFCF4096H2BI2SA I Q1 311 STD ATA-0 Hard-Disk (3919 MiBytes) (type:2 prio:103 data:fdb10) |0f7a0000| ata_detect resetresult=400f |0f7a0000| powerup iobase=1f0 st=50 |0f7a0000| powerup iobase=1f0 st=0 |0f7a0000| ata_detect ata0-1: sc=55 sn=aa dh=b0 |0f7a0000| send_cmd : DRQ not set (status 00) pmm_free 0x0f7a0000 (detail=0x0f7a63d0) \0f7a0000/ End thread All threads complete. handle_08 handle_76 enter handle_16: a=00000100 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d58 cs=f000 ip=e985 f=0202 handle_08 enter handle_10: a=00000e50 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am enter handle_10: a=00000e72 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am enter handle_10: a=00000e65 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am handle_08 enter handle_10: a=00000e73 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am enter handle_10: a=00000e73 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am enter handle_10: a=00000e20 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am enter handle_10: a=00000e46 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am handle_08 enter handle_10: a=00000e31 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am enter handle_10: a=00000e32 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am enter handle_10: a=00000e20 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am handle_08 enter handle_10: a=00000e66 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am enter handle_10: a=00000e6f b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am enter handle_10: a=00000e72 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am handle_08 enter handle_10: a=00000e20 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am enter handle_10: a=00000e62 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am enter handle_10: a=00000e6f b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am enter handle_10: a=00000e6f b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am handle_08 enter handle_10: a=00000e74 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am enter handle_10: a=00000e20 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am enter handle_10: a=00000e6d b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am handle_08 enter handle_10: a=00000e65 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am enter handle_10: a=00000e6e b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am enter handle_10: a=00000e75 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am enter handle_10: a=00000e2e b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am handle_08 enter handle_10: a=00000e0d b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d64 cs=f000 ip=c2de f=0202 Here I am enter handle_10: a=00000e0a b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am enter handle_10: a=00000e0d b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d64 cs=f000 ip=c2de f=0202 Here I am handle_08 enter handle_10: a=00000e0a b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006d6c cs=f000 ip=c2de f=0202 Here I am Checking for bootsplash pmm_malloc zone=0x0f7afe93 handle=ffffffff size=921655 align=10 ret=0x0f6c5360 (detail=0x0f7a6640) Copying romfile 'bootsplash.bmp' (len 921654) Copying data 921654@0xffe2f3a8 to 921654@0x0f6c5360 handle_08 handle_08 handle_08 handle_08 handle_08 handle_08 handle_08 handle_08 handle_08 handle_08 handle_08 handle_08 handle_08 handle_08 handle_08 handle_08 start showing bootsplash pmm_malloc zone=0x0f7afe97 handle=ffffffff size=256 align=10 ret=0x0008ff00 (detail=0x0f7a6610) pmm_malloc zone=0x0f7afe97 handle=ffffffff size=256 align=10 ret=0x0008fe00 (detail=0x0f7a65e0) handle_08 enter handle_10: a=00004f00 b=00000000 c=00000000 d=00000000 ds=0000 es=8ff0 ss=0000 si=00000000 di=00000000 bp=00000000 sp=00006dbc cs=f000 ip=c2de f=0202 Here I am No VBE2 found. was 32454256 pmm_free 0x0f6c5360 (detail=0x0f7a6640) pmm_free 0x0008ff00 (detail=0x0f7a6610) pmm_free 0x0008fe00 (detail=0x0f7a65e0) ... the int10 4f00 should be handled by vbe.c in the VBIOS but it is handled by src/misc.c - "Here I am" output. I am running latest git version of SeaBios with some changes - patch attached. I see nothing that is wrong as the patch only extends the geode stuff. I am quite happy for every hint. --- Christian Gmeiner, MSc

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Next release
by Kevin O'Connor Aug. 28, 2012

Aug. 28, 2012

Hi, I'm planning on making a SeaBIOS release - version 1.7.1. The goal is to make a release for the upcoming QEMU 1.2.0 release. The QEMU team recently pulled in SeaBIOS revision 5a023065. That revision is just one prior to the head of the current SeaBIOS tree. I'm thinking of just retroactively marking the 5a023065 revision as version 1.7.1. Does anyone know of any bugs that should be fixed prior to marking a release? I know of a bugfix for coreboot payload booting (the be64_to_cpu fix), but that seems to be an infrequent code path. I'm also aware of several feature patches pending (alt-numpad patch, geode vga improvements, ipmi patches, ACPI LNKS patch, dynamic SSDT patches, PCI v3 support patch, and PMTIMER patches). Apologies for falling behind on these pending patches. However, I think all of these can wait until after tagging the next version. Unless something comes up, I'll likely tag the next release on Wednesday. Thanks, -Kevin

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Re: [SeaBIOS] [Qemu-devel] [Bug 1042084] [NEW] Windows 7 guest cannot boot after seabios updated
by Gerd Hoffmann Aug. 28, 2012

Aug. 28, 2012

On 08/28/12 10:07, Stefan Hajnoczi wrote: > On Mon, Aug 27, 2012 at 7:54 AM, Vic <llyzs(a)163.com> wrote: >> Public bug reported: >> >> Hi, >> >> I can no longer boot my Windows 7 guest after this commit (update >> seabios to latest master) >> >> http://git.qemu.org/?p=qemu.git;a=commitdiff;h=01afdadc92e71e29700e64f3a5f4… >> >> When I tried to boot Windows, it BSOD and said "The BIOS in this system >> is not fully ACPI compliant. Please contact your system vendor for an >> updated BIOS". Reverting this commit will fix the issue. > > Gerd, Kevin: Any ideas? Not yet. My win7 32bit guests boots fine. Installing 64bit version right now to see how that behaves, at least the windows setup booted just fine too. cheers, Gerd

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Re: [SeaBIOS] [Qemu-devel] [Bug 1042084] [NEW] Windows 7 guest cannot boot after seabios updated
by Stefan Hajnoczi Aug. 28, 2012

Aug. 28, 2012

On Mon, Aug 27, 2012 at 7:54 AM, Vic <llyzs(a)163.com> wrote: > Public bug reported: > > Hi, > > I can no longer boot my Windows 7 guest after this commit (update > seabios to latest master) > > http://git.qemu.org/?p=qemu.git;a=commitdiff;h=01afdadc92e71e29700e64f3a5f4… > > When I tried to boot Windows, it BSOD and said "The BIOS in this system > is not fully ACPI compliant. Please contact your system vendor for an > updated BIOS". Reverting this commit will fix the issue. Gerd, Kevin: Any ideas? > > ** Affects: qemu > Importance: Undecided > Status: New > > -- > You received this bug notification because you are a member of qemu- > devel-ml, which is subscribed to QEMU. > https://bugs.launchpad.net/bugs/1042084 > > Title: > Windows 7 guest cannot boot after seabios updated > > Status in QEMU: > New > > Bug description: > Hi, > > I can no longer boot my Windows 7 guest after this commit (update > seabios to latest master) > > http://git.qemu.org/?p=qemu.git;a=commitdiff;h=01afdadc92e71e29700e64f3a5f4… > > When I tried to boot Windows, it BSOD and said "The BIOS in this > system is not fully ACPI compliant. Please contact your system vendor > for an updated BIOS". Reverting this commit will fix the issue. > > To manage notifications about this bug go to: > https://bugs.launchpad.net/qemu/+bug/1042084/+subscriptions >

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[PATCH] Search PCIv3 device list in optionroms if present
by Daniel Verkamp Aug. 27, 2012

Aug. 27, 2012

PCI Firmware Specification v3.0 defined a new optional device list, allowing a single optionrom to handle several device IDs. Add support for this list when looking for an optionrom for a PCI device. Signed-off-by: Daniel Verkamp <daniel(a)drv.nu> --- src/optionroms.c | 33 ++++++++++++++++++++++++++++----- src/optionroms.h | 2 +- 2 files changed, 29 insertions(+), 6 deletions(-) diff --git a/src/optionroms.c b/src/optionroms.c index 00697b2..0023d90 100644 --- a/src/optionroms.c +++ b/src/optionroms.c @@ -292,19 +292,42 @@ map_pcirom(struct pci_device *pci) goto fail; } - if (pd->vendor == pci->vendor && pd->device == pci->device - && pd->type == PCIROM_CODETYPE_X86) - // A match - break; + void *nextrom = (void*)((u32)rom + pd->ilen * 512); + + if (pd->vendor == pci->vendor && pd->type == PCIROM_CODETYPE_X86) + { + if (pd->device == pci->device) + { + dprintf(6, "Matched device in PCI header\n"); + goto found; + } + + // PCI header device ID did not match, but vendor ID did + // search device list if available + if (pd->drevision >= 3 && pd->devicelist) { + u16 *devicelist = (u16*)((u32)pd + pd->devicelist); + dprintf(6, "Searching PCIv3 device ID list at %p\n", devicelist); + while (devicelist < (u16*)nextrom && *devicelist) { + dprintf(6, "Dev list entry: %04x\n", *devicelist); + if (*devicelist == pci->device) { + dprintf(6, "Matched device in PCIv3 device list\n"); + goto found; + } + devicelist++; + } + dprintf(6, "Didn't match device ID list\n"); + } + } dprintf(6, "Didn't match dev/ven (got %04x:%04x) or type (got %d)\n" , pd->vendor, pd->device, pd->type); if (pd->indicator & 0x80) { dprintf(6, "No more images left\n"); goto fail; } - rom = (void*)((u32)rom + pd->ilen * 512); + rom = nextrom; } +found: rom = copy_rom(rom); pci_config_writel(bdf, PCI_ROM_ADDRESS, orig); return rom; diff --git a/src/optionroms.h b/src/optionroms.h index 94ca4ae..487ea45 100644 --- a/src/optionroms.h +++ b/src/optionroms.h @@ -20,7 +20,7 @@ struct pci_data { u32 signature; u16 vendor; u16 device; - u16 vitaldata; + u16 devicelist; u16 dlen; u8 drevision; u8 class_lo; -- 1.7.8.6

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Re: [SeaBIOS] [PATCH] geodevga: make use of readl and writel for mmio access
by Kevin O'Connor Aug. 27, 2012

Aug. 27, 2012

On Mon, Aug 27, 2012 at 04:05:36PM +0200, Christian Gmeiner wrote: > Maybe I am too blind but I don't get it: > > out/../vgasrc/geodevga.c: In function ‘init_video_mode’: > out/../vgasrc/geodevga.c:443:11: error: variable or field ‘__val’ declared void > out/../vgasrc/geodevga.c:443:11: warning: dereferencing ‘void *’ > pointer [enabled by default] > out/../vgasrc/geodevga.c:443:11: warning: dereferencing ‘void *’ > pointer [enabled by default] > out/../vgasrc/geodevga.c:443:11: warning: dereferencing ‘void *’ > pointer [enabled by default] > out/../vgasrc/geodevga.c:443:11: warning: dereferencing ‘void *’ > pointer [enabled by default] > out/../vgasrc/geodevga.c:443:11: warning: taking address of expression > of type ‘void’ [enabled by default] > make: *** [out/vgaccode16.raw.s] Error 1 > > void *VG = (void *)pci_config_readl(GET_GLOBAL(VgaBDF), PCI_BASE_ADDRESS_3); > ... > u32 val = GET_FARVAR(0, *(VG + 0x50)); > > I only want to read a u32 value with offset to 0x50 from VG. You can't read a void*, so use: GET_FARVAR(0, *(u32*)(VG + 0x50)); -Kevin

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Re: [SeaBIOS] [PATCH] geodevga: make use of readl and writel for mmio access
by Kevin O'Connor Aug. 27, 2012

Aug. 27, 2012

On Tue, Jul 17, 2012 at 12:08:59PM +0200, Christian Gmeiner wrote: > This commit just simplifies some code. > > Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> > --- > vgasrc/geodevga.c | 48 +++++++++--------------------------------------- > 1 file changed, 9 insertions(+), 39 deletions(-) > > diff --git a/vgasrc/geodevga.c b/vgasrc/geodevga.c > index 5c6caf0..4e3d912 100644 > --- a/vgasrc/geodevga.c > +++ b/vgasrc/geodevga.c [...] > /* Set mmio registers > * there may be some timing issues here, the reads seem > * to slow things down enough work reliably > */ > > - reg = geode_memRead(vp+VP_MISC); > + reg = readl(vp+VP_MISC); The code is run in 16bit "big real" mode. This means all of memory is available, but one still needs to be careful about segment usage. SeaBIOS always calls the option roms with a %ss == %ds == 0, but I don't think it is wise to rely upon that. So, it's better to use GET_FARVAR(0, *(vp+VP_MISC)). -Kevin

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