July 2011 - SeaBIOS - mail.coreboot.org

[PATCH 0/5] pci: two-pass initialization
by Gerd Hoffmann Aug. 9, 2011

Aug. 9, 2011

Hi, Next (and hopefully final) version of the two-pass pci initialization patches. Addressed review comments, fixed some bugs, especially the io range setup for bridges. cheers, Gerd Gerd Hoffmann (5): pci: add two-pass pci initialization code pci: activate two-pass pci initialization code pci: remove old pci initilaization code pci: cleanup config.h pci: set BUILD_PCIMEM_START to 0xe0000000 Makefile | 2 +- src/config.h | 16 +-- src/pci.h | 8 + src/pci_region.c | 77 -------- src/pciinit.c | 509 ++++++++++++++++++++++++++++++++++-------------------- src/util.h | 29 --- 6 files changed, 335 insertions(+), 306 deletions(-) delete mode 100644 src/pci_region.c

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[PATCH V5 0/9] Add TPM support to SeaBIOS
by Stefan Berger Aug. 4, 2011

Aug. 4, 2011

The following set of patches add TPM and Trusted Computing support to SeaBIOS. In particular the patches add: - a TPM driver for the Qemu's TPM TIS emulation (not yet in Qemu git) - ACPI support for the TPM device (SSDT table) - ACPI support for measurement logging (TCPA table) - Support for initialzation of the TPM - Support for the TCG BIOS extensions (1ah handler [ah = 0xbb]) (used by trusted grub; http://trousers.sourceforge.net/grub.html) - Static Root of Trusted for Measurement (SRTM) support - Support for S3 resume (sends command to TPM upon resume) - TPM-specific menu for controlling aspects of the TPM - [An optional test suite for the TIS interface] All implementations necessarily follow specifications. When all patches are applied the following services are available - SSDT ACPI table for TPM support - initialization of the TPM upon VM start and S3 resume - Static root of trust for measurements (SRTM) that measures (some) data of SeaBIOS in TCPA ACPI table - 1ah interrupt handler offering APIs for measuring and sending commands to the TPM (trusted grub uses them) - User menu for controlling aspects of the state of the TPM v5: - adapted patches to checkout of 76b5e71 (June 21) - bugfixes (see individual patches) - added patch to support the transfer of Qemu-provided measurements via firmware interface v4: - if ! has_working_tpm() now returns error code everywhere - tis_test.c now also under LGPLv3 - in inthandler, pulled set_cf() out of switch and then only call it in the default case where we need to indicate that a function is not implemented v3: - some nits here and there - calling timer_setup now after S3 resume v2: - following Kevin's comment - refactoring code so that every patch compiles Regards, Stefan

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[PATCH 0/7] ahci update
by Gerd Hoffmann Aug. 4, 2011

Aug. 4, 2011

Hi, Finally the update for the ahci code, featuring: * A bunch of bugfixes, which makes the code work on real hardware (additionally to the qemu emulated ahci adapter). * Better timeout handling. * Support for unaligned access. * Support for boot ordering. cheers, Gerd The following changes since commit 77b8536e5c9908fbe99c88d01462a36a3deb05b1: pci: set BUILD_PCIMEM_START to 0xe0000000 (2011-07-12 21:14:53 -0400) are available in the git repository at: git://git.kraxel.org/seabios ahci Gerd Hoffmann (6): ahci/sata: Fix FIS setup. ahci: use interrupt status register ahci: add error recovery code ahci: don't expect ATA_CB_STAT_DRQ being clear ahci: rework init workflow & fix timeout handling ahci: bootprio support Scott Duplichan (1): ahci: handle unaligned buffers. src/ahci.c | 350 +++++++++++++++++++++++++++++++++++++++++++++--------------- src/ahci.h | 3 +- 2 files changed, 264 insertions(+), 89 deletions(-)

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[PATCH] seabios: increase smp_mtrr array size
by Marcelo Tosatti July 29, 2011

July 29, 2011

Windows Server 2008 checked build complains about lack of consistency between MTRR MSRs in SMP guests. Problem is the smp_mtrr array is not large enough to hold all MSRs (31 entries with current qemu/kvm implementations). Increase it to 32. Signed-off-by: Marcelo Tosatti <mtosatti(a)redhat.com> diff --git a/src/smp.c b/src/smp.c index 40f5451..2317d36 100644 --- a/src/smp.c +++ b/src/smp.c @@ -17,7 +17,7 @@ #define APIC_ENABLED 0x0100 -struct { u32 ecx, eax, edx; } smp_mtrr[16] VAR16VISIBLE; +struct { u32 ecx, eax, edx; } smp_mtrr[32] VAR16VISIBLE; u32 smp_mtrr_count VAR16VISIBLE; void

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[PATCH] Ctrl-Break support (INT 1B, etc)
by Nikolay Nikolov July 23, 2011

July 23, 2011

Hi, all, I made a patch for proper Ctrl-Break handling. This is useful for MS-DOS or compatible operating systems like FreeDOS. When Ctrl-Break is detected, it clears the keyboard buffer, sets the Ctrl-Break flag at [0040h:0071h], invokes int 1Bh and then adds 0000h to the keyboard buffer. If a non-enhanced keyboard is present, Ctrl-Scroll Lock works just like Ctrl-Break. This seems to be the "standard" BIOS behaviour, at least on the PCs I tested. The patch was tested with MS-DOS 6.22, running under qemu. I'm new to git (and this is my first SeaBIOS patch ever), so I'm not sure what's the preferred way to submit patches. I just did a "git diff" and attached the result. Sorry if that's not the best way :) Nikolay

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Re: [SeaBIOS] shadow RAM requirement
by Kevin O'Connor July 23, 2011

July 23, 2011

On Fri, Jul 22, 2011 at 03:06:02PM +0200, Łukasz Mielicki wrote: > Hi, > > I'm trying to run SeaBIOS in an environment where I have difficulties with > enabling a shadow RAM. > Is there a chance to w/a requirement for writable 0xF000 seg in SeaBIOS? > Could some of group members briefly estimate a scope of necessary changes? SeaBIOS stores global variables in the f-segment, and so it requires that the f-segment be writable. Requiring that the f-segment be writable was a significant code simplification - I don't see a way to remove that requirement without re-introducing the associated complexity. -Kevin

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shadow RAM requirement
by Łukasz Mielicki July 22, 2011

July 22, 2011

Hi, I'm trying to run SeaBIOS in an environment where I have difficulties with enabling a shadow RAM. Is there a chance to w/a requirement for writable 0xF000 seg in SeaBIOS? Could some of group members briefly estimate a scope of necessary changes? Thanks, Łukasz

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Xen HVM Support
by Ian Campbell July 22, 2011

July 22, 2011

The following enables support for running SeaBIOS as the virtual BIOS in a Xen HVM (fully-virtualised) guest. In this series SeaBIOS is loaded by hvmloader (the Xen early firmware) rather than directly as was previously tried. This approach turned out to be far less intrusive on the SeaBIOS side and leaves knowledge of the virtual hardware setup encapsulated within hvmloader which is updated in lock step with the hypervisor and associated tools. BIOS tables are built by hvmloader and passed to SeaBIOS via a simple in memory data structure. The tables are identified by scanning for their signatures which is hopefully extensible enough but the core structure can also be extended as necessary. The associated hvmloader series was only posted on xen-devel can be found at: http://marc.info/?l=xen-devel&m=130692187111154 the most interesting patch is probably: http://marc.info/?l=xen-devel&m=130692182011054 Ian.

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[PATCH] xen: actually setup hypercalls.
by Ian Campbell July 21, 2011

July 21, 2011

This was somehow dropped during the iterations of the original Xen patches. It's actually harmless at the moment since there are no users of hypercalls but patches are being written to support Xen PV block devices which need this. It's not clear exactly how early this needs to be but I think it needs to be at least before init_hw() (since that would detect disk devices). I put it first in maininit() since the only dependency is malloc(). Signed-off-by: Ian Campbell <ian.campbell(a)citrix.com> --- src/post.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/src/post.c b/src/post.c index d98941c..b2f6d51 100644 --- a/src/post.c +++ b/src/post.c @@ -210,6 +210,9 @@ startBoot(void) static void maininit(void) { + // Setup Xen hypercalls + xen_init_hypercalls(); + // Setup ivt/bda/ebda init_ivt(); init_bda(); -- 1.7.2.5

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Re: [SeaBIOS] [PATCH 0/7] ahci update
by Kevin O'Connor July 18, 2011

July 18, 2011

On Mon, Jul 18, 2011 at 12:26:41PM -0600, Marc Jones wrote: > On Sun, Jul 17, 2011 at 8:16 AM, Kevin O'Connor <kevin(a)koconnor.net> wrote: > > I've confirmed that with this patch series applied I can boot my > > Asrock e350m1 board in AHCI mode. > You tested that by changing SATA_MODE in cfg.h? Yes - I used the patch below to enable AHCI mode in coreboot. >If it is working and > commited, we should make ahci the default in coreboot. I have not yet committed the AHCI patch series. However, SeaBIOS can now handle the sb800 in AHCI mode with its regular ATA support. (A previous committed patch enables the the ATA driver to recognize that the AMD ahci controller can be driven as an ATA device when AHCI is disabled in SeaBIOS.) -Kevin diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 0a09e11..36136b4 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -83,7 +83,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER; sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary. //TODO: set to secondary not take effect. - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = 0; //IDE controlor exposed and combined mode enabled + sb_config->SATAMODE.SataMode.SataIdeCombinedMode = 1; //IDE controlor exposed and combined mode enabled sb_config->SATAMODE.SataMode.SATARefClkSel = SATA_CLOCK_SOURCE; /* Azalia HDA */ diff --git a/src/southbridge/amd/cimx/sb800/cfg.h b/src/southbridge/amd/cimx/sb800/cfg.h index 05db9ab..581fc66 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.h +++ b/src/southbridge/amd/cimx/sb800/cfg.h @@ -109,7 +109,7 @@ * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #ifndef SATA_MODE - #define SATA_MODE NATIVE_IDE_MODE + #define SATA_MODE AHCI_MODE #endif /**

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