July 2012 - openfirmware - mail.coreboot.org

[commit] r3085 - cpu/arm/olpc
by repository service July 27, 2012

July 27, 2012

Author: wmb Date: Fri Jul 27 04:54:42 2012 New Revision: 3085 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3085 Log: OLPC EDI driver - handle differences between KB3731 and the new KB9010 Modified: cpu/arm/olpc/edi.fth Modified: cpu/arm/olpc/edi.fth ============================================================================== --- cpu/arm/olpc/edi.fth Fri Jul 27 04:49:02 2012 (r3084) +++ cpu/arm/olpc/edi.fth Fri Jul 27 04:54:42 2012 (r3085) @@ -13,6 +13,41 @@ \ spi-out ( byte -- ) - Send byte \ spi-in ( -- byte ) - Receive byte +0 value edi-chip-id +: kb9010? ( -- flag ) edi-chip-id 4 = ; + +: efcfg ( -- reg# ) kb9010? if h# fea0 else h# fead then ; +: efcmd ( -- reg# ) kb9010? if h# fea7 else h# feac then ; +: efdat ( -- reg# ) kb9010? if h# feaa else h# feab then ; +: rst8051 ( -- reg# ) kb9010? if h# f010 else h# ff14 then ; + +\ Issues with .py code +\ A14:A8 should be A15:A8 several places +\ inconsistent use of handle vs gd.handle in edi_erase_chip + +\ KB9010 stuff... +d# 59 d# 1024 * constant /kb9010-flash +h# fe80 constant wdtcfg +h# fe81 constant wdtpf +h# fe82 constant wdt +h# fea2 constant shccfg +\ h# fea5 constant xbicfg \ Unused +h# fea6 constant xbics +\ h# feae constant efdatr \ Unused +\ h# feaf constant emfburw +h# feb2 constant xbiwp +\ h# feb6 constant xbipump +\ h# feb7 constant xbifm +\ h# feb8 constant sbivr +h# feb9 constant xbis +h# ff0d constant clkcfg +h# ff0f constant pllcfg +h# ff1d constant ecsts +h# ff1f constant pllcfg2 +h# ff14 constant pxcfg + +\ end KB9010 stuff... + d# 128 constant /flash-page defer edi-progress ' drop to edi-progress ( n -- ) @@ -73,19 +108,25 @@ ; [then] : reset-8051 ( -- ) \ Reset 8-5 - h# f010 edi-b@ 1 or h# f010 edi-b! + rst8051 edi-b@ 1 or rst8051 edi-b! ; : unreset-8051 ( -- ) \ Reset 8-5 - h# f010 edi-b@ 1 invert and h# f010 edi-b! + rst8051 edi-b@ 1 invert and rst8051 edi-b! d# 2000 ms ; \ 0 in bit 0 selects masked ROM as code source for 8051, 1 selects FLASH \ The 8051 should be in reset mode when changing that bit. + : select-flash ( -- ) \ Setup for access to FLASH inside the EC + kb9010? if exit then h# f011 edi-b@ 1 or h# f011 edi-b! ; +: edi-read-id ( -- id ) + spi-cs-on h# 3e spi-out 0 spi-out spi-in spi-cs-off +; + : probe-rdid ( -- found? ) \ Verify that the EC is the one we think it is select-flash h# f01c ['] edi-w@ catch if ( x ) @@ -95,12 +136,15 @@ 1 invert and h# 3730 = ; +: finished? ( b -- flag ) + kb9010? if 2 and 0= else h# 80 = then +; : wait-flash-busy ( -- ) \ Wait for an erase/programming operation to complete get-msecs h# 1000 + ( limit ) begin ( limit ) - h# fea0 edi-b@ ( limit b ) - h# 80 and if ( limit ) - drop exit + efcfg edi-b@ ( limit b ) + finished? if ( limit ) + drop exit ( -- ) then ( limit ) dup get-msecs - 0<= ( limit timeout? ) until ( limit ) @@ -108,11 +152,12 @@ true abort" EDI FLASH busy timeout" ; -: flash-cmd ( b -- ) h# fea7 edi-b! ; +: flash-cmd ( b -- ) efcmd edi-b! ; : set-offset ( offset -- ) - wbsplit ( offset-low offset-hi ) - h# fea9 edi-b! h# fea8 edi-b! ( ) + lbsplit drop ( offset-low mid hi ) + kb9010? if h# feaa edi-b! else drop then ( offset-low mid ) + h# fea9 edi-b! h# fea8 edi-b! ( ) ; : erase-page ( offset -- ) @@ -121,14 +166,19 @@ h# 20 flash-cmd ( ) ; -: erase-chip ( -- ) wait-flash-busy h# 60 flash-cmd wait-flash-busy ; +: erase-chip ( -- ) + 0 set-offset \ New code does this (and does not wait-flash-busy) + wait-flash-busy h# 60 flash-cmd wait-flash-busy +; -: send-byte ( b offset -- ) set-offset h# feaa edi-b! 2 flash-cmd ; +: send-byte ( b offset -- ) set-offset efdat edi-b! 2 flash-cmd ; : edi-program-page ( adr offset -- ) \ Clear HVPL wait-flash-busy h# 80 flash-cmd ( adr offset ) + wait-flash-busy ( adr offset ) \ Necessary? + \ Fill the page buffer swap /flash-page bounds do ( offset ) i c@ over send-byte ( offset ) @@ -138,7 +188,7 @@ \ Commit the buffer to the FLASH memory wait-flash-busy ( ) \ Redundant wait? - h# 70 flash-cmd ( ) + h# 70 flash-cmd ( ) \ Program page command wait-flash-busy ( ) ; h# 7e80 constant ec-flags-offset @@ -162,11 +212,12 @@ edi-next-b@ i c! ( ) loop ( ) ; + : trim@ ( offset -- b ) set-offset h# 90 flash-cmd wait-flash-busy - h# feab edi-b@ + efdat edi-b@ \ reg: efdat ; : trim-tune ( -- ) \ firmware-id 0= if @@ -226,13 +277,76 @@ then \ then ; +: set-chip-id ( -- ) + ['] edi-read-id catch if ( ) + edi-read-id ( id ) + then ( id ) + to edi-chip-id +; +: kb9010-init ( -- ) + h# 00 xbics edi-b! + h# 00 xbiwp edi-b! \ Clear XBI write protection + h# ff wdt edi-b! \ Disable WDT + h# 00 wdtcfg edi-b! + h# 00 wdtpf edi-b! + h# 00 shccfg edi-b! \ Disable SHC + h# 0c clkcfg edi-b! \ Set the 8051 to 32Mhz + h# 08 efcfg edi-b! \ Enable the embedded flash cmd mode +; +base @ hex +create special-row 1f0 w, 1f1 w, 1f2 w, 1f4 w, 1f5 w, 1f6 w, 1f3 w, +create dest-regs feb9 w, feb6 w, feb6 w, feb7 w, feb8 w, feb8 w, feb7 w, +create source-bits 1f c, 0f c, 0f c, 0f c, 07 c, 1f c, 0f c, +create dest-bits 1f c, f0 c, 0f c, 0f c, e0 c, 1f c, f0 c, +create shift-cnt 0 c, 4 c, 0 c, 0 c, 5 c, 0 c, 4 c, +base ! +: kb9010-trimtune ( -- ) + h# 1ff trim@ 0<> if + 7 0 do + special-row i wa+ w@ edi-b@ ( data ) + source-bits i ca+ c@ or ( field ) + shift-cnt i ca+ c@ lshift ( field' ) + dest-regs i wa+ w@ edi-b@ ( field dest ) + dest-bits i ca+ c@ invert and or ( dest' ) + dest-regs i wa+ w@ edi-b! ( ) + loop + wait-flash-busy + then + h# 80 trim@ h# 5a = if + ecsts edi-b@ ( old-ecsts ) + dup 4 or ecsts edi-b! ( old-ecsts ) \ chipid is now pllcfg2 + + xbis edi-b@ h# 3f and ( old-ecsts xbis-bits ) + h# 81 edi-b@ 3 and 6 lshift or ( old-ecsts xbis-value ) + xbis edi-b! ( old-ecsts ) + + h# 82 edi-b@ h# f and 4 lshift ( old-ecsts pll-high ) + h# 83 edi-b@ h# f0 and 4 rshift or ( old-ecsts pll-value ) + pllcfg edi-b! ( old-ecsts ) + + pllcfg2 edi-b@ h# 3f and ( old-ecsts pll2-bits ) + h# 82 edi-b@ h# 30 and 2 lshift or ( old-ecsts pll2-value ) + pllcfg2 edi-b! ( old-ecsts ) + + ecsts edi-b! ( ) + then +; : edi-open ( -- ) \ slow-edi-clock \ Target speed between 1 and 2 MHz spi-start + + set-chip-id + \ The first operation often fails so retry it ['] select-flash catch if select-flash then reset-8051 - trim-tune + + kb9010? if + kb9010-init + kb9010-trimtune + else + trim-tune + then \ fast-edi-clock \ Target speed up to 16 MHz \ reset ;

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[commit] r3084 - in cpu/arm/olpc: . 1.75 3.0 cl4
by repository service July 27, 2012

July 27, 2012

Author: wmb Date: Fri Jul 27 04:49:02 2012 New Revision: 3084 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3084 Log: OLPC CL4 - handle different UART assignments between CL4 and 1.75. Modified: cpu/arm/olpc/1.75/config.fth cpu/arm/olpc/1.75/fw.bth cpu/arm/olpc/1.75/gpiopins.fth cpu/arm/olpc/3.0/config.fth cpu/arm/olpc/3.0/fw.bth cpu/arm/olpc/bsl.fth cpu/arm/olpc/cl4/fw.bth cpu/arm/olpc/cl4/gpiopins.fth Modified: cpu/arm/olpc/1.75/config.fth ============================================================================== --- cpu/arm/olpc/1.75/config.fth Sun Jul 22 16:48:28 2012 (r3083) +++ cpu/arm/olpc/1.75/config.fth Fri Jul 27 04:49:02 2012 (r3084) @@ -31,6 +31,9 @@ char 4 constant expected-ec-version h# 8000 value /ec-flash -h# 10000 constant l2-#sets +\ These constants are correct for XO-1.75 and XO-CL4; they might +\ need to be changed for different hardware. See setup-gpios-hack + +fload ${BP}/cpu/arm/mmp2/soc-config.fth fload ${BP}/cpu/arm/olpc/1.75/gpiopins.fth Modified: cpu/arm/olpc/1.75/fw.bth ============================================================================== --- cpu/arm/olpc/1.75/fw.bth Sun Jul 22 16:48:28 2012 (r3083) +++ cpu/arm/olpc/1.75/fw.bth Fri Jul 27 04:49:02 2012 (r3084) @@ -7,6 +7,9 @@ " fw.tag" r/w create-file drop tag-file ! +h# 17000 +io constant bsl-uart-base \ UART2 +h# 30 constant bsl-uart-clock-offset \ APBC_UART2_CLK_RST + fload ${BP}/cpu/arm/olpc/build-fw.fth \ The internal SD card shares the host controller circuitry with @@ -20,6 +23,26 @@ fload ${BP}/cpu/arm/olpc/emmc.fth +\ Setup UART configuration +h# d4018000 to uart-base \ UART3 +devalias com1 /uart@d4018000 + +dev /uart@d4030000 \ UART1 + 0 " linux,unit#" integer-property +device-end + +dev /uart@d4017000 \ UART2 + " disabled" " status" string-property +device-end + +dev /uart@d4018000 \ UART3 + 1 " linux,unit#" integer-property +device-end + +dev /uart@d4016000 \ UART4 + " disabled" " status" string-property +device-end + \ Device node for internal microSD dev /sd new-device Modified: cpu/arm/olpc/1.75/gpiopins.fth ============================================================================== --- cpu/arm/olpc/1.75/gpiopins.fth Sun Jul 22 16:48:28 2012 (r3083) +++ cpu/arm/olpc/1.75/gpiopins.fth Fri Jul 27 04:49:02 2012 (r3084) @@ -60,3 +60,7 @@ d# 15 constant rotate-gpio# d# 17 constant check-gpio# + +d# 14 constant touch-hd-gpio# +d# 139 constant touch-tck-gpio# +d# 98 constant touch-rst-gpio# Modified: cpu/arm/olpc/3.0/config.fth ============================================================================== --- cpu/arm/olpc/3.0/config.fth Sun Jul 22 16:48:28 2012 (r3083) +++ cpu/arm/olpc/3.0/config.fth Fri Jul 27 04:49:02 2012 (r3084) @@ -30,6 +30,8 @@ char 4 constant expected-ec-version h# 8000 value /ec-flash +h# 18000 constant console-uart-base + fload ${BP}/cpu/arm/mmp2/soc-config.fth fload ${BP}/cpu/arm/olpc/3.0/gpiopins.fth Modified: cpu/arm/olpc/3.0/fw.bth ============================================================================== --- cpu/arm/olpc/3.0/fw.bth Sun Jul 22 16:48:28 2012 (r3083) +++ cpu/arm/olpc/3.0/fw.bth Fri Jul 27 04:49:02 2012 (r3084) @@ -9,6 +9,26 @@ fload ${BP}/cpu/arm/olpc/build-fw.fth +\ Setup UART configuration +h# d4018000 to uart-base \ UART3 +devalias com1 /uart@d4018000 + +dev /uart@d4030000 \ UART1 + 0 " linux,unit#" integer-property +device-end + +dev /uart@d4017000 \ UART2 + " disabled" " status" string-property +device-end + +dev /uart@d4018000 \ UART3 + 1 " linux,unit#" integer-property +device-end + +dev /uart@d4016000 \ UART4 + " disabled" " status" string-property +device-end + fload ${BP}/cpu/arm/olpc/emmc.fth devalias int /sd/disk@3 Modified: cpu/arm/olpc/bsl.fth ============================================================================== --- cpu/arm/olpc/bsl.fth Sun Jul 22 16:48:28 2012 (r3083) +++ cpu/arm/olpc/bsl.fth Fri Jul 27 04:49:02 2012 (r3084) @@ -4,20 +4,13 @@ \ devalias bsl /uart@NNNN:9600,8,e,1//bsl-protocol -\ These constants are correct for XO-1.75 and XO-CL4; they might -\ need to be changed for different hardware. See setup-gpios-hack - -h# 17000 +io constant bsl-uart-base \ UART2 - -d# 98 constant bsl-test-gpio# \ GPIO98 is alternate function 0 (the default) -d# 152 constant bsl-rst-gpio# \ SM_BELn, with GPIO152 as alternate function 1 - \ This is platform-dependent : setup-gpios ( -- ) - 3 d# 55 af! 3 d# 56 af! \ Setup pins for UART2 - 0 bsl-test-gpio# af! \ Set to GPIO function - 1 bsl-rst-gpio# af! \ Set to GPIO function (AF0 is SM_BELn for this pin) +\ The pin setup should be done in CForth, but it's complicated by the fact that the touch-enabled CL2 uses GPIO 56 differently from the ordinary one +[ifdef] olpc-cl2 3 d# 55 af! 3 d# 56 af! [then] \ Setup pins for UART2 + 0 touch-tck-gpio# af! \ Set to GPIO function + 1 touch-rst-gpio# af! \ Set to GPIO function (AF0 is SM_BELn for this pin) ; 0 [if] @@ -33,8 +26,8 @@ d# 115 to test-gpio# \ Normally UART3 TXD, but repurposed as a GPIO d# 116 to rst-gpio# \ Normally UART3 RXD, but repurposed as a GPIO - 0 bsl-test-gpio# af! \ Set to GPIO function instead of UART3 - 0 bsl-rst-gpio# af! \ Set to GPIO function instead of UART3 + 0 touch-tck-gpio# af! \ Set to GPIO function instead of UART3 + 0 touch-rst-gpio# af! \ Set to GPIO function instead of UART3 ; [then] @@ -43,8 +36,8 @@ : bsl-baud ( baud-rate -- ) \ 9600,8,e,1 uart-base >r ( baud-rate r: uart-base ) bsl-uart-base to uart-base - h# 13 h# 30 apbc! \ enable the uart2 clocks - h# 40 1 uart! \ uart unit enable + h# 13 bsl-uart-clock-offset apbc! \ enable the uart2 clocks + h# 40 1 uart! \ uart unit enable baud h# 1b 3 uart! ( r: uart-base ) r> to uart-base ( ) ; @@ -63,35 +56,35 @@ : bsl-open ( -- ) setup-gpios - bsl-rst-gpio# gpio-clr - bsl-test-gpio# gpio-clr - bsl-rst-gpio# gpio-dir-out - bsl-test-gpio# gpio-dir-out + touch-rst-gpio# gpio-clr + touch-tck-gpio# gpio-clr + touch-rst-gpio# gpio-dir-out + touch-tck-gpio# gpio-dir-out d# 9600 bsl-baud ; : bsl-close ( -- ) - bsl-rst-gpio# gpio-dir-in - bsl-test-gpio# gpio-dir-in + touch-rst-gpio# gpio-dir-in + touch-tck-gpio# gpio-dir-in ; : msp430-off ( -- ) - bsl-rst-gpio# gpio-clr - bsl-test-gpio# gpio-clr + touch-rst-gpio# gpio-clr + touch-tck-gpio# gpio-clr ; : dly ( -- ) d# 10 ms ; : start-bsl ( -- ) bsl-open d# 250 ms - bsl-test-gpio# gpio-set + touch-tck-gpio# gpio-set dly - bsl-test-gpio# gpio-clr + touch-tck-gpio# gpio-clr dly - bsl-test-gpio# gpio-set + touch-tck-gpio# gpio-set dly - bsl-rst-gpio# gpio-set + touch-rst-gpio# gpio-set dly - bsl-test-gpio# gpio-clr + touch-tck-gpio# gpio-clr ; : flush-bsl Modified: cpu/arm/olpc/cl4/fw.bth ============================================================================== --- cpu/arm/olpc/cl4/fw.bth Sun Jul 22 16:48:28 2012 (r3083) +++ cpu/arm/olpc/cl4/fw.bth Fri Jul 27 04:49:02 2012 (r3084) @@ -7,8 +7,33 @@ " fw.tag" r/w create-file drop tag-file ! +h# 16000 +io constant bsl-uart-base \ UART4 +h# 88 constant bsl-uart-clock-offset \ APBC_UART4_CLK_RST + fload ${BP}/cpu/arm/olpc/build-fw.fth +true to stand-init-debug? + +\ Setup UART configuration +h# d4017000 to uart-base \ UART2 +devalias com1 /uart@d4017000 + +dev /uart@d4030000 \ UART1 + 0 " linux,unit#" integer-property +device-end + +dev /uart@d4017000 \ UART2 + 1 " linux,unit#" integer-property +device-end + +dev /uart@d4018000 \ UART3 + " disabled" " status" string-property +device-end + +dev /uart@d4016000 \ UART4 + " disabled" " status" string-property \ Used for touchscreen BSL +device-end + dev /sd new-device 4 encode-int " reg" property Modified: cpu/arm/olpc/cl4/gpiopins.fth ============================================================================== --- cpu/arm/olpc/cl4/gpiopins.fth Sun Jul 22 16:48:28 2012 (r3083) +++ cpu/arm/olpc/cl4/gpiopins.fth Fri Jul 27 04:49:02 2012 (r3084) @@ -11,8 +11,8 @@ d# 155 constant ec-spi-cmd-gpio# d# 113 constant ec-spi-ack-gpio# -d# 167 constant dcon-scl-gpio# -d# 168 constant dcon-sda-gpio# +d# 168 constant dcon-scl-gpio# +d# 167 constant dcon-sda-gpio# d# 126 constant dcon-irq-gpio# d# 142 constant dcon-load-gpio#

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[commit] r3083 - cpu/arm/mmp3
by repository service July 22, 2012

July 22, 2012

Author: wmb Date: Sun Jul 22 16:48:28 2012 New Revision: 3083 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3083 Log: OLPC ARM - the last commit makes cpu/arm/mmp3/initmmu.fth unnecessary, so delete it. Deleted: cpu/arm/mmp3/initmmu.fth

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[commit] r3082 - in cpu/arm: mmp2 mmp3 mmp3/thunderstone olpc olpc/3.0 olpc/cl4
by repository service July 22, 2012

July 22, 2012

Author: wmb Date: Sun Jul 22 16:47:25 2012 New Revision: 3082 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3082 Log: OLPC ARM - coalesced initmmu.fth into one file, with parameterized differences between mmp2 and mmp3. Added: cpu/arm/mmp2/initmmu.fth cpu/arm/mmp2/soc-config.fth cpu/arm/mmp3/soc-config.fth Modified: cpu/arm/mmp3/initmmu.fth cpu/arm/mmp3/resetvec.fth cpu/arm/mmp3/thunderstone/config.fth cpu/arm/olpc/3.0/config.fth cpu/arm/olpc/cl4/config.fth cpu/arm/olpc/resetvec.fth Added: cpu/arm/mmp2/initmmu.fth ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ cpu/arm/mmp2/initmmu.fth Sun Jul 22 16:47:25 2012 (r3082) @@ -0,0 +1,389 @@ +\ See license at end of file +purpose: Setup the initial virtual address map + +[ifdef] notdef +\ Synchronizes the instruction and data caches over the indicated +\ address range, thus allowing the execution of instructions that +\ have recently been written to memory. +label sync-cache-range \ r0: adr, r1: len + begin + mcr p15, 0, r0, cr7, cr10, 1 \ clean D$ line + mcr p15, 0, r0, cr7, cr5, 1 \ invalidate I$ line + add r0, r0, #32 \ Advance to next line + subs r1, r1, #32 + 0<= until + mov pc, lr +end-code + +\ Forces data in the cache within the indicated address range +\ into memory. +label clean-dcache-range \ r0: adr, r1: len + begin + mcr p15, 0, r0, cr7, cr10, 1 \ clean D$ line + add r0, r0, #32 \ Advance to next line + subs r1, r1, #32 + 0<= until + mov pc, lr +end-code +[then] + +\ Turn on the caches +label caches-on + + \ Invalidate the entire L1 data cache by looping over all sets and ways + mov r0,#0 \ Start with set/way 0 of L1 cache + begin + \ In this unrolled loop, the number of iterations (8) and the increment + \ value (0x20000000) depend on fact that this cache has 8 ways. + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way - will wrap to 0 + + inc r0,#32 \ Next set + ands r1,r0,#0xfe0 \ Mask set bits - depends on #sets=128 + 0= until + + \ Invalidate the entire L2 cache by looping over all sets and ways + mov r0,#2 \ Start with set/way 0 of L2 cache + begin + \ In this unrolled loop, the number of iterations (8) and the increment + \ value (0x20000000) depend on fact that this cache has 8 ways. + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way - will wrap to 0 + + inc r0,#32 \ Next set + set r2,`l2-#sets h# 20 - #` \ Mask for set field for L2 cache + ands r1,r0,r2 \ Mask set bits + 0= until + + mcr p15, 0, r0, cr7, cr5, 0 \ Invalidate entire I$ + + mcr p15, 0, r0, cr7, cr5, 6 \ Flush branch target cache + + mrc p15,0,r0,cr1,cr0,0 \ Read control register + orr r0,r0,#0x1000 \ ICache on + orr r0,r0,#0x0800 \ Branch prediction on + orr r0,r0,#0x0004 \ DCache on + mcr p15,0,r0,cr1,cr0,0 \ Write control register with new bits + + mrc p15,0,r0,cr1,cr0,1 \ Read aux control register + orr r0,r0,#0x0002 \ L2 Cache on + mcr p15,0,r0,cr1,cr0,1 \ Write control register with new bits + + mov pc, lr +end-code + +\ Synchronizes the instruction and data caches, thus allowing the +\ execution of instructions that have recently been written to memory. +\ This version, which operates on the entire cache, is more efficient +\ than an address-range version when the range is larger than the +\ L1 cache size. +label sync-caches \ No args or returns, kills r0 and r1 + + \ Clean (push the data out to a higher level) the entire L1 data cache + \ by looping over all sets and ways + mov r0,#0 \ Start with set/way 0 of L1 cache + begin + \ In this unrolled loop, the number of iterations (8) and the increment + \ value (0x20000000) depend on fact that this cache has 8 ways. + mcr p15, 0, r0, cr7, cr10, 2 \ clean D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr10, 2 \ clean D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr10, 2 \ clean D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr10, 2 \ clean D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr10, 2 \ clean D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr10, 2 \ clean D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr10, 2 \ clean D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr10, 2 \ clean D$ line by set/index + inc r0,#0x20000000 \ Next way - will wrap to 0 + + inc r0,#32 \ Next set + ands r1,r0,#0xfe0 \ Mask set bits - depends on #sets=128 + 0= until + + mcr p15, 0, r0, cr7, cr5, 0 \ Invalidate entire I$ + mov pc, lr +end-code + +\ Insert zeros into the code stream until a cache line boundary is reached +\ This must be enclosed with "ahead .. then" to branch around the zeros. +: cache-align ( -- ) + begin + here [ also assembler ] asm-base [ previous ] - h# 1f and + while + 0 l, + repeat +; + +\ Turn on the MMU +label enable-mmu ( -- ) + mvn r2, #0 \ Set domains for Manager access - all domains su + mcr p15,0,r2,3,0,0 \ Update register 3 in CP15 - domain access control + + \ Enable the MMU + mrc p15, 0, r2, 1, 0, 0 \ Read current settings in control reg + mov r2, r2, LSL #18 \ Upper 18-bits must be written as zero, + mov r2, r2, LSR #18 \ ... clear them now. + + orr r2, r2, 0x200 \ Set the ROM Protection bit + bic r2, r2, 0x100 \ Clear the System Protection bit + orr r2, r2, 0x001 \ Set the MMU bit + + \ Align following code to a cache line boundary + ahead + cache-align + then + + mcr p15, 0, r2, cr1, cr0, 0 \ Go Virtual + mrc p15, 0, r2, cr2, cr0, 0 \ Ensure that the write completes + mov r2, r2 \ before continuing + sub pc, pc, #4 + + mov pc, lr +end-code + +\ Map sections within the given address range, using +\ the given protection/cacheability mode. pt-adr is the page table base address. +label map-sections ( r0: pt-adr, r1: padr, r2: len, r3: mode r4: vadr -- ) + add r1, r1, r3 \ PA+mode + begin + str r1, [r0, r4, lsr #18] + + inc r1, #0x100000 + inc r4, #0x100000 + decs r2, #0x100000 + 0<= until + + mov pc, lr +end-code + +\ Map sections virtual=physical within the given address range, using +\ the given protection/cacheability mode. pt-adr is the page table base address. +label map-sections-v=p ( r0: pt-adr, r1: adr, r2: len, r3: mode -- ) + begin + add r4, r1, r3 \ PA+mode + str r4, [r0, r1, lsr #18] + + inc r1, #0x100000 + decs r2, #0x100000 + 0<= until + + mov pc, lr +end-code + +\ Map sections within the given address range, using +\ the given protection/cacheability mode. pt-adr is the page table base address. +label allocate-and-map-sections ( r0: pt-adr, r1: padr-top, r2: len, r3: mode r4: vadr -- r1: padr-bot ) + inc r4, r2 \ vadr-top + add r1, r1, r3 \ PA+mode + begin + dec r1, #0x100000 + dec r4, #0x100000 + + str r1, [r0, r4, lsr #18] + + decs r2, #0x100000 + 0<= until + + mov r1,r1,lsr #20 \ Clear out mode bits in padr + mov r1,r1,lsl #20 + + mov pc, lr +end-code + +\ This assumes that there are no holes and that unused MMAP registers have CS_VALID=0 +label dramsize ( -- r0: size-in-bytes ) + mov r0,0 + mov r1,0xd0000000 \ Memory controller base address + +\ ldr r2,[r1,#0x00] \ MMAP0 register +\ and r2,r2,#0xff \ Revision +\ cmps r2,#0xNN \ MMP3? +\ >= if + +[ifdef] mmp3 + \ MMP3 memory controller - 2 banks, MMAP registers at 0x10 and 0x14 + ldr r2,[r1,#0x10] \ MMAP0 register + ands r3,r2,#1 \ Test CS_VALID + movne r3,#0x10000 \ Scale factor for memory size + movne r2,r2,lsl #11 \ Clear high bits above AREA_LENGTH field + movne r2,r2,lsr #27 \ Move AREA_LENGTH to LSB + addne r0,r0,r3,lsl r2 \ Compute bank size and add to accumulator + + ldr r2,[r1,#0x14] \ MMAP1 register + ands r3,r2,#1 \ Test CS_VALID + movne r3,#0x10000 \ Scale factor for memory size + movne r2,r2,lsl #11 \ Clear high bits above AREA_LENGTH field + movne r2,r2,lsr #27 \ Move AREA_LENGTH to LSB + addne r0,r0,r3,lsl r2 \ Compute bank size and add to accumulator + + add r1,r1,#0x10000 \ Memory controller base address d0010000 + + ldr r2,[r1,#0x10] \ MMAP0 register + ands r3,r2,#1 \ Test CS_VALID + movne r3,#0x10000 \ Scale factor for memory size + movne r2,r2,lsl #11 \ Clear high bits above AREA_LENGTH field + movne r2,r2,lsr #27 \ Move AREA_LENGTH to LSB + addne r0,r0,r3,lsl r2 \ Compute bank size and add to accumulator + + ldr r2,[r1,#0x14] \ MMAP1 register + ands r3,r2,#1 \ Test CS_VALID + movne r3,#0x10000 \ Scale factor for memory size + movne r2,r2,lsl #11 \ Clear high bits above AREA_LENGTH field + movne r2,r2,lsr #27 \ Move AREA_LENGTH to LSB + addne r0,r0,r3,lsl r2 \ Compute bank size and add to accumulator +[else] + \ MMP2 memory controller - 1 bank, MMAP registers at 0x100 and 0x110 + ldr r2,[r1,#0x100] \ MMAP0 register + ands r3,r2,#1 \ Test CS_VALID + movne r3,#0x10000 \ Scale factor for memory size + movne r2,r2,lsl #12 \ Clear high bits above AREA_LENGTH field + movne r2,r2,lsr #28 \ Move AREA_LENGTH to LSB + addne r0,r0,r3,lsl r2 \ Compute bank size and add to accumulator + + ldr r2,[r1,#0x110] \ MMAP1 register + ands r3,r2,#1 \ Test CS_VALID + movne r3,#0x10000 \ Scale factor for memory size + movne r2,r2,lsl #12 \ Clear high bits above AREA_LENGTH field + movne r2,r2,lsr #28 \ Move AREA_LENGTH to LSB + addne r0,r0,r3,lsl r2 \ Compute bank size and add to accumulator +[then] + + mov pc,lr +end-code + +\ Initial the section table, setting up mappings for the platform-specific +\ address ranges that the firmware uses. +\ Destroys: r0-r4 +label init-map ( -- ) + mov r10,lr + + bl `dramsize` \ r0: total-memory-size + mov r1,r0 \ r1: allocation pointer starts at top of DRAM + + \ Locate the page table at the top of the firmware memory, just below the frame buffer + dec r0,`/fb-mem #` \ Size of frame buffer + dec r0,`/page-table #` \ r0: page-table-pa + + mcr p15,0,r0,cr2,cr0,0 \ Set table base address + + \ Clear the entire section table for starters + mov r2, #0x1000 \ Section# + mov r3, #0 \ Invalid section entry + begin + subs r2, r2, #1 \ Decrement section number + str r3, [r0, r2, lsl #2] \ Invalidate section entry + 0= until + \ r1: top of DRAM + set r2,`/fb-mem #` \ Size of frame buffer + set r3,#0xc06 \ Write bufferable + set r4,`fb-mem-va #` \ Virtual address + bl `allocate-and-map-sections \ r1: bottom PA of frame buffer + + set r2,`/fw-mem #` \ Size of firmware region + set r3,#0xc0e \ Write bufferable + set r4,`fw-mem-va #` \ Virtual address + bl `allocate-and-map-sections` \ r1: bottom PA of firmware memory + + set r2,`/extra-mem #` \ Size of additional allocatable memory + set r3,#0xc0e \ Write bufferable + set r4,`extra-mem-va #' \ Virtual address + bl `allocate-and-map-sections` \ r1: bottom PA of extra memory + + set r2,`/dma-mem #` \ Size of DMA area + set r3,#0xc02 \ No caching or write buffering + set r4,`dma-mem-va #` \ Virtual address + bl `allocate-and-map-sections` \ r1: bottom PA of DMA memory + + mov r2,r1 \ Size of low memory + set r3,#0xc0e \ Cache and write bufferable + mov r4,#0 \ Virtual address + bl `allocate-and-map-sections` \ r1: 0 + + \ Now we have mapped all of DRAM + set r1,`sram-pa #` \ Address of SRAM + set r2,`/sram #` \ Size of SRAM + set r3,#0xc02 \ No caching or write buffering + bl `map-sections-v=p` + + set r1,`io-pa #` \ Address of I/O + set r2,`/io #` \ Size of I/O region + set r3,#0xc02 \ No caching or write buffering + bl `map-sections-v=p` + + set r1,`audio-sram-pa #` \ Address of Audio SRAM + set r2,`/audio-sram #` \ Size of audio SRAM + set r3,#0xc02 \ No caching or write buffering + bl `map-sections-v=p` + + set r1,`io-pa #` \ Address of I/O + set r2,`/io #` \ Size of I/O region + set r3,#0xc02 \ No caching or write buffering + set r4,`io-va #` \ Virtual address + bl `map-sections` + + set r1,`io2-pa #` \ Address of I/O + set r2,`/io2 #` \ Size of I/O region + set r3,#0xc02 \ No caching or write buffering + set r4,`io2-va #` \ Virtual address + bl `map-sections` + + mov pc, r10 +end-code + +\ LICENSE_BEGIN +\ Copyright (c) 2011 FirmWorks +\ +\ Permission is hereby granted, free of charge, to any person obtaining +\ a copy of this software and associated documentation files (the +\ "Software"), to deal in the Software without restriction, including +\ without limitation the rights to use, copy, modify, merge, publish, +\ distribute, sublicense, and/or sell copies of the Software, and to +\ permit persons to whom the Software is furnished to do so, subject to +\ the following conditions: +\ +\ The above copyright notice and this permission notice shall be +\ included in all copies or substantial portions of the Software. +\ +\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE +\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +\ +\ LICENSE_END Added: cpu/arm/mmp2/soc-config.fth ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ cpu/arm/mmp2/soc-config.fth Sun Jul 22 16:47:25 2012 (r3082) @@ -0,0 +1,2 @@ +create mmp2 +h# 10000 constant l2-#sets Modified: cpu/arm/mmp3/initmmu.fth ============================================================================== --- cpu/arm/mmp3/initmmu.fth Thu Jul 19 09:32:44 2012 (r3081) +++ cpu/arm/mmp3/initmmu.fth Sun Jul 22 16:47:25 2012 (r3082) @@ -79,7 +79,7 @@ inc r0,#0x20000000 \ Next way - will wrap to 0 inc r0,#32 \ Next set - set r2,#0x1ffe0 \ Mask for set field for L2 cache - depends on #sets=4096 + set r2,`l2-#sets h# 20 - #` \ Mask for set field for L2 cache ands r1,r0,r2 \ Mask set bits 0= until @@ -229,6 +229,8 @@ mov r0,0 mov r1,0xd0000000 \ Memory controller base address +[ifdef] mmp3 + \ MMP3 memory controller ldr r2,[r1,#0x10] \ MMAP0 register ands r3,r2,#1 \ Test CS_VALID movne r3,#0x10000 \ Scale factor for memory size @@ -258,6 +260,22 @@ movne r2,r2,lsl #11 \ Clear high bits above AREA_LENGTH field movne r2,r2,lsr #27 \ Move AREA_LENGTH to LSB addne r0,r0,r3,lsl r2 \ Compute bank size and add to accumulator +[else] + \ MMP2 memory controller + ldr r2,[r1,#0x100] \ MMAP0 register + ands r3,r2,#1 \ Test CS_VALID + movne r3,#0x10000 \ Scale factor for memory size + movne r2,r2,lsl #12 \ Clear high bits above AREA_LENGTH field + movne r2,r2,lsr #28 \ Move AREA_LENGTH to LSB + addne r0,r0,r3,lsl r2 \ Compute bank size and add to accumulator + + ldr r2,[r1,#0x110] \ MMAP1 register + ands r3,r2,#1 \ Test CS_VALID + movne r3,#0x10000 \ Scale factor for memory size + movne r2,r2,lsl #12 \ Clear high bits above AREA_LENGTH field + movne r2,r2,lsr #28 \ Move AREA_LENGTH to LSB + addne r0,r0,r3,lsl r2 \ Compute bank size and add to accumulator +[then] mov pc,lr end-code Modified: cpu/arm/mmp3/resetvec.fth ============================================================================== --- cpu/arm/mmp3/resetvec.fth Thu Jul 19 09:32:44 2012 (r3081) +++ cpu/arm/mmp3/resetvec.fth Sun Jul 22 16:47:25 2012 (r3082) @@ -113,7 +113,7 @@ end-code \ Load some additional subroutines that are used by the startup code -fload ${BP}/cpu/arm/mmp3/initmmu.fth \ Setup the initial virtual address map +fload ${BP}/cpu/arm/mmp2/initmmu.fth \ Setup the initial virtual address map \ **** This is the main-line code for the initial startup sequence. \ It is reached from a branch instruction (which will be patched in later) Added: cpu/arm/mmp3/soc-config.fth ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ cpu/arm/mmp3/soc-config.fth Sun Jul 22 16:47:25 2012 (r3082) @@ -0,0 +1,2 @@ +create mmp3 +h# 20000 constant l2-#sets Modified: cpu/arm/mmp3/thunderstone/config.fth ============================================================================== --- cpu/arm/mmp3/thunderstone/config.fth Thu Jul 19 09:32:44 2012 (r3081) +++ cpu/arm/mmp3/thunderstone/config.fth Sun Jul 22 16:47:25 2012 (r3082) @@ -6,4 +6,4 @@ create machine-signature ," TS0" -h# 20000 constant l2-#sets +fload ${BP}/cpu/arm/mmp3/soc-config.fth Modified: cpu/arm/olpc/3.0/config.fth ============================================================================== --- cpu/arm/olpc/3.0/config.fth Thu Jul 19 09:32:44 2012 (r3081) +++ cpu/arm/olpc/3.0/config.fth Sun Jul 22 16:47:25 2012 (r3082) @@ -30,6 +30,6 @@ char 4 constant expected-ec-version h# 8000 value /ec-flash -h# 10000 constant l2-#sets +fload ${BP}/cpu/arm/mmp2/soc-config.fth fload ${BP}/cpu/arm/olpc/3.0/gpiopins.fth Modified: cpu/arm/olpc/cl4/config.fth ============================================================================== --- cpu/arm/olpc/cl4/config.fth Thu Jul 19 09:32:44 2012 (r3081) +++ cpu/arm/olpc/cl4/config.fth Sun Jul 22 16:47:25 2012 (r3082) @@ -27,6 +27,6 @@ char 5 constant expected-ec-version h# 10000 value /ec-flash -h# 20000 constant l2-#sets +fload ${BP}/cpu/arm/mmp3/soc-config.fth fload ${BP}/cpu/arm/olpc/cl4/gpiopins.fth Modified: cpu/arm/olpc/resetvec.fth ============================================================================== --- cpu/arm/olpc/resetvec.fth Thu Jul 19 09:32:44 2012 (r3081) +++ cpu/arm/olpc/resetvec.fth Sun Jul 22 16:47:25 2012 (r3082) @@ -113,7 +113,7 @@ end-code \ Load some additional subroutines that are used by the startup code -fload ${BP}/cpu/arm/olpc/initmmu.fth \ Setup the initial virtual address map +fload ${BP}/cpu/arm/mmp2/initmmu.fth \ Setup the initial virtual address map \ **** This is the main-line code for the initial startup sequence. \ It is reached from a branch instruction (which will be patched in later)

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[commit] r3081 - cpu/arm/olpc/cl4
by repository service July 19, 2012

July 19, 2012

Author: wmb Date: Thu Jul 19 09:32:44 2012 New Revision: 3081 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3081 Log: OLPC CL4 - commented-out fload line for not-yet-implemented driver. Modified: cpu/arm/olpc/cl4/fw.bth Modified: cpu/arm/olpc/cl4/fw.bth ============================================================================== --- cpu/arm/olpc/cl4/fw.bth Thu Jul 19 01:24:14 2012 (r3080) +++ cpu/arm/olpc/cl4/fw.bth Thu Jul 19 09:32:44 2012 (r3081) @@ -31,7 +31,7 @@ fload ${BP}/cpu/arm/olpc/1.75/lcdcfg.fth fload ${BP}/cpu/arm/olpc/1.75/usb.fth -fload ${BP}/cpu/arm/olpc/nn-touchscreen.fth +\ fload ${BP}/cpu/arm/olpc/nn-touchscreen.fth fload ${BP}/cpu/arm/olpc/cl4/switches.fth fload ${BP}/cpu/arm/olpc/cl4/leds.fth fload ${BP}/cpu/arm/olpc/cl4/testitems.fth

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[commit] r3080 - cpu/arm/olpc/cl4
by repository service July 18, 2012

July 18, 2012

Author: wmb Date: Thu Jul 19 01:24:14 2012 New Revision: 3080 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3080 Log: OLPC CL4 - removed duplicate GPIO pin definition. Modified: cpu/arm/olpc/cl4/gpiopins.fth Modified: cpu/arm/olpc/cl4/gpiopins.fth ============================================================================== --- cpu/arm/olpc/cl4/gpiopins.fth Thu Jul 19 00:55:04 2012 (r3079) +++ cpu/arm/olpc/cl4/gpiopins.fth Thu Jul 19 01:24:14 2012 (r3080) @@ -53,8 +53,6 @@ d# 129 constant lid-switch-gpio# d# 130 constant ebook-mode-gpio# -d# 97 constant en-emmc-pwr-gpio# - d# 4 constant hdmi-scl-gpio# d# 5 constant hdmi-sda-gpio# d# 14 constant hdmi-hp-det-gpio#

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[commit] r3079 - cpu/arm/build
by repository service July 18, 2012

July 18, 2012

Author: wmb Date: Thu Jul 19 00:55:04 2012 New Revision: 3079 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3079 Log: svnignore Modified: cpu/arm/build/ (props changed)

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[commit] r3078 - cpu/arm/mmp3/thunderstone
by repository service July 18, 2012

July 18, 2012

Author: wmb Date: Thu Jul 19 00:54:18 2012 New Revision: 3078 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3078 Log: ARM Thunderstone - build prefw.dic in the build directory, not the source directory Modified: cpu/arm/mmp3/thunderstone/fw.bth Modified: cpu/arm/mmp3/thunderstone/fw.bth ============================================================================== --- cpu/arm/mmp3/thunderstone/fw.bth Thu Jul 19 00:49:49 2012 (r3077) +++ cpu/arm/mmp3/thunderstone/fw.bth Thu Jul 19 00:54:18 2012 (r3078) @@ -1,7 +1,7 @@ purpose: Build Open Firmware for Marvell MMP3 Thunderstone reference board \ See license at end of file -dictionary: ${BP}/cpu/arm/mmp3/thunderstone/prefw.dic +dictionary: ${BP}/cpu/arm/mmp3/thunderstone/build/prefw.dic command: &armforth &dictionary &this build-now

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[commit] r3077 - cpu/arm/olpc/cl4
by repository service July 18, 2012

July 18, 2012

Author: wmb Date: Thu Jul 19 00:49:49 2012 New Revision: 3077 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3077 Log: OLPC CL4 - minor comment change. Modified: cpu/arm/olpc/cl4/fw-version.fth Modified: cpu/arm/olpc/cl4/fw-version.fth ============================================================================== --- cpu/arm/olpc/cl4/fw-version.fth Thu Jul 19 00:49:20 2012 (r3076) +++ cpu/arm/olpc/cl4/fw-version.fth Thu Jul 19 00:49:49 2012 (r3077) @@ -3,7 +3,7 @@ macro: FW_MAJOR A macro: FW_MINOR 00 -\ Create a 2-character build/fw-suffix file to personalize your builds +\ Create a 2-character build/fw-suffix file to personalize your test builds " fw-suffix" $file-exists? [if] " fw-suffix" $read-file 2 min " ${FW_MINOR}%s" expand$ sprintf " FW_MINOR" $set-macro

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[commit] r3076 - cpu/arm/olpc/cl4/build
by repository service July 18, 2012

July 18, 2012

Author: wmb Date: Thu Jul 19 00:49:20 2012 New Revision: 3076 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3076 Log: svnignore Modified: cpu/arm/olpc/cl4/build/ (props changed)

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