July 2012 - openfirmware - mail.coreboot.org

[commit] r3105 - in cpu/arm: mmp3 olpc
by repository service July 31, 2012

July 31, 2012

Author: wmb Date: Wed Aug 1 00:41:17 2012 New Revision: 3105 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3105 Log: OLPC CL4 - fix USB2 PHY init and reinstate USB probing. Modified: cpu/arm/mmp3/usb2phy.fth cpu/arm/olpc/build-fw.fth cpu/arm/olpc/usb.fth Modified: cpu/arm/mmp3/usb2phy.fth ============================================================================== --- cpu/arm/mmp3/usb2phy.fth Tue Jul 31 11:05:47 2012 (r3104) +++ cpu/arm/mmp3/usb2phy.fth Wed Aug 1 00:41:17 2012 (r3105) @@ -3,16 +3,16 @@ : +usb2 ( offset -- offset' ) h# 20.7000 + ; -h# 04 +usb2 constant pll-reg0 -h# 08 +usb2 constant pll-reg1 -h# 10 +usb2 constant tx-reg0 -h# 14 +usb2 constant tx-reg1 -h# 18 +usb2 constant tx-reg2 -h# 20 +usb2 constant rx-reg0 -h# 24 +usb2 constant rx-reg1 -h# 28 +usb2 constant rx-reg2 + h# 04 +usb2 constant pll-reg0 + h# 08 +usb2 constant pll-reg1 + h# 10 +usb2 constant tx-reg0 + h# 14 +usb2 constant tx-reg1 + h# 18 +usb2 constant tx-reg2 + h# 20 +usb2 constant rx-reg0 + h# 24 +usb2 constant rx-reg1 + h# 28 +usb2 constant rx-reg2 \ h# 30 +usb2 constant ana-reg0 -\ h# 34 +usb2 constant ana-reg1 + h# 34 +usb2 constant ana-reg1 \ h# 38 +usb2 constant ana-reg2 \ h# 3c +usb2 constant dig-reg0 \ h# 40 +usb2 constant dig-reg1 @@ -22,9 +22,9 @@ \ h# 50 +usb2 constant test-reg1 \ h# 54 +usb2 constant test-reg2 \ h# 58 +usb2 constant charger-reg0 -\ h# 5c +usb2 constant otg-reg0 + h# 5c +usb2 constant otg-reg0 \ h# 60 +usb2 constant phy-mono -\ h# 64 +usb2 constant resetve-reg0 + h# 64 +usb2 constant reserve-reg0 \ h# 78 +usb2 constant icid-reg0 \ h# 7c +usb2 constant icid-reg1 @@ -38,28 +38,43 @@ : init-usb-phy ( -- ) h# f00 h# 100 +pmua io-clr -\ h# d00 h# 100 +pmua io-set \ Select 26 MHz VCXO clock - h# 200 h# 100 +pmua io-set \ Select crystal +\ h# d00 h# 100 +pmua io-set \ Select 26 MHz VCXO clock + h# 000 h# 100 +pmua io-set \ Select crystal - h# 3fff pll-reg0 io-clr \ REFDIV_MASK_B0 3e00, FBDIV_MASK_B0 01ff - h# 1af0 pll-reg0 io-set \ 0xd << 9 , 0xf0 << 0 +\ h# 3fff pll-reg0 io-clr \ REFDIV_MASK_B0 3e00, FBDIV_MASK_B0 01ff +\ h# 1af0 pll-reg0 io-set \ 0xd << 9 , 0xf0 << 0 +\ h# ca60 is the value to use for a 25 MHz crystal + h# daf0 pll-reg0 io-set \ 0xd << 9 , 0xf0 << 0 - h# 2773 pll-reg1 io-clr \ PU_PLL_MASK 2000, (LOCK_BYPASS) 1000, ICP_MASK 700, KVCO_MASK 70, CALI12_MASK 3 - h# 3333 pll-reg1 io-set \ 1 1 3 3 3 + h# 3000 reserve-reg0 io! \ Program PLLVDD12 per Marvell email - h# 0700 tx-reg0 io-clr \ TX_IMPCAL_VTH_MASK 0700 - h# 0200 tx-reg0 io-set \ 2 +\ h# 2773 pll-reg1 io-clr \ PU_PLL_MASK 2000, (LOCK_BYPASS) 1000, ICP_MASK 700, KVCO_MASK 70, CALI12_MASK 3 +\ h# 3333 pll-reg1 io-set \ 1 1 3 3 3 - h# 037f tx-reg1 io-clr \ TX_VDD12_MASK 300 , TX_AMP_MASK 70, TX_CK60_PHSEL_MASK f - h# 0344 tx-reg1 io-set \ 3 4 4 + h# 1433 pll-reg1 io! + d# 100 ms + h# 3433 pll-reg1 io! - h# 0c00 tx-reg2 io-clr \ TX_DRV_SLEWRATE_MASK c00 - h# 0800 tx-reg2 io-set \ 2 << 10 +\ h# 0700 tx-reg0 io-clr \ TX_IMPCAL_VTH_MASK 0700 +\ h# 0200 tx-reg0 io-set \ 2 + h# 0588 tx-reg0 io! \ 2 - h# 00f0 rx-reg0 io-clr \ RX_SQ_THRESH_MASK 00f0 - h# 00a0 rx-reg0 io-set \ a +\ h# 037f tx-reg1 io-clr \ TX_VDD12_MASK 300 , TX_AMP_MASK 70, TX_CK60_PHSEL_MASK f +\ h# 0344 tx-reg1 io-set \ 3 4 4 + h# 07c4 tx-reg1 io! - h# 0008 rx-reg1 io-set \ 1 << OTG_PU_OTG_SHIFT (3) +\ h# 0c00 tx-reg2 io-clr \ TX_DRV_SLEWRATE_MASK c00 +\ h# 0800 tx-reg2 io-set \ 2 << 10 + h# 0eff tx-reg2 io! + +\ h# 00f0 rx-reg0 io-clr \ RX_SQ_THRESH_MASK 00f0 +\ h# 00a0 rx-reg0 io-set \ a + h# aaa1 rx-reg0 io! + + h# 5000 ana-reg1 io-set \ Power up Analog Port + h# 0008 otg-reg0 io-set \ Power up OTG Port + +\ h# 0008 rx-reg1 io-set \ 1 << OTG_PU_OTG_SHIFT (3) \ Calibrate PHY d# 200 us Modified: cpu/arm/olpc/build-fw.fth ============================================================================== --- cpu/arm/olpc/build-fw.fth Tue Jul 31 11:05:47 2012 (r3104) +++ cpu/arm/olpc/build-fw.fth Wed Aug 1 00:41:17 2012 (r3105) @@ -316,9 +316,6 @@ warning @ warning off : stand-init stand-init -[ifdef] olpc-cl4 -." build-fw.fth: Skipping root node properties" cr exit -[then] root-device model-version$ 2dup model ( name$ ) " OLPC " encode-bytes 2swap encode-string encode+ " banner-name" property @@ -856,11 +853,7 @@ \+ use-screen-kbd ?text-on [ifdef] probe-usb factory-test? if d# 1000 ms then \ Extra USB probe delay in the factory -[ifdef] olpc-cl4 - ." build-fw.fth: not probing usb" cr -[else] probe-usb -[then] report-disk report-keyboard [then] Modified: cpu/arm/olpc/usb.fth ============================================================================== --- cpu/arm/olpc/usb.fth Tue Jul 31 11:05:47 2012 (r3104) +++ cpu/arm/olpc/usb.fth Wed Aug 1 00:41:17 2012 (r3105) @@ -29,9 +29,6 @@ : init-usb ( -- ) h# 9 h# 5c pmua! \ Enable clock to USB block reset-usb-hub -[ifdef] olpc-cl4 - ." olpc/usb.fth: Skipping USB phy init!" cr exit -[then] init-usb-phy ;

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[commit] r3104 - cpu/arm/mmp2
by repository service July 31, 2012

July 31, 2012

Author: wmb Date: Tue Jul 31 11:05:47 2012 New Revision: 3104 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3104 Log: OLPC ARM - revert the change to the SSP SSP_SSPSP register, as it was ineffective. Leave the cosmetic change to the way the other register offsets were specified, for clarity. Modified: cpu/arm/mmp2/sspspi.fth Modified: cpu/arm/mmp2/sspspi.fth ============================================================================== --- cpu/arm/mmp2/sspspi.fth Tue Jul 31 07:38:25 2012 (r3103) +++ cpu/arm/mmp2/sspspi.fth Tue Jul 31 11:05:47 2012 (r3104) @@ -11,14 +11,12 @@ : ssp-sscr1 ( -- adr ) ssp-base 4 + ; : ssp-sssr ( -- adr ) ssp-base 8 + ; : ssp-ssdr ( -- adr ) ssp-base h# 10 + ; -: ssp-sspsp ( -- adr ) ssp-base h# 2c + ; : ssp-spi-start ( -- ) \ Avoid reinitializing the device after the first time, as that \ seems to cause glitches that confuse the SPI FLASH chip ssp-sscr1 io@ 0= if exit then - h# 01 ssp-sspsp io! h# 07 ssp-sscr0 io! 0 ssp-sscr1 io! h# 87 ssp-sscr0 io!

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[commit] r3103 - cpu/arm/mmp2
by repository service July 30, 2012

July 30, 2012

Author: wmb Date: Tue Jul 31 07:38:25 2012 New Revision: 3103 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3103 Log: OLPC ARM - SSP SPI driver - sample data from EC on falling edge. Modified: cpu/arm/mmp2/sspspi.fth Modified: cpu/arm/mmp2/sspspi.fth ============================================================================== --- cpu/arm/mmp2/sspspi.fth Tue Jul 31 07:09:03 2012 (r3102) +++ cpu/arm/mmp2/sspspi.fth Tue Jul 31 07:38:25 2012 (r3103) @@ -8,15 +8,17 @@ h# 035000 value ssp-base \ SSP1 : ssp-sscr0 ( -- adr ) ssp-base ; -: ssp-sscr1 ( -- adr ) ssp-base la1+ ; -: ssp-sssr ( -- adr ) ssp-base 2 la+ ; -: ssp-ssdr ( -- adr ) ssp-base 4 la+ ; +: ssp-sscr1 ( -- adr ) ssp-base 4 + ; +: ssp-sssr ( -- adr ) ssp-base 8 + ; +: ssp-ssdr ( -- adr ) ssp-base h# 10 + ; +: ssp-sspsp ( -- adr ) ssp-base h# 2c + ; : ssp-spi-start ( -- ) \ Avoid reinitializing the device after the first time, as that \ seems to cause glitches that confuse the SPI FLASH chip ssp-sscr1 io@ 0= if exit then + h# 01 ssp-sspsp io! h# 07 ssp-sscr0 io! 0 ssp-sscr1 io! h# 87 ssp-sscr0 io!

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[commit] r3102 - in cpu/arm: mmp3 olpc
by repository service July 30, 2012

July 30, 2012

Author: wmb Date: Tue Jul 31 07:09:03 2012 New Revision: 3102 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3102 Log: OLPC CL4 - Use USB2 PHY driver instead of utmiphy driver for MMP3 chip. Added: cpu/arm/mmp3/usb2phy.fth Modified: cpu/arm/olpc/build-fw.fth Added: cpu/arm/mmp3/usb2phy.fth ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ cpu/arm/mmp3/usb2phy.fth Tue Jul 31 07:09:03 2012 (r3102) @@ -0,0 +1,74 @@ +\ See license at end of file +purpose: Init USB2 Phy in Marvell SoC + +: +usb2 ( offset -- offset' ) h# 20.7000 + ; + +h# 04 +usb2 constant pll-reg0 +h# 08 +usb2 constant pll-reg1 +h# 10 +usb2 constant tx-reg0 +h# 14 +usb2 constant tx-reg1 +h# 18 +usb2 constant tx-reg2 +h# 20 +usb2 constant rx-reg0 +h# 24 +usb2 constant rx-reg1 +h# 28 +usb2 constant rx-reg2 +\ h# 30 +usb2 constant ana-reg0 +\ h# 34 +usb2 constant ana-reg1 +\ h# 38 +usb2 constant ana-reg2 +\ h# 3c +usb2 constant dig-reg0 +\ h# 40 +usb2 constant dig-reg1 +\ h# 44 +usb2 constant dig-reg2 +\ h# 48 +usb2 constant dig-reg3 +\ h# 4c +usb2 constant test-reg0 +\ h# 50 +usb2 constant test-reg1 +\ h# 54 +usb2 constant test-reg2 +\ h# 58 +usb2 constant charger-reg0 +\ h# 5c +usb2 constant otg-reg0 +\ h# 60 +usb2 constant phy-mono +\ h# 64 +usb2 constant resetve-reg0 +\ h# 78 +usb2 constant icid-reg0 +\ h# 7c +usb2 constant icid-reg1 + +: wait-cal ( spins -- ) + 0 do + pll-reg1 io@ h# 8000 and if unloop exit then \ PLL_READY_MASK + 1 ms + loop + ." PLL calibrate timeout" cr +; + +: init-usb-phy ( -- ) + h# f00 h# 100 +pmua io-clr +\ h# d00 h# 100 +pmua io-set \ Select 26 MHz VCXO clock + h# 200 h# 100 +pmua io-set \ Select crystal + + h# 3fff pll-reg0 io-clr \ REFDIV_MASK_B0 3e00, FBDIV_MASK_B0 01ff + h# 1af0 pll-reg0 io-set \ 0xd << 9 , 0xf0 << 0 + + h# 2773 pll-reg1 io-clr \ PU_PLL_MASK 2000, (LOCK_BYPASS) 1000, ICP_MASK 700, KVCO_MASK 70, CALI12_MASK 3 + h# 3333 pll-reg1 io-set \ 1 1 3 3 3 + + h# 0700 tx-reg0 io-clr \ TX_IMPCAL_VTH_MASK 0700 + h# 0200 tx-reg0 io-set \ 2 + + h# 037f tx-reg1 io-clr \ TX_VDD12_MASK 300 , TX_AMP_MASK 70, TX_CK60_PHSEL_MASK f + h# 0344 tx-reg1 io-set \ 3 4 4 + + h# 0c00 tx-reg2 io-clr \ TX_DRV_SLEWRATE_MASK c00 + h# 0800 tx-reg2 io-set \ 2 << 10 + + h# 00f0 rx-reg0 io-clr \ RX_SQ_THRESH_MASK 00f0 + h# 00a0 rx-reg0 io-set \ a + + h# 0008 rx-reg1 io-set \ 1 << OTG_PU_OTG_SHIFT (3) + + \ Calibrate PHY + d# 200 us + h# 0004 pll-reg1 io-set \ 1 << PLL_VCOCAL_START_SHIFT (2) + d# 400 us + h# 2000 tx-reg0 io-set \ 1 << TX_RCAL_START_SHIFT (13) + d# 40 us + h# 2000 tx-reg0 io-clr \ 1 << TX_RCAL_START_SHIFT (13) + d# 400 us + + d# 100 wait-cal +; Modified: cpu/arm/olpc/build-fw.fth ============================================================================== --- cpu/arm/olpc/build-fw.fth Tue Jul 31 07:03:38 2012 (r3101) +++ cpu/arm/olpc/build-fw.fth Tue Jul 31 07:09:03 2012 (r3102) @@ -293,7 +293,11 @@ then ; +[ifdef] mmp3 +fload ${BP}/cpu/arm/mmp3/usb2phy.fth +[else] fload ${BP}/cpu/arm/marvell/utmiphy.fth +[then] fload ${BP}/cpu/arm/olpc/usb.fth fload ${BP}/dev/olpc/mmp2camera/loadpkg.fth

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[commit] r3101 - cpu/arm/olpc/cl4
by repository service July 30, 2012

July 30, 2012

Author: wmb Date: Tue Jul 31 07:03:38 2012 New Revision: 3101 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3101 Log: OLPC CL4 - include ecimage.bin in dropins. Modified: cpu/arm/olpc/cl4/olpc.bth Modified: cpu/arm/olpc/cl4/olpc.bth ============================================================================== --- cpu/arm/olpc/cl4/olpc.bth Tue Jul 31 04:18:27 2012 (r3100) +++ cpu/arm/olpc/cl4/olpc.bth Tue Jul 31 07:03:38 2012 (r3101) @@ -1,7 +1,7 @@ purpose: Construct the Open Firmware module collection command: &builder &this -\ in: ${BP}/cpu/arm/olpc/cl4/build/ec.img +in: ${BP}/cpu/arm/olpc/cl4/build/ec.img in: ${BP}/cpu/arm/olpc/cl4/build/fw.img in: ${BP}/cpu/arm/olpc/cl4/build/resetvec.img in: ${BP}/cpu/arm/olpc/cl4/build/mcastnand.bin @@ -151,7 +151,7 @@ " nandblaster15_rx.bin" " nb15_rx" $add-deflated-dropin " nandblaster_tx.bin" " nb_tx" $add-deflated-dropin -\ " ec.img" " ecimage.bin" $add-deflated-dropin + " ec.img" " ecimage.bin" $add-deflated-dropin " ${BP}/clients/emacs/x86/emacs.rc" " emacs.rc" $add-deflated-dropin " ${BP}/clients/emacs/emacs.hlp" " emacs.hlp" $add-deflated-dropin " ${BP}/clients/emacs/arm/emacs" " emacs" $add-deflated-dropin

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[commit] r3100 - cpu/arm/olpc
by repository service July 30, 2012

July 30, 2012

Author: pgf Date: Tue Jul 31 04:18:27 2012 New Revision: 3100 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3100 Log: edi-open: activate EDI with a dummy read Modified: cpu/arm/olpc/edi.fth Modified: cpu/arm/olpc/edi.fth ============================================================================== --- cpu/arm/olpc/edi.fth Mon Jul 30 10:25:06 2012 (r3099) +++ cpu/arm/olpc/edi.fth Tue Jul 31 04:18:27 2012 (r3100) @@ -334,6 +334,9 @@ : edi-open ( -- ) \ slow-edi-clock \ Target speed between 1 and 2 MHz spi-start + + \ dummy read, to activate EDI + h# ff22 edi-b@ drop set-chip-id

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[commit] r3099 - cpu/x86/pc/olpc/via
by repository service July 30, 2012

July 30, 2012

Author: quozl Date: Mon Jul 30 10:25:06 2012 New Revision: 3099 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3099 Log: OLPC XO-1.5 XO-1.75 - handle exceptions in open-nand during fs-update, #12025 Modified: cpu/x86/pc/olpc/via/fsupdate.fth Modified: cpu/x86/pc/olpc/via/fsupdate.fth ============================================================================== --- cpu/x86/pc/olpc/via/fsupdate.fth Mon Jul 30 09:58:46 2012 (r3098) +++ cpu/x86/pc/olpc/via/fsupdate.fth Mon Jul 30 10:25:06 2012 (r3099) @@ -290,7 +290,7 @@ ['] noop to show-progress ( adr len ) - open-nand ( adr len ) + ['] open-nand catch ?dup if .error security-failure then ( adr len ) \ clear-context nand-commands t-hms( @@ -309,7 +309,7 @@ ; : fs-update-from-list ( devlist$ -- ) - load-crypto if visible ." Crytpo load failed" cr show-sad security-failure then + load-crypto if visible ." Crypto load failed" cr show-sad security-failure then visible ( devlist$ ) begin dup while ( rem$ )

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[commit] r3098 - cpu/arm/olpc/cl4
by repository service July 30, 2012

July 30, 2012

Author: wmb Date: Mon Jul 30 09:58:46 2012 New Revision: 3098 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3098 Log: OLPC CL4 - EC platform# is 7 not 6. Modified: cpu/arm/olpc/cl4/config.fth Modified: cpu/arm/olpc/cl4/config.fth ============================================================================== --- cpu/arm/olpc/cl4/config.fth Mon Jul 30 09:41:11 2012 (r3097) +++ cpu/arm/olpc/cl4/config.fth Mon Jul 30 09:58:46 2012 (r3098) @@ -20,7 +20,7 @@ : signature$ " CL4" ; : model$ " olpc,XO-CL4" ; : compatible$ " olpc,xo-cl4" ; -: ec-platform$ ( -- adr len ) " 6" ; +: ec-platform$ ( -- adr len ) " 7" ; d# 10001 constant machine-type \ Backwards compatibility with non-device-tree kernel

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[commit] r3097 - cpu/arm/olpc
by repository service July 30, 2012

July 30, 2012

Author: wmb Date: Mon Jul 30 09:41:11 2012 New Revision: 3097 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3097 Log: OLPC CL4 - fixed typo in last commit. Modified: cpu/arm/olpc/build-fw.fth Modified: cpu/arm/olpc/build-fw.fth ============================================================================== --- cpu/arm/olpc/build-fw.fth Mon Jul 30 09:34:51 2012 (r3096) +++ cpu/arm/olpc/build-fw.fth Mon Jul 30 09:41:11 2012 (r3097) @@ -840,7 +840,7 @@ \+ use-screen-kbd open-hotspot install-alarm -[ifdef] olpc-clr +[ifdef] olpc-cl4 ." build-fw.fth: not sounding" cr [else] ?sound

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[commit] r3096 - cpu/arm/olpc
by repository service July 30, 2012

July 30, 2012

Author: wmb Date: Mon Jul 30 09:34:51 2012 New Revision: 3096 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3096 Log: OLPC CL4 - Skip some steps in the startup process that are not working yet. Ifdefs in common files need to be deleted as these steps are made to work. Modified: cpu/arm/olpc/banner.fth cpu/arm/olpc/build-fw.fth cpu/arm/olpc/usb.fth Modified: cpu/arm/olpc/banner.fth ============================================================================== --- cpu/arm/olpc/banner.fth Mon Jul 30 09:30:34 2012 (r3095) +++ cpu/arm/olpc/banner.fth Mon Jul 30 09:34:51 2012 (r3096) @@ -65,6 +65,9 @@ ; : .storage ( -- ) +[ifdef] olpc-cl4 +." olpc/banner.fth: Skipping .storage" cr exit +[then] internal-disk-present? 0= if ( ) get-internal-disk-info ( ) then Modified: cpu/arm/olpc/build-fw.fth ============================================================================== --- cpu/arm/olpc/build-fw.fth Mon Jul 30 09:30:34 2012 (r3095) +++ cpu/arm/olpc/build-fw.fth Mon Jul 30 09:34:51 2012 (r3096) @@ -312,6 +312,9 @@ warning @ warning off : stand-init stand-init +[ifdef] olpc-cl4 +." build-fw.fth: Skipping root node properties" cr exit +[then] root-device model-version$ 2dup model ( name$ ) " OLPC " encode-bytes 2swap encode-string encode+ " banner-name" property @@ -837,7 +840,11 @@ \+ use-screen-kbd open-hotspot install-alarm +[ifdef] olpc-clr + ." build-fw.fth: not sounding" cr +[else] ?sound +[then] ?games @@ -845,7 +852,11 @@ \+ use-screen-kbd ?text-on [ifdef] probe-usb factory-test? if d# 1000 ms then \ Extra USB probe delay in the factory +[ifdef] olpc-cl4 + ." build-fw.fth: not probing usb" cr +[else] probe-usb +[then] report-disk report-keyboard [then] @@ -867,6 +878,9 @@ auto-banner? if banner then \+ use-screen-kbd ?text-on +[ifdef] olpc-cl4 + ." Quitting before auto-boot" cr quit +[then] auto-boot \+ use-screen-kbd close-hotspot Modified: cpu/arm/olpc/usb.fth ============================================================================== --- cpu/arm/olpc/usb.fth Mon Jul 30 09:30:34 2012 (r3095) +++ cpu/arm/olpc/usb.fth Mon Jul 30 09:34:51 2012 (r3096) @@ -29,6 +29,9 @@ : init-usb ( -- ) h# 9 h# 5c pmua! \ Enable clock to USB block reset-usb-hub +[ifdef] olpc-cl4 + ." olpc/usb.fth: Skipping USB phy init!" cr exit +[then] init-usb-phy ;

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[commit] r3095 - cpu/arm/olpc/cl4
by repository service July 30, 2012

July 30, 2012

Author: wmb Date: Mon Jul 30 09:30:34 2012 New Revision: 3095 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3095 Log: OLPC CL4 - Use 1 MiB SPI FLASH for now. Modified: cpu/arm/olpc/cl4/config.fth Modified: cpu/arm/olpc/cl4/config.fth ============================================================================== --- cpu/arm/olpc/cl4/config.fth Mon Jul 30 09:13:00 2012 (r3094) +++ cpu/arm/olpc/cl4/config.fth Mon Jul 30 09:30:34 2012 (r3095) @@ -10,12 +10,12 @@ fload ${BP}/cpu/arm/mmp2/hwaddrs.fth fload ${BP}/cpu/arm/olpc/addrs.fth -h# 1f.0000 constant mfg-data-offset \ Offset to manufacturing data area in SPI FLASH -h# 20.0000 constant mfg-data-end-offset \ Offset to end of manufacturing data area in SPI FLASH -h# 1e.ffd0 constant crc-offset -h# 1e.ffc0 constant signature-offset +h# 10.0000 constant /rom \ Total size of SPI FLASH -h# 20.0000 constant /rom \ Total size of SPI FLASH +/rom h# 1.0000 - constant mfg-data-offset \ Offset to manufacturing data area in SPI FLASH +/rom constant mfg-data-end-offset \ Offset to end of manufacturing data area in SPI FLASH +mfg-data-offset h# 30 - constant crc-offset \ e.g. 1e.ffd0 +crc-offset h# 10 - constant signature-offset \ e.g. 1e.ffc0 : signature$ " CL4" ; : model$ " olpc,XO-CL4" ;

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[commit] r3094 - cpu/arm/olpc
by repository service July 30, 2012

July 30, 2012

Author: pgf Date: Mon Jul 30 09:13:00 2012 New Revision: 3094 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3094 Log: bbedi: clock faster on cl4 Modified: cpu/arm/olpc/bbedi.fth Modified: cpu/arm/olpc/bbedi.fth ============================================================================== --- cpu/arm/olpc/bbedi.fth Mon Jul 30 09:12:55 2012 (r3093) +++ cpu/arm/olpc/bbedi.fth Mon Jul 30 09:13:00 2012 (r3094) @@ -106,10 +106,15 @@ begin ands r3,tos,#0x80 \ Test bit +[ifdef] olpc-cl4 + strne r0,[r1,#0x18] \ Set MOSI if bit is non0 + streq r0,[r1,#0x24] \ Clr MOSI if bit is 0 +[else] strne r0,[r1,#0x18] \ Set MOSI if bit is non0 strne r0,[r1,#0x18] \ Set MOSI if bit is non0 \ Twice for delay - setup time to CLK streq r0,[r1,#0x24] \ Clr MOSI if bit is 0 streq r0,[r1,#0x24] \ Clr MOSI if bit is 0 \ Twice for delay - setup time to CLK +[then] str r4,[r1,#0x18] \ Set CLK str r4,[r1,#0x24] \ Clr CLK

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[commit] r3093 - in cpu/arm/olpc: . 1.75 cl4
by repository service July 30, 2012

July 30, 2012

Author: pgf Date: Mon Jul 30 09:12:55 2012 New Revision: 3093 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3093 Log: config ec-flags-offset on a per laptop basis Modified: cpu/arm/olpc/1.75/config.fth cpu/arm/olpc/cl4/config.fth cpu/arm/olpc/edi.fth Modified: cpu/arm/olpc/1.75/config.fth ============================================================================== --- cpu/arm/olpc/1.75/config.fth Mon Jul 30 09:12:43 2012 (r3092) +++ cpu/arm/olpc/1.75/config.fth Mon Jul 30 09:12:55 2012 (r3093) @@ -29,7 +29,8 @@ d# 9999 constant machine-type \ Backwards compatibility with non-device-tree kernel char 4 constant expected-ec-version -h# 8000 value /ec-flash +h# 8000 constant /ec-flash +h# 7e80 constant ec-flags-offset \ don't program or verify this page \ These constants are correct for XO-1.75 and XO-CL4; they might \ need to be changed for different hardware. See setup-gpios-hack Modified: cpu/arm/olpc/cl4/config.fth ============================================================================== --- cpu/arm/olpc/cl4/config.fth Mon Jul 30 09:12:43 2012 (r3092) +++ cpu/arm/olpc/cl4/config.fth Mon Jul 30 09:12:55 2012 (r3093) @@ -25,7 +25,8 @@ d# 10001 constant machine-type \ Backwards compatibility with non-device-tree kernel char 5 constant expected-ec-version -h# 10000 value /ec-flash +h# ec00 constant /ec-flash +h# eb80 constant ec-flags-offset \ don't program or verify this page fload ${BP}/cpu/arm/mmp3/soc-config.fth Modified: cpu/arm/olpc/edi.fth ============================================================================== --- cpu/arm/olpc/edi.fth Mon Jul 30 09:12:43 2012 (r3092) +++ cpu/arm/olpc/edi.fth Mon Jul 30 09:12:55 2012 (r3093) @@ -191,7 +191,7 @@ h# 70 flash-cmd ( ) \ Program page command wait-flash-busy ( ) ; -h# 7e80 constant ec-flags-offset + : edi-program-flash ( adr len offset -- ) cr ( adr len offset ) swap 0 ?do ( adr offset )

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[commit] r3092 - cpu/arm/olpc
by repository service July 30, 2012

July 30, 2012

Author: pgf Date: Mon Jul 30 09:12:43 2012 New Revision: 3092 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3092 Log: fixes for kb9010 edi programming Modified: cpu/arm/olpc/edi.fth Modified: cpu/arm/olpc/edi.fth ============================================================================== --- cpu/arm/olpc/edi.fth Mon Jul 30 09:12:40 2012 (r3091) +++ cpu/arm/olpc/edi.fth Mon Jul 30 09:12:43 2012 (r3092) @@ -16,10 +16,10 @@ 0 value edi-chip-id : kb9010? ( -- flag ) edi-chip-id 4 = ; -: efcfg ( -- reg# ) kb9010? if h# fea0 else h# fead then ; -: efcmd ( -- reg# ) kb9010? if h# fea7 else h# feac then ; -: efdat ( -- reg# ) kb9010? if h# feaa else h# feab then ; -: rst8051 ( -- reg# ) kb9010? if h# f010 else h# ff14 then ; +: efcfg ( -- reg# ) kb9010? if h# fead else h# fea0 then ; +: efcmd ( -- reg# ) kb9010? if h# feac else h# fea7 then ; +: efdat ( -- reg# ) kb9010? if h# feab else h# feaa then ; +: rst8051 ( -- reg# ) kb9010? if h# ff14 else h# f010 then ; \ Issues with .py code \ A14:A8 should be A15:A8 several places @@ -124,7 +124,7 @@ ; : edi-read-id ( -- id ) - spi-cs-on h# 3e spi-out 0 spi-out spi-in spi-cs-off + spi-cs-on h# 3e spi-out spi-in spi-cs-off ; : probe-rdid ( -- found? ) \ Verify that the EC is the one we think it is

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[commit] r3091 - cpu/arm/olpc/cl4
by repository service July 30, 2012

July 30, 2012

Author: wmb Date: Mon Jul 30 09:12:40 2012 New Revision: 3091 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3091 Log: OLPC CL4 - Working version of TIM header. Modified: cpu/arm/olpc/cl4/olpc.bth Modified: cpu/arm/olpc/cl4/olpc.bth ============================================================================== --- cpu/arm/olpc/cl4/olpc.bth Mon Jul 30 09:11:20 2012 (r3090) +++ cpu/arm/olpc/cl4/olpc.bth Mon Jul 30 09:12:40 2012 (r3091) @@ -41,20 +41,18 @@ fload ${BP}/cpu/arm/marvell/tim.fth -\ Marvel Trusted Image Module image creation script for -\ XO-CL4 platform. +\ Marvell Non-Trusted Image Module image creation script for XO-CL4 platform. -tim: 00030400 0 OLPC PXA212x -flash: SPI'10 -timh: TIMH 0 d101f000 -\ Main Processor code loaded into DRAM -image: OBMI 800 d101c000 ${BP}/cpu/arm/olpc/dummy.img -\ Secure Processor code loaded into SRAM -image: WTMI 1000 d1018000 shim.img -image: CFTH 2000 d1000000 cforth.img -reserved: - term: -end-reserved +tim: 00030400 0 THS'01 PXA212x + flash: SPI'10 + timh: TIMH 0 d101f000 + image: OBMI 2000 d1000000 cforth.img + reserved: + \ Disable USB download/init by enabling the FFUART for download + \ This works around a PHY init erratum for the B0 chip + uart: 00004646 1 + term: + end-reserved end-tim h# 20.0000 to reserved-start

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[commit] r3090 - cpu/arm/marvell
by repository service July 30, 2012

July 30, 2012

Author: wmb Date: Mon Jul 30 09:11:20 2012 New Revision: 3090 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3090 Log: OLPC ARM - Marvell TIM compiler enhancements for version 4 of the TIM header. Modified: cpu/arm/marvell/tim.fth Modified: cpu/arm/marvell/tim.fth ============================================================================== --- cpu/arm/marvell/tim.fth Mon Jul 30 09:08:16 2012 (r3089) +++ cpu/arm/marvell/tim.fth Mon Jul 30 09:11:20 2012 (r3090) @@ -1,11 +1,17 @@ : >hex ( n -- n' ) d# 10 /mod h# 10 * + ; + +0 value tim-version +: tim-v3? ( -- flag ) tim-version h# 00ffff00 and h# 00030400 = ; + : today>hex ( -- n ) today ( day month year ) d# 100 /mod ( day month yr century ) rot >hex >r ( day yr century r: hex-month ) rot >hex >r ( yr century r: hex-month hex-day ) >hex >r ( yr r: hex-month hex-day hex-century ) - >hex r> r> r> bljoin ( n ) + >hex r> r> r> + tim-v3? if 2swap then + bljoin ( n ) ; 0 value image-size @@ -71,26 +77,29 @@ ofd @ fclose image-adr image-size free-mem ; +: id, ( -- ) + get-word ( adr len ) + \ Convert trailing number to binary byte value - e.g. NAN'6 -> NAN(06) + 2dup [char] ' left-parse-string 2drop ( adr len tail$ ) + push-decimal $number pop-base abort" Bad number" ( adr len n ) + nip over 3 + c! 4 ( adr 4 ) + 4c, +; : tim: \ version trusted ID Processor 0 to last-image-adr here to tim-adr - hex, + get-hex dup l, to tim-version " TIMH" 4c, hex, \ Trusted \ hex, \ Date today>hex l, - get-word -4c, \ OEM ID + id, \ OEM ID get-word 2drop \ Processor ; : flash: \ id (e.g. NAN6) 5 0 do -1 l, loop - get-word ( adr len ) - \ Convert trailing number to binary byte value - e.g. NAN'6 -> NAN(06) - 2dup [char] ' left-parse-string 2drop ( adr len tail$ ) - push-decimal $number pop-base abort" Bad number" ( adr len n ) - nip over 3 + c! 4 ( adr 4 ) - 4c, + id, here to #images-adr 0 l, here to #keys-adr 0 l, @@ -112,12 +121,18 @@ ifd @ fgets ( size read-size ) over <> abort" Read failed" ( size ) ifd @ fclose ( size ) -\ h# 1000 round-up - h# 800 round-up -\ 4 round-up + \ Older BOOTROMs seem to want the size to be strongly aligned + tim-v3? if 4 else h# 800 then round-up ( size' ) ; : place-hash \ XXX need to implement non-null hash info - d# 10 0 do 0 l, loop + tim-v3? if + 0 l, \ Size to hash (should be -1 but 0 is in the examples) + d# 20 l, \ HashAlgorithmID - SHA-160 + d# 16 0 do 0 l, loop \ Hash + 0 l, \ Partition number + else + d# 10 0 do 0 l, loop \ Hash + then ; : +#images ( -- ) #images-adr l@ 1+ #images-adr l! ; : start-image ( adr len -- ) @@ -168,6 +183,8 @@ my-timh-adr if here tim-adr - my-timh-adr 4 la+ l! tim-adr image-adr my-timh-adr 2 la+ l@ + here tim-adr - move + else + tim-adr image-adr here tim-adr - move then ; : tbrx: \ xferloc @@ -198,4 +215,16 @@ : cmcc: \ " CMCC" start-package ; +: usb: \ Port# Enabled? + " "(00)USB" start-package hex, hex, end-package +; +: uart: \ Port# Enabled? + " "UART" start-package hex, hex, end-package +; +: cmon: \ + " CMON" start-package end-package +; +: core: \ number mapping + " CORE" start-package hex, hex, end-package +; : term: " Term" start-package end-package ;

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[commit] r3089 - in cpu/arm/olpc: . 1.75 3.0 cl4
by repository service July 30, 2012

July 30, 2012

Author: wmb Date: Mon Jul 30 09:08:16 2012 New Revision: 3089 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3089 Log: OLPC CL4 - Changed names of EDI GPIO pins to match new naming schema. Modified: cpu/arm/olpc/1.75/gpiopins.fth cpu/arm/olpc/3.0/gpiopins.fth cpu/arm/olpc/bbedi.fth cpu/arm/olpc/cl4/gpiopins.fth Modified: cpu/arm/olpc/1.75/gpiopins.fth ============================================================================== --- cpu/arm/olpc/1.75/gpiopins.fth Mon Jul 30 01:16:14 2012 (r3088) +++ cpu/arm/olpc/1.75/gpiopins.fth Mon Jul 30 09:08:16 2012 (r3089) @@ -30,6 +30,7 @@ d# 53 constant rtc-scl-gpio# d# 54 constant rtc-sda-gpio# +d# 103 constant ec-edi-miso-gpio# d# 104 constant ec-edi-cs-gpio# d# 105 constant ec-edi-mosi-gpio# d# 106 constant ec-edi-clk-gpio# Modified: cpu/arm/olpc/3.0/gpiopins.fth ============================================================================== --- cpu/arm/olpc/3.0/gpiopins.fth Mon Jul 30 01:16:14 2012 (r3088) +++ cpu/arm/olpc/3.0/gpiopins.fth Mon Jul 30 09:08:16 2012 (r3089) @@ -27,6 +27,7 @@ d# 53 constant rtc-scl-gpio# d# 54 constant rtc-sda-gpio# +d# 103 constant ec-edi-miso-gpio# d# 104 constant ec-edi-cs-gpio# d# 105 constant ec-edi-mosi-gpio# d# 106 constant ec-edi-clk-gpio# Modified: cpu/arm/olpc/bbedi.fth ============================================================================== --- cpu/arm/olpc/bbedi.fth Mon Jul 30 01:16:14 2012 (r3088) +++ cpu/arm/olpc/bbedi.fth Mon Jul 30 09:08:16 2012 (r3089) @@ -1,16 +1,11 @@ \ See license at end of file purpose: Bit-banged SPI bus driver for KB3731 EC "EDI" interface -d# 103 constant edi-miso-gpio# -d# 104 constant edi-cs-gpio# -d# 105 constant edi-mosi-gpio# -d# 106 constant edi-clk-gpio# +: edi-cs-on ( -- ) ec-edi-cs-gpio# gpio-clr ; +: edi-cs-off ( -- ) ec-edi-cs-gpio# gpio-set ; -: edi-cs-on ( -- ) edi-cs-gpio# gpio-clr ; -: edi-cs-off ( -- ) edi-cs-gpio# gpio-set ; - -: edi-clk-lo ( -- ) edi-clk-gpio# gpio-clr ; -: edi-clk-hi ( -- ) edi-clk-gpio# gpio-set ; +: edi-clk-lo ( -- ) ec-edi-clk-gpio# gpio-clr ; +: edi-clk-hi ( -- ) ec-edi-clk-gpio# gpio-set ; 0 [if] \ All this timing stuff is pointless because the GPIOs are so slow @@ -60,7 +55,7 @@ [ifndef] edi-bit! : edi-bit! ( flag -- ) - edi-mosi-gpio# swap if gpio-set else gpio-clr then + ec-edi-mosi-gpio# swap if gpio-set else gpio-clr then edi-clk-hi edi-dly edi-clk-lo @@ -71,13 +66,13 @@ [ifndef] edi-bit! : edi-bit! ( flag -- ) if - [ edi-mosi-gpio# >gpio-pin h# 18 + ] dliteral io! \ Fast gpio-set + [ ec-edi-mosi-gpio# >gpio-pin h# 18 + ] dliteral io! \ Fast gpio-set else - [ edi-mosi-gpio# >gpio-pin h# 24 + ] dliteral io! \ Fast gpio-clr + [ ec-edi-mosi-gpio# >gpio-pin h# 24 + ] dliteral io! \ Fast gpio-clr then - [ edi-clk-gpio# >gpio-pin h# 18 + ] dliteral io! \ Fast gpio-set + [ ec-edi-clk-gpio# >gpio-pin h# 18 + ] dliteral io! \ Fast gpio-set \ edi-dly - [ edi-clk-gpio# >gpio-pin h# 24 + ] dliteral io! \ Fast gpio-set + [ ec-edi-clk-gpio# >gpio-pin h# 24 + ] dliteral io! \ Fast gpio-set \ edi-dly ; [then] @@ -92,7 +87,7 @@ : edi-bit@ ( -- flag ) edi-clk-hi edi-dly - edi-miso-gpio# gpio-pin@ + ec-edi-miso-gpio# gpio-pin@ edi-clk-lo edi-dly ; Modified: cpu/arm/olpc/cl4/gpiopins.fth ============================================================================== --- cpu/arm/olpc/cl4/gpiopins.fth Mon Jul 30 01:16:14 2012 (r3088) +++ cpu/arm/olpc/cl4/gpiopins.fth Mon Jul 30 09:08:16 2012 (r3089) @@ -31,6 +31,7 @@ d# 53 constant rtc-scl-gpio# d# 54 constant rtc-sda-gpio# +d# 103 constant ec-edi-miso-gpio# d# 104 constant ec-edi-cs-gpio# d# 105 constant ec-edi-mosi-gpio# d# 106 constant ec-edi-clk-gpio#

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[commit] r3088 - cpu/arm/mmp2
by repository service July 29, 2012

July 29, 2012

Author: wmb Date: Mon Jul 30 01:16:14 2012 New Revision: 3088 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3088 Log: OLPC MMP GPIO driver - omit pxa-gpio entry from compatible property. Modified: cpu/arm/mmp2/gpio.fth Modified: cpu/arm/mmp2/gpio.fth ============================================================================== --- cpu/arm/mmp2/gpio.fth Fri Jul 27 04:57:48 2012 (r3087) +++ cpu/arm/mmp2/gpio.fth Mon Jul 30 01:16:14 2012 (r3088) @@ -44,8 +44,7 @@ 0 0 " d4019000" " /" begin-package " gpio" name - " mrvl,mmp-gpio" encode-string - " mrvl,pxa-gpio" encode-string encode+ " compatible" property + " mrvl,mmp-gpio" encode-string +compatible my-address my-space h# 1000 reg

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[commit] r3087 - cpu/arm/olpc
by repository service July 26, 2012

July 26, 2012

Author: wmb Date: Fri Jul 27 04:57:48 2012 New Revision: 3087 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3087 Log: OLPC ARM - this goes with svn 3084 - moving the UART assignment out to version-specific fw.bth Modified: cpu/arm/olpc/build-fw.fth Modified: cpu/arm/olpc/build-fw.fth ============================================================================== --- cpu/arm/olpc/build-fw.fth Fri Jul 27 04:55:18 2012 (r3086) +++ cpu/arm/olpc/build-fw.fth Fri Jul 27 04:57:48 2012 (r3087) @@ -31,8 +31,6 @@ fload ${BP}/dev/omap/diaguart.fth \ OMAP UART -h# 18000 +io to uart-base \ UART3 base address on MMP2 -\ h# 30000 +io to uart-base \ UART1 base address on MMP2 d# 26000000 to uart-clock-frequency \ CForth has already set up the serial port @@ -105,8 +103,14 @@ fload ${BP}/cpu/arm/mmp2/uart.fth " /apbc" encode-phandle d# 12 encode-int encode+ " clocks" property d# 24 " interrupts" integer-property - 1 " linux,unit#" integer-property end-package + +0 0 " d4017000" " /" begin-package \ UART2 + fload ${BP}/cpu/arm/mmp2/uart.fth + " /apbc" encode-phandle d# 11 encode-int encode+ " clocks" property + d# 28 " interrupts" integer-property +end-package + devalias com1 /uart : com1 " com1" ; ' com1 is fallback-device @@ -115,10 +119,13 @@ fload ${BP}/cpu/arm/mmp2/uart.fth d# 27 " interrupts" integer-property " /apbc" encode-phandle d# 10 encode-int encode+ " clocks" property - 0 " linux,unit#" integer-property end-package -devalias com2 /uart -: com2 " com2" ; + +0 0 " d4016000" " /" begin-package \ UART4 + fload ${BP}/cpu/arm/mmp2/uart.fth + " /apbc" encode-phandle d# 32 encode-int encode+ " clocks" property + d# 46 " interrupts" integer-property +end-package \needs md5init fload ${BP}/ofw/ppp/md5.fth \ MD5 hash @@ -342,7 +349,9 @@ fload ${BP}/cpu/arm/mmp2/thermal.fth fload ${BP}/cpu/arm/mmp2/fuse.fth +[ifdef] bsl-uart-base fload ${BP}/cpu/arm/olpc/bsl.fth +[then] [ifndef] virtual-mode warning off

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[commit] r3086 - dev/olpc/spiflash
by repository service July 26, 2012

July 26, 2012

Author: wmb Date: Fri Jul 27 04:55:18 2012 New Revision: 3086 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3086 Log: OLPC SPIFLASH driver - handle 2 MB parts. Modified: dev/olpc/spiflash/spiflash.fth Modified: dev/olpc/spiflash/spiflash.fth ============================================================================== --- dev/olpc/spiflash/spiflash.fth Fri Jul 27 04:54:42 2012 (r3085) +++ dev/olpc/spiflash/spiflash.fth Fri Jul 27 04:55:18 2012 (r3086) @@ -199,6 +199,8 @@ 3drop ; +: null-write ( adr len offset -- ) 3drop ; + \ This version is for SST parts, which use an auto-increment \ address command for fast writing. The SST part does not \ require you to stop at 256-byte page boundaries. The @@ -306,12 +308,16 @@ h# 13 of ['] common-write endof h# 34 of ['] common-write endof h# bf of ['] sst-write endof - h# 14 of - ." The SPI FLASH ID reads as 14. This is due to an infrequent hardware problem." cr - ." If you power cycle and try again, it will probably work the next time." cr - abort - endof - ( default ) true abort" Unsupported SPI FLASH ID" + h# 14 of ['] common-write endof +\ On some old board the ID would read as 14 when it should have been something else. +\ On CL4, 14 is the expected ID. +\ ." The SPI FLASH ID reads as 14. This is due to an infrequent hardware problem." cr +\ ." If you power cycle and try again, it will probably work the next time." cr +\ abort +\ endof + +\ ( default ) true abort" Unsupported SPI FLASH ID" + ( default ) ." Bad SPI FLASH ID " dup . cr ['] null-write swap endcase to write-spi-flash spi-unprotect @@ -326,6 +332,7 @@ else spi-id# case h# 13 of ." type 13 - Spansion, Winbond, or ST" endof + h# 14 of ." type 14 - 2 MB" endof h# 34 of ." type 34 - Macronyx" endof endcase then

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[commit] r3085 - cpu/arm/olpc
by repository service July 26, 2012

July 26, 2012

Author: wmb Date: Fri Jul 27 04:54:42 2012 New Revision: 3085 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3085 Log: OLPC EDI driver - handle differences between KB3731 and the new KB9010 Modified: cpu/arm/olpc/edi.fth Modified: cpu/arm/olpc/edi.fth ============================================================================== --- cpu/arm/olpc/edi.fth Fri Jul 27 04:49:02 2012 (r3084) +++ cpu/arm/olpc/edi.fth Fri Jul 27 04:54:42 2012 (r3085) @@ -13,6 +13,41 @@ \ spi-out ( byte -- ) - Send byte \ spi-in ( -- byte ) - Receive byte +0 value edi-chip-id +: kb9010? ( -- flag ) edi-chip-id 4 = ; + +: efcfg ( -- reg# ) kb9010? if h# fea0 else h# fead then ; +: efcmd ( -- reg# ) kb9010? if h# fea7 else h# feac then ; +: efdat ( -- reg# ) kb9010? if h# feaa else h# feab then ; +: rst8051 ( -- reg# ) kb9010? if h# f010 else h# ff14 then ; + +\ Issues with .py code +\ A14:A8 should be A15:A8 several places +\ inconsistent use of handle vs gd.handle in edi_erase_chip + +\ KB9010 stuff... +d# 59 d# 1024 * constant /kb9010-flash +h# fe80 constant wdtcfg +h# fe81 constant wdtpf +h# fe82 constant wdt +h# fea2 constant shccfg +\ h# fea5 constant xbicfg \ Unused +h# fea6 constant xbics +\ h# feae constant efdatr \ Unused +\ h# feaf constant emfburw +h# feb2 constant xbiwp +\ h# feb6 constant xbipump +\ h# feb7 constant xbifm +\ h# feb8 constant sbivr +h# feb9 constant xbis +h# ff0d constant clkcfg +h# ff0f constant pllcfg +h# ff1d constant ecsts +h# ff1f constant pllcfg2 +h# ff14 constant pxcfg + +\ end KB9010 stuff... + d# 128 constant /flash-page defer edi-progress ' drop to edi-progress ( n -- ) @@ -73,19 +108,25 @@ ; [then] : reset-8051 ( -- ) \ Reset 8-5 - h# f010 edi-b@ 1 or h# f010 edi-b! + rst8051 edi-b@ 1 or rst8051 edi-b! ; : unreset-8051 ( -- ) \ Reset 8-5 - h# f010 edi-b@ 1 invert and h# f010 edi-b! + rst8051 edi-b@ 1 invert and rst8051 edi-b! d# 2000 ms ; \ 0 in bit 0 selects masked ROM as code source for 8051, 1 selects FLASH \ The 8051 should be in reset mode when changing that bit. + : select-flash ( -- ) \ Setup for access to FLASH inside the EC + kb9010? if exit then h# f011 edi-b@ 1 or h# f011 edi-b! ; +: edi-read-id ( -- id ) + spi-cs-on h# 3e spi-out 0 spi-out spi-in spi-cs-off +; + : probe-rdid ( -- found? ) \ Verify that the EC is the one we think it is select-flash h# f01c ['] edi-w@ catch if ( x ) @@ -95,12 +136,15 @@ 1 invert and h# 3730 = ; +: finished? ( b -- flag ) + kb9010? if 2 and 0= else h# 80 = then +; : wait-flash-busy ( -- ) \ Wait for an erase/programming operation to complete get-msecs h# 1000 + ( limit ) begin ( limit ) - h# fea0 edi-b@ ( limit b ) - h# 80 and if ( limit ) - drop exit + efcfg edi-b@ ( limit b ) + finished? if ( limit ) + drop exit ( -- ) then ( limit ) dup get-msecs - 0<= ( limit timeout? ) until ( limit ) @@ -108,11 +152,12 @@ true abort" EDI FLASH busy timeout" ; -: flash-cmd ( b -- ) h# fea7 edi-b! ; +: flash-cmd ( b -- ) efcmd edi-b! ; : set-offset ( offset -- ) - wbsplit ( offset-low offset-hi ) - h# fea9 edi-b! h# fea8 edi-b! ( ) + lbsplit drop ( offset-low mid hi ) + kb9010? if h# feaa edi-b! else drop then ( offset-low mid ) + h# fea9 edi-b! h# fea8 edi-b! ( ) ; : erase-page ( offset -- ) @@ -121,14 +166,19 @@ h# 20 flash-cmd ( ) ; -: erase-chip ( -- ) wait-flash-busy h# 60 flash-cmd wait-flash-busy ; +: erase-chip ( -- ) + 0 set-offset \ New code does this (and does not wait-flash-busy) + wait-flash-busy h# 60 flash-cmd wait-flash-busy +; -: send-byte ( b offset -- ) set-offset h# feaa edi-b! 2 flash-cmd ; +: send-byte ( b offset -- ) set-offset efdat edi-b! 2 flash-cmd ; : edi-program-page ( adr offset -- ) \ Clear HVPL wait-flash-busy h# 80 flash-cmd ( adr offset ) + wait-flash-busy ( adr offset ) \ Necessary? + \ Fill the page buffer swap /flash-page bounds do ( offset ) i c@ over send-byte ( offset ) @@ -138,7 +188,7 @@ \ Commit the buffer to the FLASH memory wait-flash-busy ( ) \ Redundant wait? - h# 70 flash-cmd ( ) + h# 70 flash-cmd ( ) \ Program page command wait-flash-busy ( ) ; h# 7e80 constant ec-flags-offset @@ -162,11 +212,12 @@ edi-next-b@ i c! ( ) loop ( ) ; + : trim@ ( offset -- b ) set-offset h# 90 flash-cmd wait-flash-busy - h# feab edi-b@ + efdat edi-b@ \ reg: efdat ; : trim-tune ( -- ) \ firmware-id 0= if @@ -226,13 +277,76 @@ then \ then ; +: set-chip-id ( -- ) + ['] edi-read-id catch if ( ) + edi-read-id ( id ) + then ( id ) + to edi-chip-id +; +: kb9010-init ( -- ) + h# 00 xbics edi-b! + h# 00 xbiwp edi-b! \ Clear XBI write protection + h# ff wdt edi-b! \ Disable WDT + h# 00 wdtcfg edi-b! + h# 00 wdtpf edi-b! + h# 00 shccfg edi-b! \ Disable SHC + h# 0c clkcfg edi-b! \ Set the 8051 to 32Mhz + h# 08 efcfg edi-b! \ Enable the embedded flash cmd mode +; +base @ hex +create special-row 1f0 w, 1f1 w, 1f2 w, 1f4 w, 1f5 w, 1f6 w, 1f3 w, +create dest-regs feb9 w, feb6 w, feb6 w, feb7 w, feb8 w, feb8 w, feb7 w, +create source-bits 1f c, 0f c, 0f c, 0f c, 07 c, 1f c, 0f c, +create dest-bits 1f c, f0 c, 0f c, 0f c, e0 c, 1f c, f0 c, +create shift-cnt 0 c, 4 c, 0 c, 0 c, 5 c, 0 c, 4 c, +base ! +: kb9010-trimtune ( -- ) + h# 1ff trim@ 0<> if + 7 0 do + special-row i wa+ w@ edi-b@ ( data ) + source-bits i ca+ c@ or ( field ) + shift-cnt i ca+ c@ lshift ( field' ) + dest-regs i wa+ w@ edi-b@ ( field dest ) + dest-bits i ca+ c@ invert and or ( dest' ) + dest-regs i wa+ w@ edi-b! ( ) + loop + wait-flash-busy + then + h# 80 trim@ h# 5a = if + ecsts edi-b@ ( old-ecsts ) + dup 4 or ecsts edi-b! ( old-ecsts ) \ chipid is now pllcfg2 + + xbis edi-b@ h# 3f and ( old-ecsts xbis-bits ) + h# 81 edi-b@ 3 and 6 lshift or ( old-ecsts xbis-value ) + xbis edi-b! ( old-ecsts ) + + h# 82 edi-b@ h# f and 4 lshift ( old-ecsts pll-high ) + h# 83 edi-b@ h# f0 and 4 rshift or ( old-ecsts pll-value ) + pllcfg edi-b! ( old-ecsts ) + + pllcfg2 edi-b@ h# 3f and ( old-ecsts pll2-bits ) + h# 82 edi-b@ h# 30 and 2 lshift or ( old-ecsts pll2-value ) + pllcfg2 edi-b! ( old-ecsts ) + + ecsts edi-b! ( ) + then +; : edi-open ( -- ) \ slow-edi-clock \ Target speed between 1 and 2 MHz spi-start + + set-chip-id + \ The first operation often fails so retry it ['] select-flash catch if select-flash then reset-8051 - trim-tune + + kb9010? if + kb9010-init + kb9010-trimtune + else + trim-tune + then \ fast-edi-clock \ Target speed up to 16 MHz \ reset ;

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[commit] r3084 - in cpu/arm/olpc: . 1.75 3.0 cl4
by repository service July 26, 2012

July 26, 2012

Author: wmb Date: Fri Jul 27 04:49:02 2012 New Revision: 3084 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3084 Log: OLPC CL4 - handle different UART assignments between CL4 and 1.75. Modified: cpu/arm/olpc/1.75/config.fth cpu/arm/olpc/1.75/fw.bth cpu/arm/olpc/1.75/gpiopins.fth cpu/arm/olpc/3.0/config.fth cpu/arm/olpc/3.0/fw.bth cpu/arm/olpc/bsl.fth cpu/arm/olpc/cl4/fw.bth cpu/arm/olpc/cl4/gpiopins.fth Modified: cpu/arm/olpc/1.75/config.fth ============================================================================== --- cpu/arm/olpc/1.75/config.fth Sun Jul 22 16:48:28 2012 (r3083) +++ cpu/arm/olpc/1.75/config.fth Fri Jul 27 04:49:02 2012 (r3084) @@ -31,6 +31,9 @@ char 4 constant expected-ec-version h# 8000 value /ec-flash -h# 10000 constant l2-#sets +\ These constants are correct for XO-1.75 and XO-CL4; they might +\ need to be changed for different hardware. See setup-gpios-hack + +fload ${BP}/cpu/arm/mmp2/soc-config.fth fload ${BP}/cpu/arm/olpc/1.75/gpiopins.fth Modified: cpu/arm/olpc/1.75/fw.bth ============================================================================== --- cpu/arm/olpc/1.75/fw.bth Sun Jul 22 16:48:28 2012 (r3083) +++ cpu/arm/olpc/1.75/fw.bth Fri Jul 27 04:49:02 2012 (r3084) @@ -7,6 +7,9 @@ " fw.tag" r/w create-file drop tag-file ! +h# 17000 +io constant bsl-uart-base \ UART2 +h# 30 constant bsl-uart-clock-offset \ APBC_UART2_CLK_RST + fload ${BP}/cpu/arm/olpc/build-fw.fth \ The internal SD card shares the host controller circuitry with @@ -20,6 +23,26 @@ fload ${BP}/cpu/arm/olpc/emmc.fth +\ Setup UART configuration +h# d4018000 to uart-base \ UART3 +devalias com1 /uart@d4018000 + +dev /uart@d4030000 \ UART1 + 0 " linux,unit#" integer-property +device-end + +dev /uart@d4017000 \ UART2 + " disabled" " status" string-property +device-end + +dev /uart@d4018000 \ UART3 + 1 " linux,unit#" integer-property +device-end + +dev /uart@d4016000 \ UART4 + " disabled" " status" string-property +device-end + \ Device node for internal microSD dev /sd new-device Modified: cpu/arm/olpc/1.75/gpiopins.fth ============================================================================== --- cpu/arm/olpc/1.75/gpiopins.fth Sun Jul 22 16:48:28 2012 (r3083) +++ cpu/arm/olpc/1.75/gpiopins.fth Fri Jul 27 04:49:02 2012 (r3084) @@ -60,3 +60,7 @@ d# 15 constant rotate-gpio# d# 17 constant check-gpio# + +d# 14 constant touch-hd-gpio# +d# 139 constant touch-tck-gpio# +d# 98 constant touch-rst-gpio# Modified: cpu/arm/olpc/3.0/config.fth ============================================================================== --- cpu/arm/olpc/3.0/config.fth Sun Jul 22 16:48:28 2012 (r3083) +++ cpu/arm/olpc/3.0/config.fth Fri Jul 27 04:49:02 2012 (r3084) @@ -30,6 +30,8 @@ char 4 constant expected-ec-version h# 8000 value /ec-flash +h# 18000 constant console-uart-base + fload ${BP}/cpu/arm/mmp2/soc-config.fth fload ${BP}/cpu/arm/olpc/3.0/gpiopins.fth Modified: cpu/arm/olpc/3.0/fw.bth ============================================================================== --- cpu/arm/olpc/3.0/fw.bth Sun Jul 22 16:48:28 2012 (r3083) +++ cpu/arm/olpc/3.0/fw.bth Fri Jul 27 04:49:02 2012 (r3084) @@ -9,6 +9,26 @@ fload ${BP}/cpu/arm/olpc/build-fw.fth +\ Setup UART configuration +h# d4018000 to uart-base \ UART3 +devalias com1 /uart@d4018000 + +dev /uart@d4030000 \ UART1 + 0 " linux,unit#" integer-property +device-end + +dev /uart@d4017000 \ UART2 + " disabled" " status" string-property +device-end + +dev /uart@d4018000 \ UART3 + 1 " linux,unit#" integer-property +device-end + +dev /uart@d4016000 \ UART4 + " disabled" " status" string-property +device-end + fload ${BP}/cpu/arm/olpc/emmc.fth devalias int /sd/disk@3 Modified: cpu/arm/olpc/bsl.fth ============================================================================== --- cpu/arm/olpc/bsl.fth Sun Jul 22 16:48:28 2012 (r3083) +++ cpu/arm/olpc/bsl.fth Fri Jul 27 04:49:02 2012 (r3084) @@ -4,20 +4,13 @@ \ devalias bsl /uart@NNNN:9600,8,e,1//bsl-protocol -\ These constants are correct for XO-1.75 and XO-CL4; they might -\ need to be changed for different hardware. See setup-gpios-hack - -h# 17000 +io constant bsl-uart-base \ UART2 - -d# 98 constant bsl-test-gpio# \ GPIO98 is alternate function 0 (the default) -d# 152 constant bsl-rst-gpio# \ SM_BELn, with GPIO152 as alternate function 1 - \ This is platform-dependent : setup-gpios ( -- ) - 3 d# 55 af! 3 d# 56 af! \ Setup pins for UART2 - 0 bsl-test-gpio# af! \ Set to GPIO function - 1 bsl-rst-gpio# af! \ Set to GPIO function (AF0 is SM_BELn for this pin) +\ The pin setup should be done in CForth, but it's complicated by the fact that the touch-enabled CL2 uses GPIO 56 differently from the ordinary one +[ifdef] olpc-cl2 3 d# 55 af! 3 d# 56 af! [then] \ Setup pins for UART2 + 0 touch-tck-gpio# af! \ Set to GPIO function + 1 touch-rst-gpio# af! \ Set to GPIO function (AF0 is SM_BELn for this pin) ; 0 [if] @@ -33,8 +26,8 @@ d# 115 to test-gpio# \ Normally UART3 TXD, but repurposed as a GPIO d# 116 to rst-gpio# \ Normally UART3 RXD, but repurposed as a GPIO - 0 bsl-test-gpio# af! \ Set to GPIO function instead of UART3 - 0 bsl-rst-gpio# af! \ Set to GPIO function instead of UART3 + 0 touch-tck-gpio# af! \ Set to GPIO function instead of UART3 + 0 touch-rst-gpio# af! \ Set to GPIO function instead of UART3 ; [then] @@ -43,8 +36,8 @@ : bsl-baud ( baud-rate -- ) \ 9600,8,e,1 uart-base >r ( baud-rate r: uart-base ) bsl-uart-base to uart-base - h# 13 h# 30 apbc! \ enable the uart2 clocks - h# 40 1 uart! \ uart unit enable + h# 13 bsl-uart-clock-offset apbc! \ enable the uart2 clocks + h# 40 1 uart! \ uart unit enable baud h# 1b 3 uart! ( r: uart-base ) r> to uart-base ( ) ; @@ -63,35 +56,35 @@ : bsl-open ( -- ) setup-gpios - bsl-rst-gpio# gpio-clr - bsl-test-gpio# gpio-clr - bsl-rst-gpio# gpio-dir-out - bsl-test-gpio# gpio-dir-out + touch-rst-gpio# gpio-clr + touch-tck-gpio# gpio-clr + touch-rst-gpio# gpio-dir-out + touch-tck-gpio# gpio-dir-out d# 9600 bsl-baud ; : bsl-close ( -- ) - bsl-rst-gpio# gpio-dir-in - bsl-test-gpio# gpio-dir-in + touch-rst-gpio# gpio-dir-in + touch-tck-gpio# gpio-dir-in ; : msp430-off ( -- ) - bsl-rst-gpio# gpio-clr - bsl-test-gpio# gpio-clr + touch-rst-gpio# gpio-clr + touch-tck-gpio# gpio-clr ; : dly ( -- ) d# 10 ms ; : start-bsl ( -- ) bsl-open d# 250 ms - bsl-test-gpio# gpio-set + touch-tck-gpio# gpio-set dly - bsl-test-gpio# gpio-clr + touch-tck-gpio# gpio-clr dly - bsl-test-gpio# gpio-set + touch-tck-gpio# gpio-set dly - bsl-rst-gpio# gpio-set + touch-rst-gpio# gpio-set dly - bsl-test-gpio# gpio-clr + touch-tck-gpio# gpio-clr ; : flush-bsl Modified: cpu/arm/olpc/cl4/fw.bth ============================================================================== --- cpu/arm/olpc/cl4/fw.bth Sun Jul 22 16:48:28 2012 (r3083) +++ cpu/arm/olpc/cl4/fw.bth Fri Jul 27 04:49:02 2012 (r3084) @@ -7,8 +7,33 @@ " fw.tag" r/w create-file drop tag-file ! +h# 16000 +io constant bsl-uart-base \ UART4 +h# 88 constant bsl-uart-clock-offset \ APBC_UART4_CLK_RST + fload ${BP}/cpu/arm/olpc/build-fw.fth +true to stand-init-debug? + +\ Setup UART configuration +h# d4017000 to uart-base \ UART2 +devalias com1 /uart@d4017000 + +dev /uart@d4030000 \ UART1 + 0 " linux,unit#" integer-property +device-end + +dev /uart@d4017000 \ UART2 + 1 " linux,unit#" integer-property +device-end + +dev /uart@d4018000 \ UART3 + " disabled" " status" string-property +device-end + +dev /uart@d4016000 \ UART4 + " disabled" " status" string-property \ Used for touchscreen BSL +device-end + dev /sd new-device 4 encode-int " reg" property Modified: cpu/arm/olpc/cl4/gpiopins.fth ============================================================================== --- cpu/arm/olpc/cl4/gpiopins.fth Sun Jul 22 16:48:28 2012 (r3083) +++ cpu/arm/olpc/cl4/gpiopins.fth Fri Jul 27 04:49:02 2012 (r3084) @@ -11,8 +11,8 @@ d# 155 constant ec-spi-cmd-gpio# d# 113 constant ec-spi-ack-gpio# -d# 167 constant dcon-scl-gpio# -d# 168 constant dcon-sda-gpio# +d# 168 constant dcon-scl-gpio# +d# 167 constant dcon-sda-gpio# d# 126 constant dcon-irq-gpio# d# 142 constant dcon-load-gpio#

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[commit] r3083 - cpu/arm/mmp3
by repository service July 22, 2012

July 22, 2012

Author: wmb Date: Sun Jul 22 16:48:28 2012 New Revision: 3083 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3083 Log: OLPC ARM - the last commit makes cpu/arm/mmp3/initmmu.fth unnecessary, so delete it. Deleted: cpu/arm/mmp3/initmmu.fth

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[commit] r3082 - in cpu/arm: mmp2 mmp3 mmp3/thunderstone olpc olpc/3.0 olpc/cl4
by repository service July 22, 2012

July 22, 2012

Author: wmb Date: Sun Jul 22 16:47:25 2012 New Revision: 3082 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3082 Log: OLPC ARM - coalesced initmmu.fth into one file, with parameterized differences between mmp2 and mmp3. Added: cpu/arm/mmp2/initmmu.fth cpu/arm/mmp2/soc-config.fth cpu/arm/mmp3/soc-config.fth Modified: cpu/arm/mmp3/initmmu.fth cpu/arm/mmp3/resetvec.fth cpu/arm/mmp3/thunderstone/config.fth cpu/arm/olpc/3.0/config.fth cpu/arm/olpc/cl4/config.fth cpu/arm/olpc/resetvec.fth Added: cpu/arm/mmp2/initmmu.fth ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ cpu/arm/mmp2/initmmu.fth Sun Jul 22 16:47:25 2012 (r3082) @@ -0,0 +1,389 @@ +\ See license at end of file +purpose: Setup the initial virtual address map + +[ifdef] notdef +\ Synchronizes the instruction and data caches over the indicated +\ address range, thus allowing the execution of instructions that +\ have recently been written to memory. +label sync-cache-range \ r0: adr, r1: len + begin + mcr p15, 0, r0, cr7, cr10, 1 \ clean D$ line + mcr p15, 0, r0, cr7, cr5, 1 \ invalidate I$ line + add r0, r0, #32 \ Advance to next line + subs r1, r1, #32 + 0<= until + mov pc, lr +end-code + +\ Forces data in the cache within the indicated address range +\ into memory. +label clean-dcache-range \ r0: adr, r1: len + begin + mcr p15, 0, r0, cr7, cr10, 1 \ clean D$ line + add r0, r0, #32 \ Advance to next line + subs r1, r1, #32 + 0<= until + mov pc, lr +end-code +[then] + +\ Turn on the caches +label caches-on + + \ Invalidate the entire L1 data cache by looping over all sets and ways + mov r0,#0 \ Start with set/way 0 of L1 cache + begin + \ In this unrolled loop, the number of iterations (8) and the increment + \ value (0x20000000) depend on fact that this cache has 8 ways. + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way - will wrap to 0 + + inc r0,#32 \ Next set + ands r1,r0,#0xfe0 \ Mask set bits - depends on #sets=128 + 0= until + + \ Invalidate the entire L2 cache by looping over all sets and ways + mov r0,#2 \ Start with set/way 0 of L2 cache + begin + \ In this unrolled loop, the number of iterations (8) and the increment + \ value (0x20000000) depend on fact that this cache has 8 ways. + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr6, 2 \ Invalidate D$ line by set/index + inc r0,#0x20000000 \ Next way - will wrap to 0 + + inc r0,#32 \ Next set + set r2,`l2-#sets h# 20 - #` \ Mask for set field for L2 cache + ands r1,r0,r2 \ Mask set bits + 0= until + + mcr p15, 0, r0, cr7, cr5, 0 \ Invalidate entire I$ + + mcr p15, 0, r0, cr7, cr5, 6 \ Flush branch target cache + + mrc p15,0,r0,cr1,cr0,0 \ Read control register + orr r0,r0,#0x1000 \ ICache on + orr r0,r0,#0x0800 \ Branch prediction on + orr r0,r0,#0x0004 \ DCache on + mcr p15,0,r0,cr1,cr0,0 \ Write control register with new bits + + mrc p15,0,r0,cr1,cr0,1 \ Read aux control register + orr r0,r0,#0x0002 \ L2 Cache on + mcr p15,0,r0,cr1,cr0,1 \ Write control register with new bits + + mov pc, lr +end-code + +\ Synchronizes the instruction and data caches, thus allowing the +\ execution of instructions that have recently been written to memory. +\ This version, which operates on the entire cache, is more efficient +\ than an address-range version when the range is larger than the +\ L1 cache size. +label sync-caches \ No args or returns, kills r0 and r1 + + \ Clean (push the data out to a higher level) the entire L1 data cache + \ by looping over all sets and ways + mov r0,#0 \ Start with set/way 0 of L1 cache + begin + \ In this unrolled loop, the number of iterations (8) and the increment + \ value (0x20000000) depend on fact that this cache has 8 ways. + mcr p15, 0, r0, cr7, cr10, 2 \ clean D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr10, 2 \ clean D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr10, 2 \ clean D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr10, 2 \ clean D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr10, 2 \ clean D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr10, 2 \ clean D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr10, 2 \ clean D$ line by set/index + inc r0,#0x20000000 \ Next way + mcr p15, 0, r0, cr7, cr10, 2 \ clean D$ line by set/index + inc r0,#0x20000000 \ Next way - will wrap to 0 + + inc r0,#32 \ Next set + ands r1,r0,#0xfe0 \ Mask set bits - depends on #sets=128 + 0= until + + mcr p15, 0, r0, cr7, cr5, 0 \ Invalidate entire I$ + mov pc, lr +end-code + +\ Insert zeros into the code stream until a cache line boundary is reached +\ This must be enclosed with "ahead .. then" to branch around the zeros. +: cache-align ( -- ) + begin + here [ also assembler ] asm-base [ previous ] - h# 1f and + while + 0 l, + repeat +; + +\ Turn on the MMU +label enable-mmu ( -- ) + mvn r2, #0 \ Set domains for Manager access - all domains su + mcr p15,0,r2,3,0,0 \ Update register 3 in CP15 - domain access control + + \ Enable the MMU + mrc p15, 0, r2, 1, 0, 0 \ Read current settings in control reg + mov r2, r2, LSL #18 \ Upper 18-bits must be written as zero, + mov r2, r2, LSR #18 \ ... clear them now. + + orr r2, r2, 0x200 \ Set the ROM Protection bit + bic r2, r2, 0x100 \ Clear the System Protection bit + orr r2, r2, 0x001 \ Set the MMU bit + + \ Align following code to a cache line boundary + ahead + cache-align + then + + mcr p15, 0, r2, cr1, cr0, 0 \ Go Virtual + mrc p15, 0, r2, cr2, cr0, 0 \ Ensure that the write completes + mov r2, r2 \ before continuing + sub pc, pc, #4 + + mov pc, lr +end-code + +\ Map sections within the given address range, using +\ the given protection/cacheability mode. pt-adr is the page table base address. +label map-sections ( r0: pt-adr, r1: padr, r2: len, r3: mode r4: vadr -- ) + add r1, r1, r3 \ PA+mode + begin + str r1, [r0, r4, lsr #18] + + inc r1, #0x100000 + inc r4, #0x100000 + decs r2, #0x100000 + 0<= until + + mov pc, lr +end-code + +\ Map sections virtual=physical within the given address range, using +\ the given protection/cacheability mode. pt-adr is the page table base address. +label map-sections-v=p ( r0: pt-adr, r1: adr, r2: len, r3: mode -- ) + begin + add r4, r1, r3 \ PA+mode + str r4, [r0, r1, lsr #18] + + inc r1, #0x100000 + decs r2, #0x100000 + 0<= until + + mov pc, lr +end-code + +\ Map sections within the given address range, using +\ the given protection/cacheability mode. pt-adr is the page table base address. +label allocate-and-map-sections ( r0: pt-adr, r1: padr-top, r2: len, r3: mode r4: vadr -- r1: padr-bot ) + inc r4, r2 \ vadr-top + add r1, r1, r3 \ PA+mode + begin + dec r1, #0x100000 + dec r4, #0x100000 + + str r1, [r0, r4, lsr #18] + + decs r2, #0x100000 + 0<= until + + mov r1,r1,lsr #20 \ Clear out mode bits in padr + mov r1,r1,lsl #20 + + mov pc, lr +end-code + +\ This assumes that there are no holes and that unused MMAP registers have CS_VALID=0 +label dramsize ( -- r0: size-in-bytes ) + mov r0,0 + mov r1,0xd0000000 \ Memory controller base address + +\ ldr r2,[r1,#0x00] \ MMAP0 register +\ and r2,r2,#0xff \ Revision +\ cmps r2,#0xNN \ MMP3? +\ >= if + +[ifdef] mmp3 + \ MMP3 memory controller - 2 banks, MMAP registers at 0x10 and 0x14 + ldr r2,[r1,#0x10] \ MMAP0 register + ands r3,r2,#1 \ Test CS_VALID + movne r3,#0x10000 \ Scale factor for memory size + movne r2,r2,lsl #11 \ Clear high bits above AREA_LENGTH field + movne r2,r2,lsr #27 \ Move AREA_LENGTH to LSB + addne r0,r0,r3,lsl r2 \ Compute bank size and add to accumulator + + ldr r2,[r1,#0x14] \ MMAP1 register + ands r3,r2,#1 \ Test CS_VALID + movne r3,#0x10000 \ Scale factor for memory size + movne r2,r2,lsl #11 \ Clear high bits above AREA_LENGTH field + movne r2,r2,lsr #27 \ Move AREA_LENGTH to LSB + addne r0,r0,r3,lsl r2 \ Compute bank size and add to accumulator + + add r1,r1,#0x10000 \ Memory controller base address d0010000 + + ldr r2,[r1,#0x10] \ MMAP0 register + ands r3,r2,#1 \ Test CS_VALID + movne r3,#0x10000 \ Scale factor for memory size + movne r2,r2,lsl #11 \ Clear high bits above AREA_LENGTH field + movne r2,r2,lsr #27 \ Move AREA_LENGTH to LSB + addne r0,r0,r3,lsl r2 \ Compute bank size and add to accumulator + + ldr r2,[r1,#0x14] \ MMAP1 register + ands r3,r2,#1 \ Test CS_VALID + movne r3,#0x10000 \ Scale factor for memory size + movne r2,r2,lsl #11 \ Clear high bits above AREA_LENGTH field + movne r2,r2,lsr #27 \ Move AREA_LENGTH to LSB + addne r0,r0,r3,lsl r2 \ Compute bank size and add to accumulator +[else] + \ MMP2 memory controller - 1 bank, MMAP registers at 0x100 and 0x110 + ldr r2,[r1,#0x100] \ MMAP0 register + ands r3,r2,#1 \ Test CS_VALID + movne r3,#0x10000 \ Scale factor for memory size + movne r2,r2,lsl #12 \ Clear high bits above AREA_LENGTH field + movne r2,r2,lsr #28 \ Move AREA_LENGTH to LSB + addne r0,r0,r3,lsl r2 \ Compute bank size and add to accumulator + + ldr r2,[r1,#0x110] \ MMAP1 register + ands r3,r2,#1 \ Test CS_VALID + movne r3,#0x10000 \ Scale factor for memory size + movne r2,r2,lsl #12 \ Clear high bits above AREA_LENGTH field + movne r2,r2,lsr #28 \ Move AREA_LENGTH to LSB + addne r0,r0,r3,lsl r2 \ Compute bank size and add to accumulator +[then] + + mov pc,lr +end-code + +\ Initial the section table, setting up mappings for the platform-specific +\ address ranges that the firmware uses. +\ Destroys: r0-r4 +label init-map ( -- ) + mov r10,lr + + bl `dramsize` \ r0: total-memory-size + mov r1,r0 \ r1: allocation pointer starts at top of DRAM + + \ Locate the page table at the top of the firmware memory, just below the frame buffer + dec r0,`/fb-mem #` \ Size of frame buffer + dec r0,`/page-table #` \ r0: page-table-pa + + mcr p15,0,r0,cr2,cr0,0 \ Set table base address + + \ Clear the entire section table for starters + mov r2, #0x1000 \ Section# + mov r3, #0 \ Invalid section entry + begin + subs r2, r2, #1 \ Decrement section number + str r3, [r0, r2, lsl #2] \ Invalidate section entry + 0= until + \ r1: top of DRAM + set r2,`/fb-mem #` \ Size of frame buffer + set r3,#0xc06 \ Write bufferable + set r4,`fb-mem-va #` \ Virtual address + bl `allocate-and-map-sections \ r1: bottom PA of frame buffer + + set r2,`/fw-mem #` \ Size of firmware region + set r3,#0xc0e \ Write bufferable + set r4,`fw-mem-va #` \ Virtual address + bl `allocate-and-map-sections` \ r1: bottom PA of firmware memory + + set r2,`/extra-mem #` \ Size of additional allocatable memory + set r3,#0xc0e \ Write bufferable + set r4,`extra-mem-va #' \ Virtual address + bl `allocate-and-map-sections` \ r1: bottom PA of extra memory + + set r2,`/dma-mem #` \ Size of DMA area + set r3,#0xc02 \ No caching or write buffering + set r4,`dma-mem-va #` \ Virtual address + bl `allocate-and-map-sections` \ r1: bottom PA of DMA memory + + mov r2,r1 \ Size of low memory + set r3,#0xc0e \ Cache and write bufferable + mov r4,#0 \ Virtual address + bl `allocate-and-map-sections` \ r1: 0 + + \ Now we have mapped all of DRAM + set r1,`sram-pa #` \ Address of SRAM + set r2,`/sram #` \ Size of SRAM + set r3,#0xc02 \ No caching or write buffering + bl `map-sections-v=p` + + set r1,`io-pa #` \ Address of I/O + set r2,`/io #` \ Size of I/O region + set r3,#0xc02 \ No caching or write buffering + bl `map-sections-v=p` + + set r1,`audio-sram-pa #` \ Address of Audio SRAM + set r2,`/audio-sram #` \ Size of audio SRAM + set r3,#0xc02 \ No caching or write buffering + bl `map-sections-v=p` + + set r1,`io-pa #` \ Address of I/O + set r2,`/io #` \ Size of I/O region + set r3,#0xc02 \ No caching or write buffering + set r4,`io-va #` \ Virtual address + bl `map-sections` + + set r1,`io2-pa #` \ Address of I/O + set r2,`/io2 #` \ Size of I/O region + set r3,#0xc02 \ No caching or write buffering + set r4,`io2-va #` \ Virtual address + bl `map-sections` + + mov pc, r10 +end-code + +\ LICENSE_BEGIN +\ Copyright (c) 2011 FirmWorks +\ +\ Permission is hereby granted, free of charge, to any person obtaining +\ a copy of this software and associated documentation files (the +\ "Software"), to deal in the Software without restriction, including +\ without limitation the rights to use, copy, modify, merge, publish, +\ distribute, sublicense, and/or sell copies of the Software, and to +\ permit persons to whom the Software is furnished to do so, subject to +\ the following conditions: +\ +\ The above copyright notice and this permission notice shall be +\ included in all copies or substantial portions of the Software. +\ +\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE +\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +\ +\ LICENSE_END Added: cpu/arm/mmp2/soc-config.fth ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ cpu/arm/mmp2/soc-config.fth Sun Jul 22 16:47:25 2012 (r3082) @@ -0,0 +1,2 @@ +create mmp2 +h# 10000 constant l2-#sets Modified: cpu/arm/mmp3/initmmu.fth ============================================================================== --- cpu/arm/mmp3/initmmu.fth Thu Jul 19 09:32:44 2012 (r3081) +++ cpu/arm/mmp3/initmmu.fth Sun Jul 22 16:47:25 2012 (r3082) @@ -79,7 +79,7 @@ inc r0,#0x20000000 \ Next way - will wrap to 0 inc r0,#32 \ Next set - set r2,#0x1ffe0 \ Mask for set field for L2 cache - depends on #sets=4096 + set r2,`l2-#sets h# 20 - #` \ Mask for set field for L2 cache ands r1,r0,r2 \ Mask set bits 0= until @@ -229,6 +229,8 @@ mov r0,0 mov r1,0xd0000000 \ Memory controller base address +[ifdef] mmp3 + \ MMP3 memory controller ldr r2,[r1,#0x10] \ MMAP0 register ands r3,r2,#1 \ Test CS_VALID movne r3,#0x10000 \ Scale factor for memory size @@ -258,6 +260,22 @@ movne r2,r2,lsl #11 \ Clear high bits above AREA_LENGTH field movne r2,r2,lsr #27 \ Move AREA_LENGTH to LSB addne r0,r0,r3,lsl r2 \ Compute bank size and add to accumulator +[else] + \ MMP2 memory controller + ldr r2,[r1,#0x100] \ MMAP0 register + ands r3,r2,#1 \ Test CS_VALID + movne r3,#0x10000 \ Scale factor for memory size + movne r2,r2,lsl #12 \ Clear high bits above AREA_LENGTH field + movne r2,r2,lsr #28 \ Move AREA_LENGTH to LSB + addne r0,r0,r3,lsl r2 \ Compute bank size and add to accumulator + + ldr r2,[r1,#0x110] \ MMAP1 register + ands r3,r2,#1 \ Test CS_VALID + movne r3,#0x10000 \ Scale factor for memory size + movne r2,r2,lsl #12 \ Clear high bits above AREA_LENGTH field + movne r2,r2,lsr #28 \ Move AREA_LENGTH to LSB + addne r0,r0,r3,lsl r2 \ Compute bank size and add to accumulator +[then] mov pc,lr end-code Modified: cpu/arm/mmp3/resetvec.fth ============================================================================== --- cpu/arm/mmp3/resetvec.fth Thu Jul 19 09:32:44 2012 (r3081) +++ cpu/arm/mmp3/resetvec.fth Sun Jul 22 16:47:25 2012 (r3082) @@ -113,7 +113,7 @@ end-code \ Load some additional subroutines that are used by the startup code -fload ${BP}/cpu/arm/mmp3/initmmu.fth \ Setup the initial virtual address map +fload ${BP}/cpu/arm/mmp2/initmmu.fth \ Setup the initial virtual address map \ **** This is the main-line code for the initial startup sequence. \ It is reached from a branch instruction (which will be patched in later) Added: cpu/arm/mmp3/soc-config.fth ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ cpu/arm/mmp3/soc-config.fth Sun Jul 22 16:47:25 2012 (r3082) @@ -0,0 +1,2 @@ +create mmp3 +h# 20000 constant l2-#sets Modified: cpu/arm/mmp3/thunderstone/config.fth ============================================================================== --- cpu/arm/mmp3/thunderstone/config.fth Thu Jul 19 09:32:44 2012 (r3081) +++ cpu/arm/mmp3/thunderstone/config.fth Sun Jul 22 16:47:25 2012 (r3082) @@ -6,4 +6,4 @@ create machine-signature ," TS0" -h# 20000 constant l2-#sets +fload ${BP}/cpu/arm/mmp3/soc-config.fth Modified: cpu/arm/olpc/3.0/config.fth ============================================================================== --- cpu/arm/olpc/3.0/config.fth Thu Jul 19 09:32:44 2012 (r3081) +++ cpu/arm/olpc/3.0/config.fth Sun Jul 22 16:47:25 2012 (r3082) @@ -30,6 +30,6 @@ char 4 constant expected-ec-version h# 8000 value /ec-flash -h# 10000 constant l2-#sets +fload ${BP}/cpu/arm/mmp2/soc-config.fth fload ${BP}/cpu/arm/olpc/3.0/gpiopins.fth Modified: cpu/arm/olpc/cl4/config.fth ============================================================================== --- cpu/arm/olpc/cl4/config.fth Thu Jul 19 09:32:44 2012 (r3081) +++ cpu/arm/olpc/cl4/config.fth Sun Jul 22 16:47:25 2012 (r3082) @@ -27,6 +27,6 @@ char 5 constant expected-ec-version h# 10000 value /ec-flash -h# 20000 constant l2-#sets +fload ${BP}/cpu/arm/mmp3/soc-config.fth fload ${BP}/cpu/arm/olpc/cl4/gpiopins.fth Modified: cpu/arm/olpc/resetvec.fth ============================================================================== --- cpu/arm/olpc/resetvec.fth Thu Jul 19 09:32:44 2012 (r3081) +++ cpu/arm/olpc/resetvec.fth Sun Jul 22 16:47:25 2012 (r3082) @@ -113,7 +113,7 @@ end-code \ Load some additional subroutines that are used by the startup code -fload ${BP}/cpu/arm/olpc/initmmu.fth \ Setup the initial virtual address map +fload ${BP}/cpu/arm/mmp2/initmmu.fth \ Setup the initial virtual address map \ **** This is the main-line code for the initial startup sequence. \ It is reached from a branch instruction (which will be patched in later)

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[commit] r3081 - cpu/arm/olpc/cl4
by repository service July 19, 2012

July 19, 2012

Author: wmb Date: Thu Jul 19 09:32:44 2012 New Revision: 3081 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3081 Log: OLPC CL4 - commented-out fload line for not-yet-implemented driver. Modified: cpu/arm/olpc/cl4/fw.bth Modified: cpu/arm/olpc/cl4/fw.bth ============================================================================== --- cpu/arm/olpc/cl4/fw.bth Thu Jul 19 01:24:14 2012 (r3080) +++ cpu/arm/olpc/cl4/fw.bth Thu Jul 19 09:32:44 2012 (r3081) @@ -31,7 +31,7 @@ fload ${BP}/cpu/arm/olpc/1.75/lcdcfg.fth fload ${BP}/cpu/arm/olpc/1.75/usb.fth -fload ${BP}/cpu/arm/olpc/nn-touchscreen.fth +\ fload ${BP}/cpu/arm/olpc/nn-touchscreen.fth fload ${BP}/cpu/arm/olpc/cl4/switches.fth fload ${BP}/cpu/arm/olpc/cl4/leds.fth fload ${BP}/cpu/arm/olpc/cl4/testitems.fth

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