January 2017 - OpenBIOS - mail.coreboot.org

[PATCH] libopenbios/bootinfo_load.c: Implement Mac OS 9.2 boot script support
by Programmingkid Dec. 25, 2017

Dec. 25, 2017

This patch makes booting Mac OS 9.2 possible. It replaces all occurrences of >r and r> with sub_>r and sub_r>. This allows for the return stack to be left alone. This patch also makes it so that the boot script is executed one line at a time. Signed-off-by: John Arbuckle <programmingkidx(a)gmail.com> Note: this patch depends on the strstr() and return stack substitution patches. Index: libopenbios/bootinfo_load.c =================================================================== --- libopenbios/bootinfo_load.c (revision 1395) +++ libopenbios/bootinfo_load.c (working copy) @@ -19,6 +19,7 @@ #include "libopenbios/bootinfo_load.h" #include "libopenbios/ofmem.h" #include "libc/vsprintf.h" +#include "libc/string.h" //#define DEBUG_BOOTINFO @@ -116,6 +117,75 @@ return LOADER_NOT_SUPPORT; } +// Replace all occurrences of orig_str in buffer with replace_str +static void replace_string(char *buffer, const char *orig_str, const char *replace_str) +{ + char *ptr; + int index, new_buf_index = 0; + const int max_size = 5000; + char *new_buffer = malloc(max_size * sizeof(char)); + + for (index = 0; index < strlen(buffer); index++) { + if (buffer[index] == orig_str[0]) { + ptr = strstr(buffer + index, orig_str); + + // if we encountered an orig_str in the buffer + if (index == (ptr - buffer)) { + sprintf(new_buffer + new_buf_index, "%s ", replace_str); + new_buf_index += strlen(replace_str) + 1; + index += strlen(orig_str); + continue; + } + } + new_buffer[new_buf_index++] = buffer[index]; + } + + // copy new_buffer into buffer + for (index = 0; index < strlen(new_buffer); index++) { + buffer[index] = new_buffer[index]; + } + buffer[index+1] = '\0'; +} + +/* Replace >r and r> with sub_>r and sub_r> */ +static void replace_return_stack_words(char *bootscript) +{ + const char *find_str1 = ">r"; + const char *replace_str1 = "sub_>r"; + const char *find_str2 = "r>"; + const char *replace_str2 = "sub_r>"; + + replace_string(bootscript, find_str1, replace_str1); + replace_string(bootscript, find_str2, replace_str2); +} + +/* Runs the bootscript one line at a time */ +void run_script(char *bootscript) +{ + int index = 0, buf_index = 0; + char c; + char *buffer = malloc(1000 * sizeof(char)); + + while (1) { + c = bootscript[index]; + + // fill up buffer + while (c != '\n' && c != '\r' && c != '\0') { + buffer[buf_index++] = c; + c = bootscript[++index]; + } + buffer[buf_index] = '\0'; + buf_index = 0; + index++; + DPRINTF("%s\n", buffer); + feval(buffer); + if (c == '\0') { + break; + } + } + free(buffer); +} + /* Parse SGML structure like: <chrp-boot> @@ -209,9 +279,6 @@ script = 0; bootscript[scriptlen] = '\0'; - DPRINTF("got bootscript %s\n", - bootscript); - scriptvalid = -1; break; @@ -261,8 +328,8 @@ /* If the payload is bootinfo then we execute it immediately */ if (scriptvalid) { - DPRINTF("bootscript: %s\n", bootscript); - feval(bootscript); + replace_return_stack_words(bootscript); + run_script(bootscript); } else DPRINTF("Unable to parse bootinfo bootscript\n");

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[PATCH 3/4 v3] arch/ppc/qemu: Add a node for the other (empty) PCI bus to the device tree
by BALATON Zoltan Feb. 15, 2017

Feb. 15, 2017

QEMU emulates two of the three PCI buses found on real hardware because some clients seem to need both and fail with only one present, but OpenBIOS only handles a single PCI bus and initialises and puts in the device tree only one of these: the second one which is where devices are connected and also marks it bus 0. However, clients getting info from the device tree may not know about this and thinking there is only one PCI bus they erroneously use the address of the first bus to access PCI config registers for devices on the second bus which silently fails as these requests will go to the other empty bus emulated and return invalid values. Devices mapped via MMIO still appear to work but they may not be correctly initialised and some cards are not detected because of this. Until support for multiple PCI buses is implemented add an empty node in the device tree for the uninitialised bus to let clients know about it. This is still not entirely correct as bus-range property does not match real hardware but this fixes detecting PCI devices (such as USB) under MorphOS and may also fix enabling the bus master bit needed with some network cards and allow the workaround for this to be reverted. Signed-off-by: BALATON Zoltan <balaton(a)eik.bme.hu> --- arch/ppc/qemu/init.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) v3: Move device tree patching in its own function and call it from init (otherwise same as v2, take which you like) v2: Move to init.c from tree.fs and only add it for mac99 Patches 1 and 2 from original series https://www.coreboot.org/pipermail/openbios/2016-November/009825.html https://www.coreboot.org/pipermail/openbios/2016-November/009824.html are still valid and needed, patch 4 was already applied so only this one (3/4) is resent but 1 and 2 should be applied as well with this. diff --git a/arch/ppc/qemu/init.c b/arch/ppc/qemu/init.c index ffbf08d..46a56a0 100644 --- a/arch/ppc/qemu/init.c +++ b/arch/ppc/qemu/init.c @@ -668,6 +668,48 @@ static void kvm_of_init(void) fword("finish-device"); } +static void empty_pci_bus_init(void) +{ + if (machine_id == ARCH_MAC99) { + /* Add empty node for first pci bus */ + /* Remove this when pci driver is fixed to handle multiple buses */ + activate_device("/"); + fword("new-device"); + push_str("pci"); + fword("device-name"); + push_str("pci"); + fword("device-type"); + PUSH(0xf0000000); + fword("encode-int"); + PUSH(0x02000000); + fword("encode-int"); + fword("encode+"); + push_str("reg"); + fword("property"); + PUSH(3); + fword("encode-int"); + push_str("#address-cells"); + fword("property"); + PUSH(2); + fword("encode-int"); + push_str("#size-cells"); + fword("property"); + PUSH(1); + fword("encode-int"); + push_str("#interrupt-cells"); + fword("property"); + PUSH(0); + fword("encode-int"); + PUSH(0); + fword("encode-int"); + fword("encode+"); + push_str("bus-range"); + fword("property"); + fword("finish-device"); + device_end(); + } +} + /* * filll ( addr bytes quad -- ) */ @@ -755,6 +797,7 @@ arch_of_init(void) openbios_init(); modules_init(); setup_timers(); + empty_pci_bus_init(); #ifdef CONFIG_DRIVER_PCI ob_pci_init(); #endif -- 2.7.4

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Re: [OpenBIOS] Beginners How-To for DTS and OpenFirmware?
by Michael Feb. 13, 2017

Feb. 13, 2017

Hello Zoltan, hey list, On Mon, Nov 21, 2016 at 07:15:21PM +0100, BALATON Zoltan wrote: > ... > For forth commands I've found this page useful (not sure if this is linked > from somewhere): > http://www.firmworks.com/QuickRef.html Thank you, I found this (and more) last week. The OLPC sites are the best for me: 1: http://wiki.laptop.org/go/Open_Firmware 2: http://wiki.laptop.org/go/Forth_Lessons 3: http://wiki.laptop.org/go/Cross_Compiling_Open_Firmware > ... > This is a bit confusing. There are multiple implementations of the IEEE > standard (commonly referred to as Open Firmware) and one of these is also > called Open Firmware. These are listed under Implementations on the left of > the page at www.openfirmware.info. Another implementation used by QEMU for Yes and I looked at them. But they are either very old or not usable for ppc (too much work to implement a new arch). > ... > talking about Open Firmware: the standard or the implementation with the > same name. One thing is left which confuses me: In wikipedia and you say, that you use the name "Open Firmware" (also, besides as name for a standard) for an implementation. OK. But the website gives the impression (and G 3 says), that the implementation has the name "OpenBIOS"... So I have two statements which don't fit well. Please remember that I am new to this and did not live through the history. > ... > Actually running OpenBIOS on real hardware is not something that is well > tested (I'm not sure if it was ever tried but I think it wasn't done > recently) so if you try to do that be prepared for likely needing some The OLPC project did it, e.g. > fixing. This is true for any implementation that does not support the > hardware you want to run it on, then you likely need to port it. That there will be the need for porting was clear. > ... > it's enough to have the basics in there. Not sure how much up to date is > this but this is discussed in the kernel documentation here: > https://www.kernel.org/doc/Documentation/devicetree/booting-without-of.txt > Thank you, I missed this source. > As for giving the device tree to OpenBIOS I think it should just know it or > construct it from discovering the hardware as the point of the device tree > is to describe the hardware for the operating system so the firmware should > know the hardware and provide the device tree. It does not get it from The "firmware" is our handmade init-assemblercode. It has to enable the machine (beginning from Adam...) to run C-code in its RAM. If there is no software-interface, then we provide the device-tree maybe in forth or in a blob. Just thinking loudly. > ... > In fact OpenBIOS does not have that many drivers but maybe the basics are > there, only the platform specific init code might need to be adapted for a That would be very nice. We give it a try. Maybe with help from you / the list. > new board. For ppc these would be in arch/ppc. Running on QEMU is quite a > bit simpler as we can skip a lot of init code (such as memory controller or > other hardware) so maybe these are not well implemented or buggy as they > were not tested with real hardware for a while. > ... Did you use OpenBIOS in a recent qemu and have you been able to remote-debug it there? I was able to load and run the old OpenBIOS code (from svn repo) on "qemu-system-ppc". Thank you for your time and suggestions, greetings, Michael

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[PATCH 3/4 v2] arch/ppc/qemu: Add a node for the other (empty) PCI bus to the device tree
by BALATON Zoltan Jan. 27, 2017

Jan. 27, 2017

QEMU emulates two of the three PCI buses found on real hardware because some clients seem to need both and fail with only one present, but OpenBIOS only handles a single PCI bus and initialises and puts in the device tree only one of these: the second one which is where devices are connected and also marks it bus 0. However, clients getting info from the device tree may not know about this and thinking there is only one PCI bus they erroneously use the address of the first bus to access PCI config registers for devices on the second bus which silently fails as these requests will go to the other empty bus emulated and return invalid values. Devices mapped via MMIO still appear to work but they may not be correctly initialised and some cards are not detected because of this. Until support for multiple PCI buses is implemented add an empty node in the device tree for the uninitialised bus to let clients know about it. This is still not entirely correct as bus-range property does not match real hardware but this fixes detecting PCI devices (such as USB) under MorphOS and may also fix enabling the bus master bit needed with some network cards and allow the workaround for this to be reverted. Signed-off-by: BALATON Zoltan <balaton(a)eik.bme.hu> --- arch/ppc/qemu/init.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) v2: Move to init.c from tree.fs and only add it for mac99 Patches 1 and 2 from original series https://www.coreboot.org/pipermail/openbios/2016-November/009825.html https://www.coreboot.org/pipermail/openbios/2016-November/009824.html are still valid and needed, patch 4 was already applied so only this one (3/4) is resent but 1 and 2 should be applied as well with this. diff --git a/arch/ppc/qemu/init.c b/arch/ppc/qemu/init.c index ffbf08d..629d71b 100644 --- a/arch/ppc/qemu/init.c +++ b/arch/ppc/qemu/init.c @@ -755,6 +755,44 @@ arch_of_init(void) openbios_init(); modules_init(); setup_timers(); + if (machine_id == ARCH_MAC99) { + /* Add empty node for first pci bus */ + /* Remove this when pci driver is fixed to handle multiple buses */ + activate_device("/"); + fword("new-device"); + push_str("pci"); + fword("device-name"); + push_str("pci"); + fword("device-type"); + PUSH(0xf0000000); + fword("encode-int"); + PUSH(0x02000000); + fword("encode-int"); + fword("encode+"); + push_str("reg"); + fword("property"); + PUSH(3); + fword("encode-int"); + push_str("#address-cells"); + fword("property"); + PUSH(2); + fword("encode-int"); + push_str("#size-cells"); + fword("property"); + PUSH(1); + fword("encode-int"); + push_str("#interrupt-cells"); + fword("property"); + PUSH(0); + fword("encode-int"); + PUSH(0); + fword("encode-int"); + fword("encode+"); + push_str("bus-range"); + fword("property"); + fword("finish-device"); + device_end(); + } #ifdef CONFIG_DRIVER_PCI ob_pci_init(); #endif -- 2.7.4

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SPARC32 : SMP
by Olivier Danet Jan. 27, 2017

Jan. 27, 2017

I splitted the patch. It was tested with an old Linux distro (RH 4.2) and with NetBSD. The SMP kernel must be selected during install. Here is, for example, a NetBSD/sparc32 image with SMP enabled : temlib.org/pub/net702.qcow.bz2 qemu-system-sparc net702.qcow -M SS-20 -vga cg3 -smp 2 This SMP mode used to work a while ago, but it has so far no practical purpose as enabling it slows down QEMU considerably.

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ping: vga patch
by G 3 Jan. 13, 2017

Jan. 13, 2017

Hi, I was wondering if you could manage to look at my vga patch.

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[PATCH 2/2] SPARC32 : Fix SMP boot
by Olivier Danet Jan. 8, 2017

Jan. 8, 2017

Only the first CPU shall clear the RAM. Signed-off-by: Olivier Danet <odanet(a)caramail.com> --- arch/sparc32/entry.S | 31 ++++++++++++------------------- 1 file changed, 12 insertions(+), 19 deletions(-) diff --git a/arch/sparc32/entry.S b/arch/sparc32/entry.S index 7dc9fc8..74841c5 100644 --- a/arch/sparc32/entry.S +++ b/arch/sparc32/entry.S @@ -126,6 +126,17 @@ entry: or %g3, %g4, %g1 ! %g1 contains end of memory + ! Get CPU number + ! XXX: not all CPUs should have MXCC + set 0x1c00f00, %g2 + ldda [%g2] ASI_CONTROL, %g2 + srl %g3, 24, %g7 + subcc %g7, 8, %g7 + + ! Only the first CPU clears memory + bnz clear_done + nop + ! Get kernel address from configuration device ! NB: little endian format mov FW_CFG_KERNEL_ADDR, %g2 @@ -168,23 +179,6 @@ clear_done: set 0x2000, %g3 sub %g1, %g3, %g6 - ! Check if this is the boot CPU and skip SMP table check if yes - ! XXX: not all CPUs should have MXCC - set 0x1c00f00, %g2 - ldda [%g2] ASI_CONTROL, %g2 - srl %g3, 24, %g7 - sub %g7, 8, %g7 - tst %g7 - bz skip_table - nop - - ! Calculate SMP table location - set 0x1f0c, %g2 - add %g6, %g2, %g2 ! valid? - lda [%g2] ASI_M_BYPASS, %g7 - sta %g0, [%g2] ASI_M_BYPASS - -skip_table: ! Get machine ID from configuration device mov FW_CFG_MACHINE_ID, %g2 sub %g5, 2, %g5 @@ -217,14 +211,13 @@ ss10: ! Clear softints used for SMP CPU startup set PHYS_SS10_INTR0 + 0x04, %g1 - sll %g2, 12, %g2 + sll %g7, 12, %g2 add %g1, %g2, %g2 set 0xffffffff, %g1 sta %g1, [%g2] ASI_M_CTL ! clear softints add %g2, 4, %g2 sta %g0, [%g2] ASI_M_CTL ! clear softints -load_ctx: ! SMP init, jump to user specified address set 0x1f04, %g5 add %g6, %g5, %g5 ! ctxtbl -- 2.7.4

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[PATCH 1/2] SPARC32: Remove SMP detection for SS-5
by Olivier Danet Jan. 8, 2017

Jan. 8, 2017

SparcStation 5 can only use one CPU. Signed-off-by: Olivier Danet <odanet(a)caramail.com> --- arch/sparc32/entry.S | 36 ++++++++++++------------------------ 1 file changed, 12 insertions(+), 24 deletions(-) diff --git a/arch/sparc32/entry.S b/arch/sparc32/entry.S index 82aa88e..7dc9fc8 100644 --- a/arch/sparc32/entry.S +++ b/arch/sparc32/entry.S @@ -179,7 +179,7 @@ clear_done: nop ! Calculate SMP table location - set 0x1f0c, %g2 + set 0x1f0c, %g2 add %g6, %g2, %g2 ! valid? lda [%g2] ASI_M_BYPASS, %g7 sta %g0, [%g2] ASI_M_BYPASS @@ -205,36 +205,40 @@ skip_table: blu ss2 nop - ! Ok, this is SS-5 + ! Ok, this is SS-5, uniprocessor + ba first_cpu + nop +ss10: + ! Ok, this is SS-10/20 or SS-600MP tst %g7 bz first_cpu nop ! Clear softints used for SMP CPU startup - set PHYS_JJ_INTR0 + 0x04, %g1 + set PHYS_SS10_INTR0 + 0x04, %g1 sll %g2, 12, %g2 add %g1, %g2, %g2 set 0xffffffff, %g1 - sta %g1, [%g2] ASI_M_BYPASS ! clear softints + sta %g1, [%g2] ASI_M_CTL ! clear softints add %g2, 4, %g2 - sta %g0, [%g2] ASI_M_BYPASS ! clear softints + sta %g0, [%g2] ASI_M_CTL ! clear softints load_ctx: ! SMP init, jump to user specified address - set 0x1f04, %g5 + set 0x1f04, %g5 add %g6, %g5, %g5 ! ctxtbl lda [%g5] ASI_M_BYPASS, %g2 sta %g0, [%g5] ASI_M_BYPASS set AC_M_CTPR, %g1 sta %g2, [%g1] ASI_M_MMUREGS ! set ctx table ptr - set 0x1f00, %g5 + set 0x1f00, %g5 add %g6, %g5, %g5 ! ctx lda [%g5] ASI_M_BYPASS, %g2 sta %g0, [%g5] ASI_M_BYPASS set AC_M_CXR, %g1 sta %g2, [%g1] ASI_M_MMUREGS ! set context - set 0x1f08, %g5 + set 0x1f08, %g5 add %g6, %g5, %g5 ! entry lda [%g5] ASI_M_BYPASS, %g2 sta %g0, [%g5] ASI_M_BYPASS @@ -242,22 +246,6 @@ load_ctx: jmp %g2 ! jump to kernel sta %g1, [%g0] ASI_M_MMUREGS ! enable mmu -ss10: - ! Ok, this is SS-10 or SS-600MP - tst %g7 - bz first_cpu - nop - - ! Clear softints used for SMP CPU startup - set PHYS_SS10_INTR0 + 0x04, %g1 - sll %g2, 12, %g2 - add %g1, %g2, %g2 - set 0xffffffff, %g1 - sta %g1, [%g2] ASI_M_CTL ! clear softints - add %g2, 4, %g2 - b load_ctx - sta %g0, [%g2] ASI_M_CTL ! clear softints - ss2: ! Ok, this is SS-2 set ss2_error, %o2 -- 2.7.4

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[PATCH 3/4] arch/ppc/qemu: Add a node for the other (empty) PCI bus to the device tree
by BALATON Zoltan Jan. 2, 2017

Jan. 2, 2017

QEMU emulates two of the three PCI buses found on real hardware because some clients seem to need both and fail with only one present, but OpenBIOS only handles a single PCI bus and initialises and puts in the device tree only one of these: the second one which is where devices are connected and also marks it bus 0. However, clients getting info from the device tree may not know about this and thinking there is only one PCI bus they erroneously use the address of the first bus to access PCI config registers for devices on the second bus which silently fails as these requests will go to the other empty bus emulated and return invalid values. Devices mapped via MMIO still appear to work but they may not be correctly initialised and some cards are not detected because of this. Until support for multiple PCI buses is implemented add an empty node in the device tree for the uninitialised bus to let clients know about it. This is still not entirely correct as bus-range property does not match real hardware but this fixes detecting PCI devices (such as USB) under MorphOS and may also fix enabling the bus master bit needed with some network cards and allow the workarund for this to be reverted. Signed-off-by: BALATON Zoltan <balaton(a)eik.bme.hu> --- arch/ppc/qemu/tree.fs | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/ppc/qemu/tree.fs b/arch/ppc/qemu/tree.fs index 5b6bbc6..e1708de 100644 --- a/arch/ppc/qemu/tree.fs +++ b/arch/ppc/qemu/tree.fs @@ -50,6 +50,18 @@ new-device h# ff800000 encode-int encode+ " ranges" property finish-device +\ Add empty node for first pci bus +\ Remove this when pci driver is fixed to handle multiple buses +new-device + " pci" device-name + " pci" device-type + h# f0000000 encode-int 02000000 encode-int encode+ " reg" property + 3 encode-int " #address-cells" property + 2 encode-int " #size-cells" property + 1 encode-int " #interrupt-cells" property + 0 encode-int 0 encode-int encode+ " bus-range" property +finish-device + \ ------------------------------------------------------------- \ /packages \ ------------------------------------------------------------- -- 2.7.4

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The tilda character in OpenBIOS
by Programmingkid Jan. 2, 2017

Jan. 2, 2017

When I push the tilda/grave-accent button, the character that shows up on OpenBIOS is the < or > character. Would you accept a patch that fixes this issue?

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