July 2014 - OpenBIOS - mail.coreboot.org

Running client with MMU off
by BALATON Zoltan Aug. 5, 2014

Aug. 5, 2014

I'm trying to solve the last bigger outstanding problem for MorphOS to run with OpenBIOS. This is that it modifies exception vectors without first turning the MMU off (probably expecting it to be off as happens on real hardware). OpenBIOS on the other hand turns the MMU on and needs this for client interface calls to work so calling the client boot code with MMU off results in a hang. There is disabled code in the quiesce method to clear the MMU bits but this is not sufficient/correct because MorphOS continues to call client interface callbacks after calling quiesce. Thus I was trying to save MSR, turn MMU on then restore MSR on client callbacks with the patch below but it does not work and leads to writes to wrong addresses and a crash on restore. (Probably the stack location is wrong after the patch?) Can anyone tell why it's not working and what could be done instead? Regards, BALATON Zoltan diff --git a/openbios-devel/arch/ppc/qemu/start.S b/openbios-devel/arch/ppc/qemu index ae2fd53..384a8a6 100644 --- a/openbios-devel/arch/ppc/qemu/start.S +++ b/openbios-devel/arch/ppc/qemu/start.S @@ -515,13 +515,13 @@ _GLOBAL(call_elf): LOAD_REG_IMMEDIATE(r5, of_client_callback) // r5 = callback li r6,0 // r6 = address of client program argume li r7,0 // r7 = length of client program argumen - li r0,MSR_FP | MSR_ME | MSR_DR | MSR_IR + li r0,MSR_FP | MSR_ME MTMSRD(r0) blrl #ifdef CONFIG_PPC64 /* Restore SF bit */ - LOAD_REG_IMMEDIATE(r0, MSR_SF | MSR_FP | MSR_ME | MSR_DR | MSR_IR) + LOAD_REG_IMMEDIATE(r0, MSR_SF | MSR_FP | MSR_ME) MTMSRD(r0) #endif LOAD_REG_IMMEDIATE(r8, saved_stack) // restore stack pointer @@ -535,10 +535,10 @@ _GLOBAL(call_elf): #ifdef __powerpc64__ #define STKOFF STACKFRAME_MINSIZE -#define SAVE_SPACE 320 +#define SAVE_SPACE 328 #else #define STKOFF 8 -#define SAVE_SPACE 144 +#define SAVE_SPACE 148 #endif GLOBL(of_client_callback): @@ -607,6 +607,10 @@ GLOBL(of_client_callback): PPC_STL r29, (STKOFF + 30 * ULONG_SIZE)(r1) PPC_STL r30, (STKOFF + 31 * ULONG_SIZE)(r1) PPC_STL r31, (STKOFF + 32 * ULONG_SIZE)(r1) + mfmsr r2 + PPC_STL r2, (STKOFF + 33 * ULONG_SIZE)(r1) + ori r2, r2, (MSR_DR | MSR_IR) + mtmsr r2 #ifdef CONFIG_PPC64 LOAD_REG_IMMEDIATE(r2, of_client_interface) @@ -643,6 +647,8 @@ GLOBL(of_client_callback): PPC_LL r29, (STKOFF + 30 * ULONG_SIZE)(r1) PPC_LL r30, (STKOFF + 31 * ULONG_SIZE)(r1) PPC_LL r31, (STKOFF + 32 * ULONG_SIZE)(r1) + PPC_LL r2, (STKOFF + 33 * ULONG_SIZE)(r1) + mtmsr r2 /* restore ctr, cr and xer */ This results in: Unassigned mem write 00000000100fff6c = 0x0 Unassigned mem write 00000000100fff74 = 0xfde7e90 Unassigned mem write 00000000100fff78 = 0x0 Unassigned mem write 00000000100fff7c = 0x4311d0 Unassigned mem write 00000000100fff80 = 0x0 Unassigned mem write 00000000100fff84 = 0x22000042 Unassigned mem write 00000000100fff88 = 0x20000000 Unassigned mem write 00000000100fff8c = 0x0 Unassigned mem write 00000000100fff90 = 0x8 Unassigned mem write 00000000100fff94 = 0x2 Unassigned mem write 00000000100fff98 = 0x0 Unassigned mem write 00000000100fff9c = 0x680000 Unassigned mem write 00000000100fffa0 = 0xfde7f98 Unassigned mem write 00000000100fffa4 = 0xfdf7e70 Unassigned mem write 00000000100fffa8 = 0x22000042 Unassigned mem write 00000000100fffac = 0x0 Unassigned mem write 00000000100fffb0 = 0xfff32687 Unassigned mem write 00000000100fffb4 = 0xfde7f60 Unassigned mem write 00000000100fffb8 = 0xfde7f20 Unassigned mem write 00000000100fffbc = 0x0 Unassigned mem write 00000000100fffc0 = 0xfffb0000 Unassigned mem write 00000000100fffc4 = 0x688000 Unassigned mem write 00000000100fffc8 = 0x3000 Unassigned mem write 00000000100fffcc = 0xfffb601c Unassigned mem write 00000000100fffd0 = 0x0 Unassigned mem write 00000000100fffd4 = 0xfffb601c Unassigned mem write 00000000100fffd8 = 0xfffb0000 Unassigned mem write 00000000100fffdc = 0x0 Unassigned mem write 00000000100fffe0 = 0xfff02620 Unassigned mem write 00000000100fffe4 = 0xfde7f60 Unassigned mem write 00000000100fffe8 = 0xfde7f20 Unassigned mem write 00000000100fffec = 0x688000 Unassigned mem write 00000000100ffff0 = 0xfffb0000 Unassigned mem write 00000000100ffff4 = 0x67bd80 Unassigned mem write 00000000100ffff8 = 0x3000 Unassigned mem read 0000000060000000 qemu: fatal: Trying to execute code outside RAM or ROM at 0x60000000 NIP 60000000 LR 60000000 CTR 00000000 XER 00000000 MSR 00000000 HID0 00000000 HF 00000000 idx 1 TB 00000000 836520711 DECR 3458446955 GPR00 0000000000000000 0000000060000000 0000000000000000 0000000000000000 GPR04 000000004bfffffc 0000000000000000 0000000000000000 0000000000000000 GPR08 0000000000000000 0000000000000000 0000000000000000 0000000000000000 GPR12 0000000000000000 0000000000000000 0000000000000000 0000000000000000 GPR16 0000000000000000 0000000000000000 0000000000000000 0000000000000000 GPR20 0000000000000000 0000000000000000 0000000000000000 0000000000000000 GPR24 0000000000000000 0000000000000000 0000000000000000 0000000000000000 GPR28 0000000000000000 0000000000000000 0000000000000000 0000000000000000 CR 00000000 [ - - - - - - - - ] RES ffffffff FPR00 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR04 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR08 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR12 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR16 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR20 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR24 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR28 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPSCR 00000000 SRR0 fff0db1c SRR1 00003030 PVR 000c0209 VRSAVE 00000000 SPRG0 0fe00000 SPRG1 ffffff6c SPRG2 22000042 SPRG3 00000000 SPRG4 00000000 SPRG5 00000000 SPRG6 00000000 SPRG7 00000000 SDR1 0fe00000 DAR ffffff3c DSISR 42000000 end of dissassembly before the error: 0xfff02750: lwz r31,136(r1) 0xfff02754: lwz r2,140(r1) 0xfff02758: mtmsr r2 IN: 0xfff0275c: lwz r2,20(r1) 0xfff02760: mtctr r2 0xfff02764: lwz r2,24(r1) 0xfff02768: mtcr r2 0xfff0276c: lwz r2,28(r1) 0xfff02770: mtxer r2 0xfff02774: lwz r2,12(r1) 0xfff02778: lwz r0,16(r1) 0xfff0277c: lwz r1,8(r1) 0xfff02780: lwz r4,4(r1) 0xfff02784: mtlr r4 0xfff02788: lwz r4,8(r1) 0xfff0278c: lwz r1,0(r1) 0xfff02790: blr qemu: fatal: Trying to execute code outside RAM or ROM at 0x60000000

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Re: [OpenBIOS] [PATCH 6/6] SPARC64: add model to hwdefs array and set it to a suitable value
by Mark Cave-Ayland Aug. 4, 2014

Aug. 4, 2014

On 28/07/14 15:33, Artyom Tarasenko wrote: > On Sun, Jul 27, 2014 at 10:44 PM, Mark Cave-Ayland > <mark.cave-ayland(a)ilande.co.uk> wrote: >> At the moment we are probably closest to an Ultra250 with an UltraSPARC-IIi >> processor and PCI bus. > > Are we? I thought QEMU was targeting Ultra-5. Both Ultra-5 and > Enterpise-250 have different serial ports, but Enterprise-250 may have > multiple CPUs, whereas QEMU can't. Yeah, it was something to do with the serial ports, although I suspect given the hacking over the past weekend that Ultra5 is probably still valid now. >> This property is checked by NetBSD during boot. > > Does it have to be something existing? Since QEMU doesn't exactly > match any real machine, I'd prefer something like "QEMU,sun4u", but > maybe it's personal. I'm not exactly sure? But sure, at the very least we should have something there to prevent errors on the console during boot. ATB, Mark.

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[PATCH 0/6] Further *BSD SPARC64 fixes
by Mark Cave-Ayland July 28, 2014

July 28, 2014

This is my current patch series for getting the various *BSDs to boot under QEMU SPARC64. NetBSD, in comparison to Linux, will stricly parse the device tree in order to ascertain information such as addresses and interrupt mappings and for devices, and so proves to be a very useful test harness for ensuring that the device tree is consistent. With a minor patch applied to QEMU git, NetBSD will now boot all the way through to IDE detection; OpenBSD is still unchanged from my last patchset due to a missing interrupt property which I can't yet locate, and FreeBSD will now finally start to boot but fails during psycho detection due to an (undocumented?) TSR register not being initialised by OpenBIOS. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland(a)ilande.co.uk> Mark Cave-Ayland (6): pci.c: add generation of pci node available property pc_serial.c: move address initialisation to a separate init word pc_serial.c: don't add address property to SPARC64 serial ports SPARC64: build ebus ranges property from PCI BARs SPARC64: switch to using interrupt-map property for interrupt pins SPARC64: add model to hwdefs array and set it to a suitable value openbios-devel/arch/sparc64/openbios.c | 17 +++++- openbios-devel/drivers/pc_serial.c | 23 ++++---- openbios-devel/drivers/pci.c | 101 ++++++++++++++++++++++++-------- 3 files changed, 105 insertions(+), 36 deletions(-) -- 1.7.10.4

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[commit] r1307 - in trunk/openbios-devel: drivers include/arch/common
by repository service July 13, 2014

July 13, 2014

Author: agraf Date: Sun Jul 13 18:19:50 2014 New Revision: 1307 URL: http://tracker.coreboot.org/trac/openbios/changeset/1307 Log: Mac99: Support flat NVRAM The mac99 machine is switching to use a flat NVRAM layout. Support that hint and treat NVRAM as flat when we find it. We keep the old (broken) shifted-by-1 way of accessing NVRAM around to be able to use new OpenBIOS binaries on older QEMU versions. Signed-off-by: Alexander Graf <agraf(a)suse.de> Modified: trunk/openbios-devel/drivers/macio.c trunk/openbios-devel/include/arch/common/fw_cfg.h Modified: trunk/openbios-devel/drivers/macio.c ============================================================================== --- trunk/openbios-devel/drivers/macio.c Fri May 30 14:11:44 2014 (r1306) +++ trunk/openbios-devel/drivers/macio.c Sun Jul 13 18:19:50 2014 (r1307) @@ -27,20 +27,31 @@ #define NW_IO_NVRAM_SIZE 0x00004000 #define NW_IO_NVRAM_OFFSET 0xfff04000 -#define NW_IO_NVRAM_SHIFT 1 #define IO_OPENPIC_SIZE 0x00040000 #define IO_OPENPIC_OFFSET 0x00040000 static char *nvram; +static int macio_nvram_shift(void) +{ + int nvram_flat; + + if (is_oldworld()) + return OW_IO_NVRAM_SHIFT; + + nvram_flat = fw_cfg_read_i32(FW_CFG_PPC_NVRAM_FLAT); + return nvram_flat ? 0 : 1; +} + int macio_get_nvram_size(void) { + int shift = macio_nvram_shift(); if (is_oldworld()) - return OW_IO_NVRAM_SIZE >> OW_IO_NVRAM_SHIFT; + return OW_IO_NVRAM_SIZE >> shift; else - return NW_IO_NVRAM_SIZE >> NW_IO_NVRAM_SHIFT; + return NW_IO_NVRAM_SIZE >> shift; } static unsigned long macio_nvram_offset(void) @@ -123,12 +134,7 @@ macio_nvram_put(char *buf) { int i; - unsigned int it_shift; - - if (is_oldworld()) - it_shift = OW_IO_NVRAM_SHIFT; - else - it_shift = NW_IO_NVRAM_SHIFT; + unsigned int it_shift = macio_nvram_shift(); for (i=0; i< arch_nvram_size() ; i++) nvram[i << it_shift] = buf[i]; @@ -142,12 +148,7 @@ macio_nvram_get(char *buf) { int i; - unsigned int it_shift; - - if (is_oldworld()) - it_shift = OW_IO_NVRAM_SHIFT; - else - it_shift = NW_IO_NVRAM_SHIFT; + unsigned int it_shift = macio_nvram_shift(); for (i=0; i< arch_nvram_size(); i++) buf[i] = nvram[i << it_shift]; Modified: trunk/openbios-devel/include/arch/common/fw_cfg.h ============================================================================== --- trunk/openbios-devel/include/arch/common/fw_cfg.h Fri May 30 14:11:44 2014 (r1306) +++ trunk/openbios-devel/include/arch/common/fw_cfg.h Sun Jul 13 18:19:50 2014 (r1307) @@ -46,6 +46,7 @@ #define FW_CFG_PPC_KVM_PID (FW_CFG_ARCH_LOCAL + 0x07) #define FW_CFG_PPC_NVRAM_ADDR (FW_CFG_ARCH_LOCAL + 0x08) #define FW_CFG_PPC_BUSFREQ (FW_CFG_ARCH_LOCAL + 0x09) +#define FW_CFG_PPC_NVRAM_FLAT (FW_CFG_ARCH_LOCAL + 0x0a) #define FW_CFG_INVALID 0xffff

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