March 2000 - OpenBIOS - mail.coreboot.org

OT: linux kernel problem
by Edwin Rhodes July 16, 2000

July 16, 2000

when compiling my linux kernel i keep on recieving this message: Warning: Clock Skew Detected Build May Be Incomplete It seams to compile ok. What does this error message mean?? and how can i fix it. thanks edwin ps. I have only been getting this message since i upgraded to an AMD K6-2 500Mhz.

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sorry to ask this again
by Ronald G. Minnich April 4, 2000

April 4, 2000

If someone has the *code* example for calling the vga init on a vga card I could use it. ron - To unsubscribe: send mail to majordomo(a)freiburg.linux.de with 'unsubscribe openbios' in the body of the message

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Fixed part of it
by Ronald G. Minnich March 30, 2000

March 30, 2000

OK, I've added simple pcibus_fixup_mem_addr code to 2.2.10, so that memory BARs get set up correctly. As for this discussion of interrupt mapping: a quick look at any motherboard spec will show you how trivial the mapping of four interrupt lines for 4 or 5 PCI slots is. There's only so many permutations you can do, and most motherboards do them the same. There aren't that many motherboards out there. Do the math. It's a very small table, and if we really ever want hot swap, we'll need it anyway. So why not just do it now? ron - To unsubscribe: send mail to majordomo(a)freiburg.linux.de with 'unsubscribe openbios' in the body of the message

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Re: [OpenBIOS] PCI setup code
by Ronald G. Minnich March 30, 2000

March 30, 2000

On Mon, 27 Mar 2000, Jeff Garzik wrote: > What problems exactly are you having in PCI setup? I've been messing > around in that area lately and can help... first, in 2.2.10, it doesn't do ANY configuration of memory-addressable BARs. Second, it doesn't do any IRQ assignment. If 2.3 fixes this then I'll just cut over. ron - To unsubscribe: send mail to majordomo(a)freiburg.linux.de with 'unsubscribe openbios' in the body of the message

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RE: [OpenBIOS] PCI setup code
by Marcus Gossner March 30, 2000

March 30, 2000

Jeff wrote: >Colin Jensen wrote: >> You can't seriously suggest that the operating system should be able to detect >> the motherboard type automatically! While in *your* application, you could >> hard code the motherboard setups into Linux, this is generally Not A Solution. > >Not motherboard type. Motherboard chipset type. > Detect only the chipset type will not solve the problem. The wireing from the chipset to the PCI Slots ist the interessting thing. > >> Marcus put it best: "IRQ assignment can't be done in the operating system". And >> this is for a simple reason: operating systems generally can't be hard-coded to >> a particular motherboard. And THERE IS NO WAY to automatically detect a >> motherboard type. NONE. NADA. CAN'T GO THERE. The BIOS, since it is going to >> be *glued* to the motherboard, is a much more reasonable choice for hard >> coding... > >You CAN detect a motherboard type, by grepping strings out of the BIOS >ROM. But that is not the point here. The motherboard CHIPSET type is >easily detected, generally by a simple PCI vendor/device id match. > >WRT IRQ assignment, Marcus is wrong. In a hotplug system, the OS _must_ >do the assignment. Even Microsoft knows this[1]. That is why most >modern BIOS ROMs come with interrupt routing tables, which give the OS a >[somewhat] standard method for > I think you should not do the assignment in the OS but you can do a reconfiguration there. All are talking about Linux but I like to use poor old DOS and WinNT 4 and other OS and I don't linke to write a device driver for PCI configuration for each OS. I agree, that the OS can change the settings made by the BIOS. I don't understand the problem. If you like you can clear all PCI registers and set up them again in the OS, but there should be done something for all OS that can't do the configuration. And one other thing: When the Linux code is the best in the world, why not put it into the BIOS? > >This is also why newer motherboards include a Windows' "IRQ driver" or >similar -- so the --OS-- can talk to your motherboard. > > Jeff Marcus - To unsubscribe: send mail to majordomo(a)freiburg.linux.de with 'unsubscribe openbios' in the body of the message

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PCI setup
by Ronald G. Minnich March 29, 2000

March 29, 2000

much improved in 2.3, so I am moving linuxbios to 2.3.45 ron - To unsubscribe: send mail to majordomo(a)freiburg.linux.de with 'unsubscribe openbios' in the body of the message

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linuxbios performance
by Ronald G. Minnich March 29, 2000

March 29, 2000

just enabling mtrr's and then setting up one mtrr as per the VOL III manual makes things fast. Boy, am I ever happier. ron - To unsubscribe: send mail to majordomo(a)freiburg.linux.de with 'unsubscribe openbios' in the body of the message

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RE: [OpenBIOS] PCI setup code
by Marcus Gossner March 29, 2000

March 29, 2000

Ronald G. Minnich wrote: > >> What problems exactly are you having in PCI setup? I've been messing >> around in that area lately and can help... > > >first, in 2.2.10, it doesn't do ANY configuration of memory-addressable >BARs. Second, it doesn't do any IRQ assignment. If 2.3 fixes this then >I'll just cut over. > >ron The IRQ assignment can't be done in the operating system. It depends on the wireing on your board and therefore it is done in BIOS. You can check the IRQ assignment with your original BIOS: 1. Select fixed ISA IRQs for PCI IRQs e.g. PCI INTA = IRQ 9 PCI INTB = IRQ 10 PCI INTC = IRQ 11 PCI INTD = IRQ 12 2. Put PCI cards in all slots 3. Boot something and look into PCI configuration space If for example the card in PCI Slot 1 got IRQ 11 you know now this Slot uses PCI INTC. Please remember to set up your chipset correctly to select with PCI IRQ use with ISA IRQ. Then you can assign this IRQs to your PCI Slots. Marcus - To unsubscribe: send mail to majordomo(a)freiburg.linux.de with 'unsubscribe openbios' in the body of the message

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Re: [OpenBIOS] PCI setup code
by James March 28, 2000

March 28, 2000

> > If anyone could repost the links to PCI support code I would appreciate > > it. Linux PCI_DIRECT is not up to snuff at present. > > Have you looked at 2.3.x? It is MUCH more up to date. > > What problems exactly are you having in PCI setup? I've been messing > around in that area lately and can help... Hey Jeff, I'll be here at the ACL for a week. Below is what we get on bootup. NOTES: Calibrating delay loop... 4.25 BogoMIPS Cache isn't enabled correctly, so the chip runs at ~ 1/100 its speed. Sigh. This makes gunzipping slow. PCI: 00:60 [9005/005f], irq 0x0 This is the SCSI controller, hence this line is repeated. Note how all the IRQs are 0x0. Continue down the printout and note how all the mbases are 00000000 when the cards initialize. I am going to try to make code to assign IRQs; I don't really know where to start; I take it PCI devices each get an IRQ of 9, 10, 11, 12, 14, or 15, and they can share? Ron says he knows how to fix the mbases problem. Any comments/suggestions would be greatly appreciated (no, I do not know what I am doing). - James >>>>>> Contents of 0018:C01DD140 (we don't have video yet) Linux version 2.2.10 (rminnich@mini) (gcc version egcs-2.91.66 19990314/Linux (egcs-1.1.2 release)) #13 Mon Mar 27 12:43:40 MST 2000. Detected 497449471 Hz processor.. Calibrating delay loop... 4.25 BogoMIPS. Memory: 309004k/313472k available (752k kernel code, 412k reserved, 3276k data, 28k init). Pentium-III serial number disabled.. CPU: Intel 00/07 stepping 03. Checking 386/387 coupling... OK, FPU using exception 16 error reporting.. Checking 'hlt' instruction... OK.. POSIX conformance testing by UNIFIX. mtrr: v1.35 (19990512) Richard Gooch (rgooch(a)atnf.csiro.au) PCI: Using configuration type 1. PCI: Probing PCI hardware. pci_scan_bus for bus 0. pci_scan_bus: bus 0, max is 0. irq is 0x0. base 0, val 0x8. base 1, val 0x0. base 2, val 0x0. base 3, val 0x0. base 4, val 0x0. base 5, val 0x0. PCI: 00:00 [8086/71a0],irq 0x0. base 0, val 0x0. base 1, val 0x0. PCI: 00:08 [8086/71a1],irq 0x0. irq is 0x0. base 0, val 0x1. base 1, val 0x4. base 3, val 0x0. base 4, val 0x0. base 5, val 0x0. PCI: 00:60 [9005/005f],irq 0x0. irq is 0x0. base 0, val 0x1. base 1, val 0x4. base 3, val 0x0. base 4, val 0x0. base 5, val 0x0. PCI: 00:61 [9005/005f],irq 0x0. irq is 0x0. base 0, val 0x0. base 1, val 0x1. base 2, val 0x0. base 3, val 0x0. base 4, val 0x0. base 5, val 0x0. PCI: 00:70 [8086/1229],irq 0x0. irq is 0x0. base 0, val 0x0. base 1, val 0x0. base 2, val 0x0. base 3, val 0x0. base 4, val 0x0. base 5, val 0x0. PCI: 00:90 [8086/7110],irq 0x0. irq is 0x0. base 0, val 0x0. base 1, val 0x0. base 2, val 0x0. base 3, val 0x0. base 4, val 0x1. base 5, val 0x0. PCI: 00:91 [8086/7111],irq 0x0. irq is 0x0. base 0, val 0x0. base 1, val 0x0. base 2, val 0x0. base 3, val 0x0. base 4, val 0x1. base 5, val 0x0. PCI: 00:92 [8086/7112],irq 0x0. irq is 0x0. base 0, val 0x0. base 1, val 0x0. base 2, val 0x0. base 3, val 0x0. base 4, val 0x0. base 5, val 0x0. PCI: 00:93 [8086/7113],irq 0x0. irq is 0x0. base 0, val 0x8. base 1, val 0x0. base 2, val 0x0. base 3, val 0x0. base 4, val 0x0. base 5, val 0x0. PCI: 00:a0 [1013/00bc],irq 0x0. pci_scan_bus for bus 1. pci_scan_bus: bus 1, max is 1. base 0, val 0x0. base 1, val 0x0. PCI: 01:78 [1011/0023],irq 0x0. pci_scan_bus for bus 2. pci_scan_bus: bus 2, max is 2. PCI: pci_scan_bus returning with max=02. PCI: pci_scan_bus returning with max=02. PCI: pci_scan_bus returning with max=02. PCI: Assigning I/O space 5800-58ff to device 00:60. PCI: Enabling I/O for device 00:60. PCI: Assigning I/O space 5900-59ff to device 00:61. PCI: Enabling I/O for device 00:61. PCI: Assigning I/O space 5a00-5a3f to device 00:70. PCI: Enabling I/O for device 00:70. PCI: Assigning I/O space 5a40-5a4f to device 00:91. PCI: Assigning I/O space 5a60-5a7f to device 00:92. PCI: Enabling I/O for device 00:92. Linux NET4.0 for Linux 2.2. Based upon Swansea University Computer Society NET3.039. NET4: Unix domain sockets 1.0 for Linux NET4.0.. NET4: Linux TCP/IP 1.0 for NET4.0. IP Protocols: ICMP, UDP, TCP. Starting kswapd v 1.5 . Serial driver version 4.27 with no serial options enabled. Floppy drive(s): fd0 is 1.44M. floppy0: no floppy controllers found. Found an aci. pdev shows irq at 0x0. aic7xxx: <Adaptec AIC-7896/7 Ultra2 SCSI host adapter> at PCI 12/0. aci7xxx: base 00005800, mbase 00000000, irq 0x0. aic7xxx: Controller disabled by BIOS, ignoring.. Found an aci. pdev shows irq at 0x0. aic7xxx: <Adaptec AIC-7896/7 Ultra2 SCSI host adapter> at PCI 12/1. aci7xxx: base 00005900, mbase 00000000, irq 0x0. aic7xxx: Controller disabled by BIOS, ignoring.. scsi : 0 hosts.. scsi : detected total.. The PCI BIOS has not enabled this device! Updating PCI command 0001->0005.. PCI latency timer (CFLT) is unreasonably low at 0. Setting to 32 clocks.. eth0: Intel EtherExpress Pro 10/100 at 0x5a00, 00:90:27:E0:34:A2, IRQ 0.. Receiver lock-up bug exists -- enabling work-around.. Board assembly 000000-000, Physical connectors present: RJ45. Primary interface chip i82555 PHY #1.. General self-test: passed.. Serial sub-system self-test: passed.. Internal registers self-test: passed.. ROM checksum self-test: passed (0x04f4518b).. VFS: Cannot open root device 08:01....... - To unsubscribe: send mail to majordomo(a)freiburg.linux.de with 'unsubscribe openbios' in the body of the message

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PCI setup code
by Ronald G. Minnich March 27, 2000

March 27, 2000

If anyone could repost the links to PCI support code I would appreciate it. Linux PCI_DIRECT is not up to snuff at present. ron - To unsubscribe: send mail to majordomo(a)freiburg.linux.de with 'unsubscribe openbios' in the body of the message

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