April 2018 - flashrom - mail.coreboot.org

Re: [flashrom] New SPI NOR Flash product Support
by Stefan Tauner Aug. 15, 2019

Aug. 15, 2019

On Mon, 9 May 2016 20:46:18 -0700 David Hendricks <dhendrix(a)google.com> wrote: > Hi Victor, > From Flashrom's software perspective all chips with the same ID are > indistinguishable. > > Part number often includes characteristics such as package and thermal > tolerance which do not affect software compatibility. However, we will add the new names to the in-program (and hence wiki) database so that this new information becomes public. Thanks for the heads up, Victor. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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80/100/132 column line width policy
by Carl-Daniel Hailfinger Dec. 14, 2018

Dec. 14, 2018

Hi, we're hitting the 80 column limit in our code in ways which actually reduce readability for the code. Examples are various multiline messages and complicated nested code where refactoring to a separate function doesn't make sense. Keeping the old 80 column limit is not really an option anymore. Standard terminal sizes have one of 80, 100 or 132 columns. Given the monitor resolutions many people have nowadays, I think it is safe to say that you can fit two xterms with 100 columns horizonally next to each other. 100 columns should also be sufficient for a msg_p* of roughly 80 columns of text. 132 columns provide more leeway, but IMHO that would be too wide for good readability (and my screen can't fit two xterms side-by-side anymore). Of course some files have sections where any column limit is not acceptable (board lists etc.), but the column limit violations should be limited to the affected file sections, not whole files. Comments? I'd like to get this decided today or tomorrow so we know where we need line breaks in Stefan Tauner's new struct flashchip patch. Regards, Carl-Daniel -- http://www.hailfinger.org/

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FOSDEM Hardware Enablement Devroom
by Paul Kocialkowski Dec. 4, 2018

Dec. 4, 2018

A Hardware Enablement devroom will be taking place at FOSDEM this year, on Sunday 10 December 2017. This newly-created devroom is the result of 3 proposals that were merged together. It is co-organized by several individuals. The devroom covers all aspects related to hardware enablement and support with free software, including aspects related to boot software, firmwares, drivers and userspace tools and adaptation. Proposals for talks related to these topics are welcome and can be submitted until Sunday 26 November 2017 via the pentabarf interface. Short talks are encouraged over longer ones in order to cover a wide range of topics. The announcement for the devroom, that contains all the useful information, was published at: https://lists.fosdem.org/pipermail/fosdem/2017-October/002649.html Cheers and see you at FOSDEM! -- Paul Kocialkowski, developer of free digital technology and hardware support Website: https://www.paulk.fr/ Coding blog: https://code.paulk.fr/ Git repositories: https://git.paulk.fr/ https://git.code.paulk.fr/

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Re: [flashrom] FAILED: Soraka DVT1
by David Hendricks April 26, 2018

April 26, 2018

Hello Hongxia, Were you able to get in touch with someone on the chromiumos team? It appears that you attempted to write the entire firmware ROM, but it failed to write the flash descriptor region. You should target the region(s) you want updated using the -i option, along with --fast-verify, so that flashrom does not attempt to write and verify regions that it might not have access to. On Mon, Apr 23, 2018 at 11:54 PM, Gao, HongxiaX <hongxiax.gao(a)intel.com> wrote: > Hi, > > > > It is failed on my board when flashing firmware R68 10599. Can you help me > on it? > > > > *HW:* Soraka DVT1 > > > > *Issue description:* > > Flash firmware 10431 without any problems, but it is failed when flashing > firmware R68 10599. Steps are: > > > > 1. Download firmware R68 10599 > <https://www.google.com/chromeos/partner/fe/#download:event=IMAGE_DOWNLOAD&u…>, > then extract it. > > 2. Enter board terminal > > localhost /home # flashrom -w 10599/image.bin > > flashrom v0.9.9 : cfd7dfc : Apr 06 2018 05:12:10 UTC on Linux 4.4.128 > (x86_64) > > flashrom v0.9.9 : cfd7dfc : Apr 06 2018 05:12:10 UTC on Linux 4.4.128 > (x86_64) > > Calibrating delay loop... OK. > > coreboot table found at 0x7aac5000. > > WARNING: SPI Configuration Lockdown activated. > > Erasing and writing flash chip... Verifying flash... VERIFY FAILED at > 0x00000081! Expected=0xff, Read=0x0b, failed byte count from > 0x00000000-0x00ffffff: 0x9 > > Your flash chip is in an unknown state. > > Get help on IRC at irc.freenode.net (channel #flashrom) or > > mail flashrom(a)flashrom.org with FAILED: your board name in the subject > line! > > ------------------------------------------------------------ > ------------------- > > DO NOT REBOOT OR POWEROFF! > > FAILED > > > > 3. Try to update firmware > > localhost /home/10599 # chromeos-firmwareupdate -m autoupdate > > Starting Google_Soraka firmware updater v4 (autoupdate)... > > - Updater package: [Google_Soraka.10431.32.0 / > EC:soraka_v1.1.8047-2c5917d7d] > > - Current system: [RO:Google_Soraka.10431.32.0 , > ACT:Google_Soraka.10431.32.0 / EC:soraka_v1.1.8047-2c5917d7d] > > - Write protection: Hardware: ON, Software: Main=off > > * invoke: flashrom -p host -r _current/bios.bin > > RO Contents are different. > > autoupdate(recovery): update RO+RW > > * invoke: flashrom -p host --fast-verify -w bios.bin > > autoupdate(recovery): update ec/RO+RW > > * invoke: flashrom -p ec --fast-verify -w ec.bin > > autoupdate(recovery): EC may be restored or updated in next boot. > > Firmware update (autoupdate) completed. > > > > 4. Reboot the board, then power off and power on > > 5. Flash fw 10599 again > > localhost /home # flashrom -w 10599/image.bin > > flashrom v0.9.9 : cfd7dfc : Apr 06 2018 05:12:10 UTC on Linux 4.4.128 > (x86_64) > > flashrom v0.9.9 : cfd7dfc : Apr 06 2018 05:12:10 UTC on Linux 4.4.128 > (x86_64) > > Calibrating delay loop... OK. > > coreboot table found at 0x7aac5000. > > WARNING: SPI Configuration Lockdown activated. > > Erasing and writing flash chip... Verifying flash... VERIFY FAILED at > 0x00000081! Expected=0xff, Read=0x0b, failed byte count from > 0x00000000-0x00ffffff: 0x9 > > Your flash chip is in an unknown state. > > Get help on IRC at irc.freenode.net (channel #flashrom) or > > mail flashrom(a)flashrom.org with FAILED: your board name in the subject > line! > > ------------------------------------------------------------ > ------------------- > > DO NOT REBOOT OR POWEROFF! > > FAILED > > > > > > Thanks > > > > Br, > > Hongxia > > > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > https://mail.coreboot.org/mailman/listinfo/flashrom >

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Re: [flashrom] Flash support FT25H04
by Balázs Vinarz April 26, 2018

April 26, 2018

Sorry, I made a mistake when applying the patch. So the patch works with read, erase and write functions. 2018-04-26 11:34 GMT+02:00 Balázs Vinarz <vinibali1(a)gmail.com>: > Hello there! > > I have the following chip: FT25H04. This is not yet supported even with > the following: patch > <https://raw.githubusercontent.com/tomaskovacik/kicad-library/master/library…>. > Can I help you anyhow to let this type supported? > > Regards >

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Flash support FT25H04
by Balázs Vinarz April 26, 2018

April 26, 2018

Hello there! I have the following chip: FT25H04. This is not yet supported even with the following: patch <https://raw.githubusercontent.com/tomaskovacik/kicad-library/master/library…>. Can I help you anyhow to let this type supported? Regards

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FAILED: Soraka DVT1
by Gao, HongxiaX April 23, 2018

April 23, 2018

Hi, It is failed on my board when flashing firmware R68 10599. Can you help me on it? HW: Soraka DVT1 Issue description: Flash firmware 10431 without any problems, but it is failed when flashing firmware R68 10599. Steps are: 1. Download firmware R68 10599<https://www.google.com/chromeos/partner/fe/#download:event=IMAGE_DOWNLOAD&u…>, then extract it. 2. Enter board terminal localhost /home # flashrom -w 10599/image.bin flashrom v0.9.9 : cfd7dfc : Apr 06 2018 05:12:10 UTC on Linux 4.4.128 (x86_64) flashrom v0.9.9 : cfd7dfc : Apr 06 2018 05:12:10 UTC on Linux 4.4.128 (x86_64) Calibrating delay loop... OK. coreboot table found at 0x7aac5000. WARNING: SPI Configuration Lockdown activated. Erasing and writing flash chip... Verifying flash... VERIFY FAILED at 0x00000081! Expected=0xff, Read=0x0b, failed byte count from 0x00000000-0x00ffffff: 0x9 Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with FAILED: your board name in the subject line! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! FAILED 3. Try to update firmware localhost /home/10599 # chromeos-firmwareupdate -m autoupdate Starting Google_Soraka firmware updater v4 (autoupdate)... - Updater package: [Google_Soraka.10431.32.0 / EC:soraka_v1.1.8047-2c5917d7d] - Current system: [RO:Google_Soraka.10431.32.0 , ACT:Google_Soraka.10431.32.0 / EC:soraka_v1.1.8047-2c5917d7d] - Write protection: Hardware: ON, Software: Main=off * invoke: flashrom -p host -r _current/bios.bin RO Contents are different. autoupdate(recovery): update RO+RW * invoke: flashrom -p host --fast-verify -w bios.bin autoupdate(recovery): update ec/RO+RW * invoke: flashrom -p ec --fast-verify -w ec.bin autoupdate(recovery): EC may be restored or updated in next boot. Firmware update (autoupdate) completed. 4. Reboot the board, then power off and power on 5. Flash fw 10599 again localhost /home # flashrom -w 10599/image.bin flashrom v0.9.9 : cfd7dfc : Apr 06 2018 05:12:10 UTC on Linux 4.4.128 (x86_64) flashrom v0.9.9 : cfd7dfc : Apr 06 2018 05:12:10 UTC on Linux 4.4.128 (x86_64) Calibrating delay loop... OK. coreboot table found at 0x7aac5000. WARNING: SPI Configuration Lockdown activated. Erasing and writing flash chip... Verifying flash... VERIFY FAILED at 0x00000081! Expected=0xff, Read=0x0b, failed byte count from 0x00000000-0x00ffffff: 0x9 Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with FAILED: your board name in the subject line! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! FAILED Thanks Br, Hongxia

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Re: [flashrom] WinBond Chip Support
by Nico Huber April 17, 2018

April 17, 2018

Hi Jordan, On 17.04.2018 14:40, Jordan Hill wrote: > Hello there, > > I have a Dell Inspiron 5559 Laptop which contains a Winbond 25Q128FVSQ > Chip. I tried running flashrom natively on the laptop and got the usual EC > warning so i stopped there. I then desoldered the SMD chip off the > motherboard and hooked it up to a RPI and connected it through the SPI > protocol. Flashrom then recognized it as a "Generic" flash chip and would > not allow the data to be read as it was still unrecognized. did you connect all input pins of the flash chip? A common error is to leave /HOLD and /WP floating. But they need a defined state. /HOLD has to be pulled up (towards VCC). /WP up too (might as well be down depen- ding on the chip's configuration, but up always works). Nico

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WinBond Chip Support
by Jordan Hill April 17, 2018

April 17, 2018

Hello there, I have a Dell Inspiron 5559 Laptop which contains a Winbond 25Q128FVSQ Chip. I tried running flashrom natively on the laptop and got the usual EC warning so i stopped there. I then desoldered the SMD chip off the motherboard and hooked it up to a RPI and connected it through the SPI protocol. Flashrom then recognized it as a "Generic" flash chip and would not allow the data to be read as it was still unrecognized. Unfortunately I do not have any logs. I believe that this chip is on the list of supported hardware yet it was not recognized in flashrom. I am using the latest version as of April 18th 2018. Any suggestions or help would be appreciated. Thank You

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Re: [flashrom] no spi flash IS25LP128
by Nico Huber April 17, 2018

April 17, 2018

On 16.04.2018 05:07, 山中老虎 wrote: > no spi flash IS25LP128 This chip is supported on our master branch only. You'd have to clone the repository and build flashrom yourself, see [1]. Nico PS. Please don't send unnecessary large attachments to the mailing list. [1] https://flashrom.org/Downloads

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As requested, W25Q256.V works perfectly with Bus Pirate
by Richard Hughes April 4, 2018

April 4, 2018

Using git master: Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Bus Pirate firmware 6.1 and older does not support SPI speeds above 2 MHz. Limiting speed to 2 MHz. It is recommended to upgrade to firmware 6.2 or newer. Found Winbond flash chip "W25Q256.V" (32768 kB, SPI) on buspirate_spi. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash chip. Please include the flashrom log file for all operations you tested (see the man page for details), and mention which mainboard or programmer you tested in the subject line. Thanks for your help! Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. Richard.

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NVIDIA CK804: TYAN VX50 B4985: unexpected second chipset match: "NVIDIA CK804"
by Paul Menzel April 3, 2018

April 3, 2018

Dear flashrom folks, As asked by flashrom, here is the output for the TYAN VX50 B4985 [1]. ``` $ sudo flashrom -p internal flashrom v1.0 on Linux 4.14.30.mx64.211 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Found chipset "NVIDIA CK804". Enabling flash write... OK. Warning: unexpected second chipset match: "NVIDIA CK804" ignoring, please report lspci and board URL to flashrom(a)flashrom.org with 'CHIPSET: your board name' in the subject line. Found SST flash chip "SST49LF080A" (1024 kB, LPC) mapped at physical address 0x00000000fff00000. No operations were specified. $ lspci 00:00.0 Memory controller: NVIDIA Corporation CK804 Memory Controller (rev a4) 00:01.0 ISA bridge: NVIDIA Corporation CK804 ISA Bridge (rev f1) 00:01.1 SMBus: NVIDIA Corporation CK804 SMBus (rev a2) 00:02.0 USB controller: NVIDIA Corporation CK804 USB Controller (rev a2) 00:02.1 USB controller: NVIDIA Corporation CK804 USB Controller (rev a4) 00:06.0 IDE interface: NVIDIA Corporation CK804 IDE (rev f3) 00:07.0 IDE interface: NVIDIA Corporation CK804 Serial ATA Controller (rev f3) 00:08.0 IDE interface: NVIDIA Corporation CK804 Serial ATA Controller (rev f3) 00:09.0 PCI bridge: NVIDIA Corporation CK804 PCI Bridge (rev f2) 00:0a.0 Bridge: NVIDIA Corporation CK804 Ethernet Controller (rev f3) 00:0b.0 PCI bridge: NVIDIA Corporation CK804 PCIE Bridge (rev f3) 00:0c.0 PCI bridge: NVIDIA Corporation CK804 PCIE Bridge (rev f3) 00:0d.0 PCI bridge: NVIDIA Corporation CK804 PCIE Bridge (rev f3) 00:0e.0 PCI bridge: NVIDIA Corporation CK804 PCIE Bridge (rev a3) 00:18.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration 00:18.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map 00:18.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control 00:18.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control 00:19.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration 00:19.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map 00:19.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller 00:19.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control 00:19.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control 00:1a.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration 00:1a.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map 00:1a.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller 00:1a.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control 00:1a.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control 00:1b.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration 00:1b.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map 00:1b.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller 00:1b.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control 00:1b.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control 00:1c.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration 00:1c.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map 00:1c.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller 00:1c.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control 00:1c.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control 00:1d.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration 00:1d.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map 00:1d.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller 00:1d.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control 00:1d.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control 00:1e.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration 00:1e.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map 00:1e.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller 00:1e.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control 00:1e.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control 00:1f.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration 00:1f.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map 00:1f.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller 00:1f.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control 00:1f.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control 01:06.0 Ethernet controller: Intel Corporation 82541GI Gigabit Ethernet Controller (rev 05) 01:09.0 VGA compatible controller: XGI Technology Inc. (eXtreme Graphics Innovation) Z7/Z9 (XG20 core) 05:00.0 RAID bus controller: 3ware Inc 9650SE SATA-II RAID PCIe (rev 01) 0a:00.0 RAID bus controller: 3ware Inc 9690SA SAS/SATA-II RAID PCIe (rev 01) 80:00.0 Memory controller: NVIDIA Corporation CK804 Memory Controller (rev a4) 80:01.0 Memory controller: NVIDIA Corporation CK804 Memory Controller (rev f1) 80:0a.0 Bridge: NVIDIA Corporation CK804 Ethernet Controller (rev f3) 80:0b.0 PCI bridge: NVIDIA Corporation CK804 PCIE Bridge (rev f3) 80:0c.0 PCI bridge: NVIDIA Corporation CK804 PCIE Bridge (rev f3) 80:0d.0 PCI bridge: NVIDIA Corporation CK804 PCIE Bridge (rev f3) 80:0e.0 PCI bridge: NVIDIA Corporation CK804 PCIE Bridge (rev a3) ``` Kind regards, Paul [1] https://www.tyan.com/Barebones_VX50B4985_Transport%20VX50

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