October 2015 - flashrom - mail.coreboot.org

80/100/132 column line width policy
by Carl-Daniel Hailfinger Dec. 15, 2018

Dec. 15, 2018

Hi, we're hitting the 80 column limit in our code in ways which actually reduce readability for the code. Examples are various multiline messages and complicated nested code where refactoring to a separate function doesn't make sense. Keeping the old 80 column limit is not really an option anymore. Standard terminal sizes have one of 80, 100 or 132 columns. Given the monitor resolutions many people have nowadays, I think it is safe to say that you can fit two xterms with 100 columns horizonally next to each other. 100 columns should also be sufficient for a msg_p* of roughly 80 columns of text. 132 columns provide more leeway, but IMHO that would be too wide for good readability (and my screen can't fit two xterms side-by-side anymore). Of course some files have sections where any column limit is not acceptable (board lists etc.), but the column limit violations should be limited to the affected file sections, not whole files. Comments? I'd like to get this decided today or tomorrow so we know where we need line breaks in Stefan Tauner's new struct flashchip patch. Regards, Carl-Daniel -- http://www.hailfinger.org/

7 9

Spansion S25FL128P......X
by The Raven April 24, 2017

April 24, 2017

I have a spansion S25FL128P......X chip and can do some tests. The "problem" is that i don't know if its an 0 or an 1. On the chip i see only "FL128PIF" and one line lower i see "00299012 C". Probing works (id1 0x01, id2 0x2018): Calibrating delay loop... OK. serprog: Programmer name is "serprog-duino" Found Spansion flash chip "S25FL128P......0" (16384 kB, SPI) on serprog. Found Spansion flash chip "S25FL128P......1" (16384 kB, SPI) on serprog. Found Spansion flash chip "S25FL128S......0" (16384 kB, SPI) on serprog. Found Spansion flash chip "S25FL128S......1" (16384 kB, SPI) on serprog. Found Spansion flash chip "S25FL129P......0" (16384 kB, SPI) on serprog. Found Spansion flash chip "S25FL129P......1" (16384 kB, SPI) on serprog. Multiple flash chip definitions match the detected chip(s): "S25FL128P......0", "S25FL128P......1", "S25FL128S......0", "S25FL128S......1", "S25FL129P......0", "S25FL129P......1" Please specify which chip definition to use with the -c <chipname> option. BTW: Chip was fund on a Dell-Systemboard.

3 6

[PATCH] Support device lists for programmers without PCI/USB IDs
by Carl-Daniel Hailfinger Feb. 29, 2016

Feb. 29, 2016

Based on an idea by Kyösti Mälkki. Issues: print_wiki is broken right now. Don't compile it in. The internal programmer is listed twice in -L output. Some programmers have stupid indentation in -L output. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-noid_programmers_support_device_list/ogp_spi.c =================================================================== --- flashrom-noid_programmers_support_device_list/ogp_spi.c (Revision 1666) +++ flashrom-noid_programmers_support_device_list/ogp_spi.c (Arbeitskopie) @@ -47,7 +47,7 @@ static uint32_t ogp_reg__ce; static uint32_t ogp_reg_sck; -const struct dev_entry ogp_spi[] = { +const struct id_dev_entry ogp_spi[] = { {PCI_VENDOR_ID_OGP, 0x0000, OK, "Open Graphics Project", "Development Board OGD1"}, {0}, Index: flashrom-noid_programmers_support_device_list/drkaiser.c =================================================================== --- flashrom-noid_programmers_support_device_list/drkaiser.c (Revision 1666) +++ flashrom-noid_programmers_support_device_list/drkaiser.c (Arbeitskopie) @@ -33,7 +33,7 @@ /* Mask to restrict flash accesses to the 128kB memory window. */ #define DRKAISER_MEMMAP_MASK ((1 << 17) - 1) -const struct dev_entry drkaiser_pcidev[] = { +const struct id_dev_entry drkaiser_pcidev[] = { {0x1803, 0x5057, OK, "Dr. Kaiser", "PC-Waechter (Actel FPGA)"}, {0}, Index: flashrom-noid_programmers_support_device_list/pcidev.c =================================================================== --- flashrom-noid_programmers_support_device_list/pcidev.c (Revision 1666) +++ flashrom-noid_programmers_support_device_list/pcidev.c (Arbeitskopie) @@ -184,7 +184,7 @@ * also matches the specified bus:device.function. * For convenience, this function also registers its own undo handlers. */ -struct pci_dev *pcidev_init(const struct dev_entry *devs, int bar) +struct pci_dev *pcidev_init(const struct id_dev_entry *devs, int bar) { struct pci_dev *dev; struct pci_dev *found_dev = NULL; Index: flashrom-noid_programmers_support_device_list/gfxnvidia.c =================================================================== --- flashrom-noid_programmers_support_device_list/gfxnvidia.c (Revision 1666) +++ flashrom-noid_programmers_support_device_list/gfxnvidia.c (Arbeitskopie) @@ -34,7 +34,7 @@ uint8_t *nvidia_bar; -const struct dev_entry gfx_nvidia[] = { +const struct id_dev_entry gfx_nvidia[] = { {0x10de, 0x0010, NT, "NVIDIA", "Mutara V08 [NV2]" }, {0x10de, 0x0018, NT, "NVIDIA", "RIVA 128" }, {0x10de, 0x0020, NT, "NVIDIA", "RIVA TNT" }, Index: flashrom-noid_programmers_support_device_list/serprog.c =================================================================== --- flashrom-noid_programmers_support_device_list/serprog.c (Revision 1666) +++ flashrom-noid_programmers_support_device_list/serprog.c (Arbeitskopie) @@ -44,6 +44,11 @@ #define MSGHEADER "serprog: " +const struct noid_dev_entry serprog_devs[] = { + {"", OK, "All programmer devices speaking the serprog protocol"}, + {0}, +}; + /* * FIXME: This prototype was added to help reduce diffs for the shutdown * registration patch, which shifted many lines of code to place Index: flashrom-noid_programmers_support_device_list/nicrealtek.c =================================================================== --- flashrom-noid_programmers_support_device_list/nicrealtek.c (Revision 1666) +++ flashrom-noid_programmers_support_device_list/nicrealtek.c (Arbeitskopie) @@ -30,7 +30,7 @@ static int bios_rom_addr, bios_rom_data; -const struct dev_entry nics_realtek[] = { +const struct id_dev_entry nics_realtek[] = { {0x10ec, 0x8139, OK, "Realtek", "RTL8139/8139C/8139C+"}, {0x10ec, 0x8169, NT, "Realtek", "RTL8169"}, {0x1113, 0x1211, OK, "SMC", "1211TX"}, /* RTL8139 clone */ Index: flashrom-noid_programmers_support_device_list/satamv.c =================================================================== --- flashrom-noid_programmers_support_device_list/satamv.c (Revision 1666) +++ flashrom-noid_programmers_support_device_list/satamv.c (Arbeitskopie) @@ -29,7 +29,7 @@ uint8_t *mv_bar; uint16_t mv_iobar; -const struct dev_entry satas_mv[] = { +const struct id_dev_entry satas_mv[] = { /* 88SX6041 and 88SX6042 are the same according to the datasheet. */ {0x11ab, 0x7042, OK, "Marvell", "88SX7042 PCI-e 4-port SATA-II"}, Index: flashrom-noid_programmers_support_device_list/dummyflasher.c =================================================================== --- flashrom-noid_programmers_support_device_list/dummyflasher.c (Revision 1666) +++ flashrom-noid_programmers_support_device_list/dummyflasher.c (Arbeitskopie) @@ -39,6 +39,11 @@ #include <sys/stat.h> #endif +const struct noid_dev_entry dummy_devs[] = { + {"dummy", OK, "Dummy device, does nothing and logs all accesses"}, + {0}, +}; + #if EMULATE_CHIP static uint8_t *flashchip_contents = NULL; enum emu_chip { Index: flashrom-noid_programmers_support_device_list/internal.c =================================================================== --- flashrom-noid_programmers_support_device_list/internal.c (Revision 1666) +++ flashrom-noid_programmers_support_device_list/internal.c (Arbeitskopie) @@ -97,6 +97,11 @@ #endif #if CONFIG_INTERNAL == 1 +const struct noid_dev_entry internal_devs[] = { + {"", OK, "Insert witty remark here and/or reference the board/chipset list\n"}, + {0}, +}; + int force_boardenable = 0; int force_boardmismatch = 0; Index: flashrom-noid_programmers_support_device_list/print_wiki.c =================================================================== --- flashrom-noid_programmers_support_device_list/print_wiki.c (Revision 1666) +++ flashrom-noid_programmers_support_device_list/print_wiki.c (Arbeitskopie) @@ -301,7 +301,7 @@ /* Following functions are not needed when no PCI/USB programmers are compiled in, * but since print_wiki code has no size constraints we include it unconditionally. */ -static int count_supported_devs_wiki(const struct dev_entry *devs) +static int count_supported_devs_wiki(const struct id_dev_entry *devs) { unsigned int count = 0; unsigned int i = 0; @@ -309,12 +309,13 @@ count++; return count; } +#warning Handle noid_dev_entry devices static void print_supported_devs_wiki_helper(const struct programmer_entry prog) { int i = 0; static int c = 0; - const struct dev_entry *devs = prog.devs.dev; + const struct id_dev_entry *devs = prog.devs.dev; const unsigned int count = count_supported_devs_wiki(devs); /* Alternate colors if the vendor changes. */ Index: flashrom-noid_programmers_support_device_list/nicintel_spi.c =================================================================== --- flashrom-noid_programmers_support_device_list/nicintel_spi.c (Revision 1666) +++ flashrom-noid_programmers_support_device_list/nicintel_spi.c (Arbeitskopie) @@ -67,7 +67,7 @@ uint8_t *nicintel_spibar; -const struct dev_entry nics_intel_spi[] = { +const struct id_dev_entry nics_intel_spi[] = { {PCI_VENDOR_ID_INTEL, 0x105e, OK, "Intel", "82571EB Gigabit Ethernet Controller"}, {PCI_VENDOR_ID_INTEL, 0x1076, OK, "Intel", "82541GI Gigabit Ethernet Controller"}, {PCI_VENDOR_ID_INTEL, 0x107c, OK, "Intel", "82541PI Gigabit Ethernet Controller"}, Index: flashrom-noid_programmers_support_device_list/usbblaster_spi.c =================================================================== --- flashrom-noid_programmers_support_device_list/usbblaster_spi.c (Revision 1666) +++ flashrom-noid_programmers_support_device_list/usbblaster_spi.c (Arbeitskopie) @@ -49,7 +49,7 @@ #define ALTERA_VID 0x09fb #define ALTERA_USBBLASTER_PID 0x6001 -const struct dev_entry devs_usbblasterspi[] = { +const struct id_dev_entry devs_usbblasterspi[] = { {ALTERA_VID, ALTERA_USBBLASTER_PID, OK, "Altera", "USB-Blaster"}, {} Index: flashrom-noid_programmers_support_device_list/nicnatsemi.c =================================================================== --- flashrom-noid_programmers_support_device_list/nicnatsemi.c (Revision 1666) +++ flashrom-noid_programmers_support_device_list/nicnatsemi.c (Arbeitskopie) @@ -30,7 +30,7 @@ #define BOOT_ROM_ADDR 0x50 #define BOOT_ROM_DATA 0x54 -const struct dev_entry nics_natsemi[] = { +const struct id_dev_entry nics_natsemi[] = { {0x100b, 0x0020, NT, "National Semiconductor", "DP83815/DP83816"}, {0x100b, 0x0022, NT, "National Semiconductor", "DP83820"}, Index: flashrom-noid_programmers_support_device_list/rayer_spi.c =================================================================== --- flashrom-noid_programmers_support_device_list/rayer_spi.c (Revision 1666) +++ flashrom-noid_programmers_support_device_list/rayer_spi.c (Arbeitskopie) @@ -37,6 +37,12 @@ #include "programmer.h" #include "hwaccess.h" +const struct noid_dev_entry rayer_spi_devs[] = { + {"rayer", OK, "RayeR parallel port programmer"}, + {"xilinx", OK, "Xilinx Parallel Cable III (DLC 5)"}, + {0}, +}; + enum rayer_type { TYPE_RAYER, TYPE_XILINX_DLC5, Index: flashrom-noid_programmers_support_device_list/dediprog.c =================================================================== --- flashrom-noid_programmers_support_device_list/dediprog.c (Revision 1666) +++ flashrom-noid_programmers_support_device_list/dediprog.c (Arbeitskopie) @@ -27,6 +27,11 @@ #include "programmer.h" #include "spi.h" +const struct noid_dev_entry dediprog_devs[] = { + {"", OK, "Dediprog SF100"}, + {0}, +}; + #define FIRMWARE_VERSION(x,y,z) ((x << 16) | (y << 8) | z) #define DEFAULT_TIMEOUT 3000 static usb_dev_handle *dediprog_handle; Index: flashrom-noid_programmers_support_device_list/buspirate_spi.c =================================================================== --- flashrom-noid_programmers_support_device_list/buspirate_spi.c (Revision 1666) +++ flashrom-noid_programmers_support_device_list/buspirate_spi.c (Arbeitskopie) @@ -27,6 +27,11 @@ #include "programmer.h" #include "spi.h" +const struct noid_dev_entry buspirate_spi_devs[] = { + {"", OK, "Dangerous Prototypes Bus Pirate"}, + {0}, +}; + /* Change this to #define if you want to test without a serial implementation */ #undef FAKE_COMMUNICATION Index: flashrom-noid_programmers_support_device_list/linux_spi.c =================================================================== --- flashrom-noid_programmers_support_device_list/linux_spi.c (Revision 1666) +++ flashrom-noid_programmers_support_device_list/linux_spi.c (Arbeitskopie) @@ -34,6 +34,11 @@ #include "programmer.h" #include "spi.h" +const struct noid_dev_entry linux_spi_devs[] = { + {"", OK, "Device files /dev/spidev*.*"}, + {0}, +}; + static int fd = -1; static int linux_spi_shutdown(void *data); Index: flashrom-noid_programmers_support_device_list/atahpt.c =================================================================== --- flashrom-noid_programmers_support_device_list/atahpt.c (Revision 1666) +++ flashrom-noid_programmers_support_device_list/atahpt.c (Arbeitskopie) @@ -33,7 +33,7 @@ #define PCI_VENDOR_ID_HPT 0x1103 -const struct dev_entry ata_hpt[] = { +const struct id_dev_entry ata_hpt[] = { {0x1103, 0x0004, NT, "Highpoint", "HPT366/368/370/370A/372/372N"}, {0x1103, 0x0005, NT, "Highpoint", "HPT372A/372N"}, {0x1103, 0x0006, NT, "Highpoint", "HPT302/302N"}, Index: flashrom-noid_programmers_support_device_list/nic3com.c =================================================================== --- flashrom-noid_programmers_support_device_list/nic3com.c (Revision 1666) +++ flashrom-noid_programmers_support_device_list/nic3com.c (Arbeitskopie) @@ -36,7 +36,7 @@ static uint32_t internal_conf; static uint16_t id; -const struct dev_entry nics_3com[] = { +const struct id_dev_entry nics_3com[] = { /* 3C90xB */ {0x10b7, 0x9055, OK, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX"}, {0x10b7, 0x9001, NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4" }, Index: flashrom-noid_programmers_support_device_list/satasii.c =================================================================== --- flashrom-noid_programmers_support_device_list/satasii.c (Revision 1666) +++ flashrom-noid_programmers_support_device_list/satasii.c (Arbeitskopie) @@ -30,7 +30,7 @@ static uint8_t *sii_bar; static uint16_t id; -const struct dev_entry satas_sii[] = { +const struct id_dev_entry satas_sii[] = { {0x1095, 0x0680, OK, "Silicon Image", "PCI0680 Ultra ATA-133 Host Ctrl"}, {0x1095, 0x3112, OK, "Silicon Image", "SiI 3112 [SATALink/SATARaid] SATA Ctrl"}, {0x1095, 0x3114, OK, "Silicon Image", "SiI 3114 [SATALink/SATARaid] SATA Ctrl"}, Index: flashrom-noid_programmers_support_device_list/ft2232_spi.c =================================================================== --- flashrom-noid_programmers_support_device_list/ft2232_spi.c (Revision 1666) +++ flashrom-noid_programmers_support_device_list/ft2232_spi.c (Arbeitskopie) @@ -57,7 +57,7 @@ #define OLIMEX_ARM_OCD_H_PID 0x002B #define OLIMEX_ARM_TINY_H_PID 0x002A -const struct dev_entry devs_ft2232spi[] = { +const struct id_dev_entry devs_ft2232spi[] = { {FTDI_VID, FTDI_FT2232H_PID, OK, "FTDI", "FT2232H"}, {FTDI_VID, FTDI_FT4232H_PID, OK, "FTDI", "FT4232H"}, {FTDI_VID, FTDI_FT232H_PID, OK, "FTDI", "FT232H"}, Index: flashrom-noid_programmers_support_device_list/pony_spi.c =================================================================== --- flashrom-noid_programmers_support_device_list/pony_spi.c (Revision 1666) +++ flashrom-noid_programmers_support_device_list/pony_spi.c (Arbeitskopie) @@ -47,6 +47,13 @@ #include "flash.h" #include "programmer.h" +const struct noid_dev_entry pony_spi_devs[] = { + {"serbang", OK, "Programmers compatible with serbang"}, + {"si_prog", OK, "Programmers compatible with SI-Prog"}, + {"ajawe", OK, "Programmers compatible with AJAWe"}, + {0}, +}; + enum pony_type { TYPE_SI_PROG, TYPE_SERBANG, Index: flashrom-noid_programmers_support_device_list/nicintel.c =================================================================== --- flashrom-noid_programmers_support_device_list/nicintel.c (Revision 1666) +++ flashrom-noid_programmers_support_device_list/nicintel.c (Arbeitskopie) @@ -27,7 +27,7 @@ uint8_t *nicintel_bar; uint8_t *nicintel_control_bar; -const struct dev_entry nics_intel[] = { +const struct id_dev_entry nics_intel[] = { {PCI_VENDOR_ID_INTEL, 0x1209, NT, "Intel", "8255xER/82551IT Fast Ethernet Controller"}, {PCI_VENDOR_ID_INTEL, 0x1229, OK, "Intel", "82557/8/9/0/1 Ethernet Pro 100"}, Index: flashrom-noid_programmers_support_device_list/flashrom.c =================================================================== --- flashrom-noid_programmers_support_device_list/flashrom.c (Revision 1666) +++ flashrom-noid_programmers_support_device_list/flashrom.c (Arbeitskopie) @@ -65,7 +65,7 @@ { .name = "internal", .type = OTHER, - .devs.note = NULL, + .devs.noid_dev = internal_devs, .init = internal_init, .map_flash_region = physmap, .unmap_flash_region = physunmap, @@ -77,8 +77,7 @@ { .name = "dummy", .type = OTHER, - /* FIXME */ - .devs.note = "Dummy device, does nothing and logs all accesses\n", + .devs.noid_dev = dummy_devs, .init = dummy_init, .map_flash_region = dummy_map, .unmap_flash_region = dummy_unmap, @@ -90,7 +89,7 @@ { .name = "nic3com", .type = PCI, - .devs.dev = nics_3com, + .devs.id_dev = nics_3com, .init = nic3com_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, @@ -103,7 +102,7 @@ /* This programmer works for Realtek RTL8139 and SMC 1211. */ .name = "nicrealtek", .type = PCI, - .devs.dev = nics_realtek, + .devs.id_dev = nics_realtek, .init = nicrealtek_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, @@ -115,7 +114,7 @@ { .name = "nicnatsemi", .type = PCI, - .devs.dev = nics_natsemi, + .devs.id_dev = nics_natsemi, .init = nicnatsemi_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, @@ -127,7 +126,7 @@ { .name = "gfxnvidia", .type = PCI, - .devs.dev = gfx_nvidia, + .devs.id_dev = gfx_nvidia, .init = gfxnvidia_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, @@ -139,7 +138,7 @@ { .name = "drkaiser", .type = PCI, - .devs.dev = drkaiser_pcidev, + .devs.id_dev = drkaiser_pcidev, .init = drkaiser_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, @@ -151,7 +150,7 @@ { .name = "satasii", .type = PCI, - .devs.dev = satas_sii, + .devs.id_dev = satas_sii, .init = satasii_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, @@ -163,7 +162,7 @@ { .name = "atahpt", .type = PCI, - .devs.dev = ata_hpt, + .devs.id_dev = ata_hpt, .init = atahpt_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, @@ -175,7 +174,7 @@ { .name = "ft2232_spi", .type = USB, - .devs.dev = devs_ft2232spi, + .devs.id_dev = devs_ft2232spi, .init = ft2232_spi_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, @@ -187,8 +186,7 @@ { .name = "serprog", .type = OTHER, - /* FIXME */ - .devs.note = "All programmer devices speaking the serprog protocol\n", + .devs.noid_dev = serprog_devs, .init = serprog_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, @@ -200,8 +198,7 @@ { .name = "buspirate_spi", .type = OTHER, - /* FIXME */ - .devs.note = "Dangerous Prototypes Bus Pirate\n", + .devs.noid_dev = buspirate_spi_devs, .init = buspirate_spi_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, @@ -213,8 +210,7 @@ { .name = "dediprog", .type = OTHER, - /* FIXME */ - .devs.note = "Dediprog SF100\n", + .devs.noid_dev = dediprog_devs, .init = dediprog_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, @@ -226,8 +222,7 @@ { .name = "rayer_spi", .type = OTHER, - /* FIXME */ - .devs.note = "RayeR parallel port programmer\n", + .devs.noid_dev = rayer_spi_devs, .init = rayer_spi_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, @@ -239,8 +234,7 @@ { .name = "pony_spi", .type = OTHER, - /* FIXME */ - .devs.note = "Programmers compatible with SI-Prog, serbang or AJAWe\n", + .devs.noid_dev = pony_spi_devs, .init = pony_spi_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, @@ -252,7 +246,7 @@ { .name = "nicintel", .type = PCI, - .devs.dev = nics_intel, + .devs.id_dev = nics_intel, .init = nicintel_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, @@ -264,7 +258,7 @@ { .name = "nicintel_spi", .type = PCI, - .devs.dev = nics_intel_spi, + .devs.id_dev = nics_intel_spi, .init = nicintel_spi_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, @@ -276,7 +270,7 @@ { .name = "ogp_spi", .type = PCI, - .devs.dev = ogp_spi, + .devs.id_dev = ogp_spi, .init = ogp_spi_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, @@ -288,7 +282,7 @@ { .name = "satamv", .type = PCI, - .devs.dev = satas_mv, + .devs.id_dev = satas_mv, .init = satamv_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, @@ -300,7 +294,7 @@ { .name = "linux_spi", .type = OTHER, - .devs.note = "Device files /dev/spidev*.*\n", + .devs.noid_dev = linux_spi_devs, .init = linux_spi_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, @@ -312,7 +306,7 @@ { .name = "usbblaster_spi", .type = USB, - .devs.dev = devs_usbblasterspi, + .devs.id_dev = devs_usbblasterspi, .init = usbblaster_spi_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, @@ -1675,10 +1669,9 @@ case USB: case PCI: case OTHER: - if (p.devs.note == NULL) { - if (strcmp("internal", p.name) == 0) - break; /* This one has its device list stored separately. */ - msg_gerr("Programmer %s has neither a device list nor a textual description!\n", + /* Either id_dev or noid_dev should be non-NULL. */ + if (p.devs.id_dev == NULL) { + msg_gerr("Programmer %s doesn't have a device list!\n", p.name); ret = 1; } Index: flashrom-noid_programmers_support_device_list/programmer.h =================================================================== --- flashrom-noid_programmers_support_device_list/programmer.h (Revision 1666) +++ flashrom-noid_programmers_support_device_list/programmer.h (Arbeitskopie) @@ -99,7 +99,13 @@ OTHER, }; -struct dev_entry { +struct noid_dev_entry { + const char *type; + const enum test_state status; + const char *description; +}; + +struct id_dev_entry { uint16_t vendor_id; uint16_t device_id; const enum test_state status; @@ -111,8 +117,8 @@ const char *name; const enum programmer_type type; union { - const struct dev_entry *const dev; - const char *const note; + const struct noid_dev_entry *const noid_dev; + const struct id_dev_entry *const id_dev; } devs; int (*init) (void); @@ -172,7 +178,7 @@ extern struct pci_access *pacc; int pci_init_common(void); uintptr_t pcidev_readbar(struct pci_dev *dev, int bar); -struct pci_dev *pcidev_init(const struct dev_entry *devs, int bar); +struct pci_dev *pcidev_init(const struct id_dev_entry *devs, int bar); /* rpci_write_* are reversible writes. The original PCI config space register * contents will be restored on shutdown. */ @@ -320,6 +326,7 @@ int register_superio(struct superio s); extern enum chipbustype internal_buses_supported; int internal_init(void); +extern const struct noid_dev_entry internal_devs[]; #endif /* hwaccess.c */ @@ -360,94 +367,97 @@ int dummy_init(void); void *dummy_map(const char *descr, unsigned long phys_addr, size_t len); void dummy_unmap(void *virt_addr, size_t len); +extern const struct noid_dev_entry dummy_devs[]; #endif /* nic3com.c */ #if CONFIG_NIC3COM == 1 int nic3com_init(void); -extern const struct dev_entry nics_3com[]; +extern const struct id_dev_entry nics_3com[]; #endif /* gfxnvidia.c */ #if CONFIG_GFXNVIDIA == 1 int gfxnvidia_init(void); -extern const struct dev_entry gfx_nvidia[]; +extern const struct id_dev_entry gfx_nvidia[]; #endif /* drkaiser.c */ #if CONFIG_DRKAISER == 1 int drkaiser_init(void); -extern const struct dev_entry drkaiser_pcidev[]; +extern const struct id_dev_entry drkaiser_pcidev[]; #endif /* nicrealtek.c */ #if CONFIG_NICREALTEK == 1 int nicrealtek_init(void); -extern const struct dev_entry nics_realtek[]; +extern const struct id_dev_entry nics_realtek[]; #endif /* nicnatsemi.c */ #if CONFIG_NICNATSEMI == 1 int nicnatsemi_init(void); -extern const struct dev_entry nics_natsemi[]; +extern const struct id_dev_entry nics_natsemi[]; #endif /* nicintel.c */ #if CONFIG_NICINTEL == 1 int nicintel_init(void); -extern const struct dev_entry nics_intel[]; +extern const struct id_dev_entry nics_intel[]; #endif /* nicintel_spi.c */ #if CONFIG_NICINTEL_SPI == 1 int nicintel_spi_init(void); -extern const struct dev_entry nics_intel_spi[]; +extern const struct id_dev_entry nics_intel_spi[]; #endif /* ogp_spi.c */ #if CONFIG_OGP_SPI == 1 int ogp_spi_init(void); -extern const struct dev_entry ogp_spi[]; +extern const struct id_dev_entry ogp_spi[]; #endif /* satamv.c */ #if CONFIG_SATAMV == 1 int satamv_init(void); -extern const struct dev_entry satas_mv[]; +extern const struct id_dev_entry satas_mv[]; #endif /* satasii.c */ #if CONFIG_SATASII == 1 int satasii_init(void); -extern const struct dev_entry satas_sii[]; +extern const struct id_dev_entry satas_sii[]; #endif /* atahpt.c */ #if CONFIG_ATAHPT == 1 int atahpt_init(void); -extern const struct dev_entry ata_hpt[]; +extern const struct id_dev_entry ata_hpt[]; #endif /* ft2232_spi.c */ #if CONFIG_FT2232_SPI == 1 int ft2232_spi_init(void); -extern const struct dev_entry devs_ft2232spi[]; +extern const struct id_dev_entry devs_ft2232spi[]; #endif /* usbblaster_spi.c */ #if CONFIG_USBBLASTER_SPI == 1 int usbblaster_spi_init(void); -extern const struct dev_entry devs_usbblasterspi[]; +extern const struct id_dev_entry devs_usbblasterspi[]; #endif /* rayer_spi.c */ #if CONFIG_RAYER_SPI == 1 int rayer_spi_init(void); +extern const struct noid_dev_entry rayer_spi_devs[]; #endif /* pony_spi.c */ #if CONFIG_PONY_SPI == 1 int pony_spi_init(void); +extern const struct noid_dev_entry pony_spi_devs[]; #endif /* bitbang_spi.c */ @@ -456,16 +466,19 @@ /* buspirate_spi.c */ #if CONFIG_BUSPIRATE_SPI == 1 int buspirate_spi_init(void); +extern const struct noid_dev_entry buspirate_spi_devs[]; #endif /* linux_spi.c */ #if CONFIG_LINUX_SPI == 1 int linux_spi_init(void); +extern const struct noid_dev_entry linux_spi_devs[]; #endif /* dediprog.c */ #if CONFIG_DEDIPROG == 1 int dediprog_init(void); +extern const struct noid_dev_entry dediprog_devs[]; #endif /* flashrom.c */ @@ -642,6 +655,7 @@ #if CONFIG_SERPROG == 1 int serprog_init(void); void serprog_delay(int usecs); +extern const struct noid_dev_entry serprog_devs[]; #endif /* serial.c */ Index: flashrom-noid_programmers_support_device_list/print.c =================================================================== --- flashrom-noid_programmers_support_device_list/print.c (Revision 1666) +++ flashrom-noid_programmers_support_device_list/print.c (Arbeitskopie) @@ -433,11 +433,11 @@ } #endif -void print_supported_devs(const struct programmer_entry prog, const char *const type) +void print_supported_id_devs(const struct programmer_entry prog, const char *const type) { int i; - const struct dev_entry *const devs = prog.devs.dev; + const struct id_dev_entry *const devs = prog.devs.id_dev; msg_ginfo("\nSupported %s devices for the %s programmer:\n", type, prog.name); for (i = 0; devs[i].vendor_name != NULL; i++) { msg_pinfo("%s %s [%04x:%04x]%s\n", devs[i].vendor_name, devs[i].device_name, devs[i].vendor_id, @@ -445,6 +445,18 @@ } } +void print_supported_noid_devs(const struct programmer_entry prog, const char *const type) +{ + int i; + + const struct noid_dev_entry *const devs = prog.devs.noid_dev; + msg_ginfo("\nSupported models for the %s programmer:\n", prog.name); + for (i = 0; devs[i].type != NULL; i++) { + msg_pinfo("%-20s %s %s\n", devs[i].type, devs[i].description, + (devs[i].status == NT) ? " (untested)" : ""); + } +} + int print_supported(void) { unsigned int i; @@ -467,18 +479,15 @@ const struct programmer_entry prog = programmer_table[i]; switch (prog.type) { case USB: - print_supported_devs(prog, "USB"); + print_supported_id_devs(prog, "USB"); break; #if NEED_PCI == 1 case PCI: - print_supported_devs(prog, "PCI"); + print_supported_id_devs(prog, "PCI"); break; #endif case OTHER: - if (prog.devs.note != NULL) { - msg_ginfo("\nSupported devices for the %s programmer:\n", prog.name); - msg_ginfo("%s", prog.devs.note); - } + print_supported_noid_devs(prog, "(generic)"); break; default: msg_gerr("\n%s: %s: Uninitialized programmer type! Please report a bug at " -- http://www.hailfinger.org/

2 6

[PATCH 1/4] Bump dediprog driver to use libusb-1.0
by Kyösti Mälkki Jan. 24, 2016

Jan. 24, 2016

From: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Am 21.02.2013 01:46 schrieb Carl-Daniel Hailfinger: > Hi Nico, > > thanks for your patch. > > Am 16.11.2012 11:28 schrieb Nico Huber: >> > This patch tracks the changes in the libusb interface. Nothing changed >> > in the behaviour of the driver, so far. >> > >> > It will be used by a follow-up patch. It's based on "Enable spi clock >> > setting in dediprog driver". >> > >> > Signed-off-by: Nico Huber <nico.huber(a)secunet.com> > Review follows. > The Makefile part checked for libusb 0.1, but it set the linker > parameter for libusb 1.0. > The code assumed that libusb_error_name() is always available, but that > function was only introduced in libusb 1.0.9. > There was a conflict between the added device parameter for multiple > Dedipro SF100 devices on one PC (r1628) and the removal of > get_device_by_vid_pid(). > > I have fixed and forward ported the code, please check that it works and > looks sane. > > This patch is completely untested, I only checked whether it compiles. > If it works for you and looks sane, please tell me so I can commit. > > Signed-off-by: Nico Huber <nico.huber(a)secunet.com> New version. Fixed error messages and incomplete cleanup in the error case. libusb header file location is still something I have to fix in another iteration. Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> --- Makefile | 58 +++++++++----- dediprog.c | 258 +++++++++++++++++++++++++++++++++---------------------------- 2 files changed, 178 insertions(+), 138 deletions(-) diff --git a/Makefile b/Makefile index 07fefc0..96a7987 100644 --- a/Makefile +++ b/Makefile @@ -117,7 +117,7 @@ UNSUPPORTED_FEATURES += CONFIG_PONY_SPI=yes else override CONFIG_PONY_SPI = no endif -# Dediprog and FT2232 are not supported under DOS (missing USB support). +# Dediprog and FT2232 are not supported under DOS (missing libusb support). ifeq ($(CONFIG_DEDIPROG), yes) UNSUPPORTED_FEATURES += CONFIG_DEDIPROG=yes else @@ -504,8 +504,9 @@ ifeq ($(NEED_FTDI), yes) FTDILIBS := $(shell pkg-config --libs libftdi 2>/dev/null || printf "%s" "-lftdi -lusb") FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "FT232H := yes" .features && printf "%s" "-D'HAVE_FT232H=1'") FEATURE_LIBS += $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "$(FTDILIBS)") -# We can't set NEED_USB here because that would transform libftdi auto-enabling +# We can't set NEED_LIBUSB1 here because that would transform libftdi auto-enabling # into a hard requirement for libusb, defeating the purpose of auto-enabling. +# Besides that, the old libftdi requires libusb 0.1, not libusb 1.0. endif ifeq ($(CONFIG_DUMMY), yes) @@ -558,7 +559,7 @@ endif ifeq ($(CONFIG_DEDIPROG), yes) FEATURE_CFLAGS += -D'CONFIG_DEDIPROG=1' PROGRAMMER_OBJS += dediprog.o -NEED_USB := yes +NEED_LIBUSB1 := yes endif ifeq ($(CONFIG_SATAMV), yes) @@ -613,10 +614,12 @@ endif endif endif -ifeq ($(NEED_USB), yes) -CHECK_LIBUSB0 = yes -FEATURE_CFLAGS += -D'NEED_USB=1' -USBLIBS := $(shell pkg-config --libs libusb 2>/dev/null || printf "%s" "-lusb") +ifeq ($(NEED_LIBUSB1), yes) +CHECK_LIBUSB1 = yes +FEATURE_CFLAGS += -D'NEED_LIBUSB1=1' +FEATURE_CFLAGS += $(shell pkg-config --cflags libusb-1.0 2>/dev/null) +USBLIBS := $(shell pkg-config --libs libusb-1.0 2>/dev/null || printf "%s" "-lusb-1.0") +FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "LIBUSB1_ERROR_NAME := yes" .features && printf "%s" "-D'LIBUSB_HAVE_ERROR_NAME=1'") endif ifeq ($(CONFIG_PRINT_WIKI), yes) @@ -711,17 +714,17 @@ int main(int argc, char **argv) endef export LIBPCI_TEST -define LIBUSB0_TEST -#include <usb.h> +define LIBUSB1_TEST +#include <libusb.h> int main(int argc, char **argv) { (void) argc; (void) argv; - usb_init(); + libusb_init(NULL); return 0; } endef -export LIBUSB0_TEST +export LIBUSB1_TEST hwlibs: compiler @printf "" > .libdeps @@ -744,18 +747,18 @@ ifeq ($(CHECK_LIBPCI), yes) rm -f .test.c .test.o .test$(EXEC_SUFFIX); exit 1) ) @rm -f .test.c .test.o .test$(EXEC_SUFFIX) endif -ifeq ($(CHECK_LIBUSB0), yes) - @printf "Checking for libusb-0.1/libusb-compat headers... " - @echo "$$LIBUSB0_TEST" > .test.c - @$(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o >/dev/null && \ +ifeq ($(CHECK_LIBUSB1), yes) + @printf "Checking for libusb-1.0 headers... " + @echo "$$LIBUSB1_TEST" > .test.c + @$(CC) -c $(CPPFLAGS) $(FEATURE_CFLAGS) $(CFLAGS) .test.c -o .test.o >/dev/null && \ echo "found." || ( echo "not found."; echo; \ - echo "Please install libusb-0.1 headers or libusb-compat headers."; \ + echo "Please install libusb-1.0 headers."; \ echo "See README for more information."; echo; \ rm -f .test.c .test.o; exit 1) - @printf "Checking if libusb-0.1 is usable... " + @printf "Checking if libusb-1.0 is usable... " @$(CC) $(LDFLAGS) .test.o -o .test$(EXEC_SUFFIX) $(LIBS) $(USBLIBS) >/dev/null && \ echo "yes." || ( echo "no."; \ - echo "Please install libusb-0.1 or libusb-compat."; \ + echo "Please install libusb-1.0."; \ echo "See README for more information."; echo; \ rm -f .test.c .test.o .test$(EXEC_SUFFIX); exit 1) @rm -f .test.c .test.o .test$(EXEC_SUFFIX) @@ -777,6 +780,18 @@ ifneq ($(UNSUPPORTED_FEATURES), ) @false endif +define LIBUSB1_ERROR_NAME_TEST +#include <libusb.h> +int main(int argc, char **argv) +{ + (void) argc; + (void) argv; + libusb_error_name(0); + return 0; +} +endef +export LIBUSB1_ERROR_NAME_TEST + define FTDI_TEST #include <ftdi.h> struct ftdi_context *ftdic = NULL; @@ -823,6 +838,13 @@ export LINUX_SPI_TEST features: compiler @echo "FEATURES := yes" > .features.tmp +ifeq ($(CHECK_LIBUSB1), yes) + @printf "Checking for libusb_error_name support in libusb-1.0... " + @echo "$$LIBUSB1_ERROR_NAME_TEST" >> .featuretest.c + @$(CC) $(CPPFLAGS) $(FEATURE_CFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) $(USBLIBS) $(LIBS) >/dev/null 2>&1 && \ + ( echo "found."; echo "LIBUSB1_ERROR_NAME := yes" >> .features.tmp ) || \ + ( echo "not found." ) +endif ifeq ($(NEED_FTDI), yes) @printf "Checking for FTDI support... " @echo "$$FTDI_TEST" > .featuretest.c diff --git a/dediprog.c b/dediprog.c index ae86810..c33dc10 100644 --- a/dediprog.c +++ b/dediprog.c @@ -2,6 +2,7 @@ * This file is part of the flashrom project. * * Copyright (C) 2010 Carl-Daniel Hailfinger + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,7 +22,8 @@ #include <string.h> #include <limits.h> #include <errno.h> -#include <usb.h> +#include <stdlib.h> +#include <libusb.h> #include "flash.h" #include "chipdrivers.h" #include "programmer.h" @@ -29,7 +31,8 @@ #define FIRMWARE_VERSION(x,y,z) ((x << 16) | (y << 8) | z) #define DEFAULT_TIMEOUT 3000 -static usb_dev_handle *dediprog_handle; +static libusb_context *usb_ctx; +static libusb_device_handle *dediprog_handle; static int dediprog_firmwareversion; static int dediprog_endpoint; @@ -47,27 +50,63 @@ static void print_hex(void *buf, size_t len) } #endif +#ifndef LIBUSB_HAVE_ERROR_NAME +/* Quick and dirty replacement for missing libusb_error_name in older libusb 1.0. */ +const char *libusb_error_name(int error_code) +{ + /* 18 chars for text, rest for number, sign, nullbyte. */ + static char my_libusb_error[18 + 3 * sizeof(int) + 2]; + + sprintf(my_libusb_error, "libusb error code %i", error_code); + return my_libusb_error; +} +#endif + /* Might be useful for other USB devices as well. static for now. */ /* device parameter allows user to specify one device of multiple installed */ -static struct usb_device *get_device_by_vid_pid(uint16_t vid, uint16_t pid, unsigned int device) +static struct libusb_device_handle *get_device_by_vid_pid_number(uint16_t vid, uint16_t pid, unsigned int num) { - struct usb_bus *bus; - struct usb_device *dev; - - for (bus = usb_get_busses(); bus; bus = bus->next) - for (dev = bus->devices; dev; dev = dev->next) - if ((dev->descriptor.idVendor == vid) && - (dev->descriptor.idProduct == pid)) { - if (device == 0) - return dev; - device--; + struct libusb_device **list; + ssize_t i = 0; + int err = 0; + struct libusb_device_handle *handle = NULL; + struct libusb_device_descriptor desc = {}; + ssize_t count = libusb_get_device_list(usb_ctx, &list); + + if (count < 0) { + msg_perr("Getting the USB device list failed (%s)!\n", libusb_error_name(count)); + return NULL; + } + + for (i = 0; i < count; i++) { + struct libusb_device *dev = list[i]; + err = libusb_get_device_descriptor(dev, &desc); + if (err != 0) { + msg_perr("Reading the USB device descriptor failed (%s)!\n", libusb_error_name(err)); + libusb_free_device_list(list, 1); + return NULL; + } + if ((desc.idVendor == vid) && (desc.idProduct == pid)) { + msg_pdbg("Found USB device %04hx:%04hx at address %hhx-%hhx.\n", desc.idVendor, + desc.idProduct, libusb_get_bus_number(dev), libusb_get_device_address(dev)); + if (num == 0) { + err = libusb_open(dev, &handle); + if (err != 0) { + msg_perr("Opening the USB device failed (%s)!\n", + libusb_error_name(err)); + libusb_free_device_list(list, 1); + return NULL; + } + break; } + num--; + } + } + libusb_free_device_list(list, 1); - return NULL; + return handle; } -//int usb_control_msg(usb_dev_handle *dev, int requesttype, int request, int value, int index, char *bytes, int size, int timeout); - /* Set/clear LEDs on dediprog */ #define PASS_ON (0 << 0) #define PASS_OFF (1 << 0) @@ -101,11 +140,10 @@ static int dediprog_set_leds(int leds) target_leds = leds; } - ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, target_leds, - NULL, 0x0, DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0x42, 0x07, 0x09, target_leds, + NULL, 0x0, DEFAULT_TIMEOUT); if (ret != 0x0) { - msg_perr("Command Set LED 0x%x failed (%s)!\n", - leds, usb_strerror()); + msg_perr("Command Set LED 0x%x failed (%s)!\n", leds, libusb_error_name(ret)); return 1; } @@ -144,8 +182,8 @@ static int dediprog_set_spi_voltage(int millivolt) /* Wait some time as the original driver does. */ programmer_delay(200 * 1000); } - ret = usb_control_msg(dediprog_handle, 0x42, 0x9, voltage_selector, - 0xff, NULL, 0x0, DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0x42, 0x9, voltage_selector, + 0xff, NULL, 0x0, DEFAULT_TIMEOUT); if (ret != 0x0) { msg_perr("Command Set SPI Voltage 0x%x failed!\n", voltage_selector); @@ -188,8 +226,8 @@ static int dediprog_set_spi_speed(unsigned int spispeed_idx) msg_pdbg("SPI speed is %sHz\n", spispeeds[spispeed_idx].name); - ret = usb_control_msg(dediprog_handle, 0x42, 0x61, spispeeds[spispeed_idx].speed, 0xff, - NULL, 0x0, DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0x42, 0x61, spispeeds[spispeed_idx].speed, 0xff, + NULL, 0x0, DEFAULT_TIMEOUT); if (ret != 0x0) { msg_perr("Command Set SPI Speed 0x%x failed!\n", spispeeds[spispeed_idx].speed); return 1; @@ -205,15 +243,15 @@ static int dediprog_set_spi_speed(unsigned int spispeed_idx) static int dediprog_spi_bulk_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) { - int ret; + int ret, transferred; unsigned int i; /* chunksize must be 512, other sizes will NOT work at all. */ const unsigned int chunksize = 0x200; const unsigned int count = len / chunksize; - const char count_and_chunk[] = {count & 0xff, - (count >> 8) & 0xff, - chunksize & 0xff, - (chunksize >> 8) & 0xff}; + const unsigned char count_and_chunk[] = { + count & 0xff, (count >> 8) & 0xff, + chunksize & 0xff, (chunksize >> 8) & 0xff + }; if ((start % chunksize) || (len % chunksize)) { msg_perr("%s: Unaligned start=%i, len=%i! Please report a bug " @@ -227,22 +265,20 @@ static int dediprog_spi_bulk_read(struct flashctx *flash, uint8_t *buf, /* Command Read SPI Bulk. No idea which read command is used on the * SPI side. */ - ret = usb_control_msg(dediprog_handle, 0x42, 0x20, start % 0x10000, - start / 0x10000, (char *)count_and_chunk, - sizeof(count_and_chunk), DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0x42, 0x20, start % 0x10000, start / 0x10000, + (unsigned char *)count_and_chunk, sizeof(count_and_chunk), + DEFAULT_TIMEOUT); if (ret != sizeof(count_and_chunk)) { - msg_perr("Command Read SPI Bulk failed, %i %s!\n", ret, - usb_strerror()); + msg_perr("Command Read SPI Bulk failed, %i %s!\n", ret, libusb_error_name(ret)); return 1; } for (i = 0; i < count; i++) { - ret = usb_bulk_read(dediprog_handle, 0x80 | dediprog_endpoint, - (char *)buf + i * chunksize, chunksize, - DEFAULT_TIMEOUT); - if (ret != chunksize) { - msg_perr("SPI bulk read %i failed, expected %i, got %i " - "%s!\n", i, chunksize, ret, usb_strerror()); + ret = libusb_bulk_transfer(dediprog_handle, 0x80 | dediprog_endpoint, + buf + i * chunksize, chunksize, &transferred, DEFAULT_TIMEOUT); + if ((ret < 0) || (transferred != chunksize)) { + msg_perr("SPI bulk read %i failed, expected %i, got %i %s!\n", + i, chunksize, ret, libusb_error_name(ret)); return 1; } } @@ -306,7 +342,7 @@ static int dediprog_spi_read(struct flashctx *flash, uint8_t *buf, static int dediprog_spi_bulk_write(struct flashctx *flash, uint8_t *buf, unsigned int chunksize, unsigned int start, unsigned int len, uint8_t dedi_spi_cmd) { - int ret; + int ret, transferred; unsigned int i; /* USB transfer size must be 512, other sizes will NOT work at all. * chunksize is the real data size per USB bulk transfer. The remaining @@ -314,7 +350,7 @@ static int dediprog_spi_bulk_write(struct flashctx *flash, uint8_t *buf, unsigne */ const unsigned int count = len / chunksize; const char count_and_cmd[] = {count & 0xff, (count >> 8) & 0xff, 0x00, dedi_spi_cmd}; - char usbbuf[512]; + unsigned char usbbuf[512]; /* * We should change this check to @@ -339,23 +375,21 @@ static int dediprog_spi_bulk_write(struct flashctx *flash, uint8_t *buf, unsigne /* Command Write SPI Bulk. No idea which write command is used on the * SPI side. */ - ret = usb_control_msg(dediprog_handle, 0x42, 0x30, start % 0x10000, start / 0x10000, - (char *)count_and_cmd, sizeof(count_and_cmd), DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0x42, 0x30, start % 0x10000, start / 0x10000, + (unsigned char *)count_and_cmd, sizeof(count_and_cmd), DEFAULT_TIMEOUT); if (ret != sizeof(count_and_cmd)) { - msg_perr("Command Write SPI Bulk failed, %i %s!\n", ret, - usb_strerror()); + msg_perr("Command Write SPI Bulk failed, %i %s!\n", ret, libusb_error_name(ret)); return 1; } for (i = 0; i < count; i++) { memset(usbbuf, 0xff, sizeof(usbbuf)); memcpy(usbbuf, buf + i * chunksize, chunksize); - ret = usb_bulk_write(dediprog_handle, dediprog_endpoint, - usbbuf, 512, - DEFAULT_TIMEOUT); - if (ret != 512) { - msg_perr("SPI bulk write failed, expected %i, got %i " - "%s!\n", 512, ret, usb_strerror()); + ret = libusb_bulk_transfer(dediprog_handle, dediprog_endpoint, + usbbuf, 512, &transferred, DEFAULT_TIMEOUT); + if ((ret < 0) || (transferred != 512)) { + msg_perr("SPI bulk write failed, expected %i, got %i %s!\n", + 512, ret, libusb_error_name(ret)); return 1; } } @@ -444,23 +478,20 @@ static int dediprog_spi_send_command(struct flashctx *flash, msg_perr("Untested readcnt=%i, aborting.\n", readcnt); return 1; } - - ret = usb_control_msg(dediprog_handle, 0x42, 0x1, 0xff, - readcnt ? 0x1 : 0x0, (char *)writearr, writecnt, - DEFAULT_TIMEOUT); + + ret = libusb_control_transfer(dediprog_handle, 0x42, 0x1, 0xff, readcnt ? 0x1 : 0x0, + (unsigned char *)writearr, writecnt, DEFAULT_TIMEOUT); if (ret != writecnt) { - msg_perr("Send SPI failed, expected %i, got %i %s!\n", - writecnt, ret, usb_strerror()); + msg_perr("Send SPI failed, expected %i, got %i %s!\n", writecnt, ret, libusb_error_name(ret)); return 1; } if (!readcnt) return 0; memset(readarr, 0, readcnt); - ret = usb_control_msg(dediprog_handle, 0xc2, 0x01, 0xbb8, 0x0000, - (char *)readarr, readcnt, DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0xc2, 0x01, 0xbb8, 0x0000, + readarr, readcnt, DEFAULT_TIMEOUT); if (ret != readcnt) { - msg_perr("Receive SPI failed, expected %i, got %i %s!\n", - readcnt, ret, usb_strerror()); + msg_perr("Receive SPI failed, expected %i, got %i %s!\n", readcnt, ret, libusb_error_name(ret)); return 1; } return 0; @@ -470,22 +501,18 @@ static int dediprog_check_devicestring(void) { int ret; int fw[3]; - char buf[0x11]; + unsigned char buf[0x11]; /* Command Prepare Receive Device String. */ memset(buf, 0, sizeof(buf)); - ret = usb_control_msg(dediprog_handle, 0xc3, 0x7, 0x0, 0xef03, buf, - 0x1, DEFAULT_TIMEOUT); - /* The char casting is needed to stop gcc complaining about an always true comparison. */ - if ((ret != 0x1) || (buf[0] != (char)0xff)) { - msg_perr("Unexpected response to Command Prepare Receive Device" - " String!\n"); + ret = libusb_control_transfer(dediprog_handle, 0xc3, 0x7, 0x0, 0xef03, buf, 0x1, DEFAULT_TIMEOUT); + if ((ret != 0x1) || (buf[0] != 0xff)) { + msg_perr("Unexpected response to Command Prepare Receive Device String!\n"); return 1; } /* Command Receive Device String. */ memset(buf, 0, sizeof(buf)); - ret = usb_control_msg(dediprog_handle, 0xc2, 0x8, 0xff, 0xff, buf, - 0x10, DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0xc2, 0x8, 0xff, 0xff, buf, 0x10, DEFAULT_TIMEOUT); if (ret != 0x10) { msg_perr("Incomplete/failed Command Receive Device String!\n"); return 1; @@ -496,7 +523,7 @@ static int dediprog_check_devicestring(void) msg_perr("Device not a SF100!\n"); return 1; } - if (sscanf(buf, "SF100 V:%d.%d.%d ", &fw[0], &fw[1], &fw[2]) != 3) { + if (sscanf((const char *)buf, "SF100 V:%d.%d.%d ", &fw[0], &fw[1], &fw[2]) != 3) { msg_perr("Unexpected firmware version string!\n"); return 1; } @@ -517,13 +544,12 @@ static int dediprog_check_devicestring(void) static int dediprog_command_a(void) { int ret; - char buf[0x1]; + unsigned char buf[0x1]; memset(buf, 0, sizeof(buf)); - ret = usb_control_msg(dediprog_handle, 0xc3, 0xb, 0x0, 0x0, buf, - 0x1, DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0xc3, 0xb, 0x0, 0x0, buf, 0x1, DEFAULT_TIMEOUT); if (ret < 0) { - msg_perr("Command A failed (%s)!\n", usb_strerror()); + msg_perr("Command A failed (%s)!\n", libusb_error_name(ret)); return 1; } if ((ret != 0x1) || (buf[0] != 0x6f)) { @@ -541,13 +567,12 @@ static int dediprog_command_a(void) static int dediprog_command_b(void) { int ret; - char buf[0x3]; + unsigned char buf[0x3]; memset(buf, 0, sizeof(buf)); - ret = usb_control_msg(dediprog_handle, 0xc3, 0x7, 0x0, 0xef00, buf, - 0x3, DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0xc3, 0x7, 0x0, 0xef00, buf, 0x3, DEFAULT_TIMEOUT); if (ret < 0) { - msg_perr("Command B failed (%s)!\n", usb_strerror()); + msg_perr("Command B failed (%s)!\n", libusb_error_name(ret)); return 1; } if ((ret != 0x3) || (buf[0] != 0xff) || (buf[1] != 0xff) || @@ -569,10 +594,9 @@ static int dediprog_command_c(void) { int ret; - ret = usb_control_msg(dediprog_handle, 0x42, 0x4, 0x0, 0x0, NULL, - 0x0, DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0x42, 0x4, 0x0, 0x0, NULL, 0x0, DEFAULT_TIMEOUT); if (ret != 0x0) { - msg_perr("Command C failed (%s)!\n", usb_strerror()); + msg_perr("Command C failed (%s)!\n", libusb_error_name(ret)); return 1; } return 0; @@ -587,17 +611,16 @@ static int dediprog_command_c(void) static int dediprog_command_f(int timeout) { int ret; - char buf[0x1]; + unsigned char buf[0x1]; memset(buf, 0, sizeof(buf)); - ret = usb_control_msg(dediprog_handle, 0xc2, 0x11, 0xff, 0xff, buf, - 0x1, timeout); + ret = libusb_control_transfer(dediprog_handle, 0xc2, 0x11, 0xff, 0xff, buf, 0x1, timeout); /* This check is most probably wrong. Command F always causes a timeout * in the logs, so we should check for timeout instead of checking for * success. */ if (ret != 0x1) { - msg_perr("Command F failed (%s)!\n", usb_strerror()); + msg_perr("Command F failed (%s)!\n", libusb_error_name(ret)); return 1; } return 0; @@ -611,9 +634,9 @@ static int dediprog_command_g(void) { int ret; - ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, 0x03, NULL, 0x0, DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0x42, 0x07, 0x09, 0x03, NULL, 0x0, DEFAULT_TIMEOUT); if (ret != 0x0) { - msg_perr("Command G failed (%s)!\n", usb_strerror()); + msg_perr("Command G failed (%s)!\n", libusb_error_name(ret)); return 1; } return 0; @@ -628,9 +651,9 @@ static int dediprog_command_h(void) { int ret; - ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, 0x05, NULL, 0x0, DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0x42, 0x07, 0x09, 0x05, NULL, 0x0, DEFAULT_TIMEOUT); if (ret != 0x0) { - msg_perr("Command H failed (%s)!\n", usb_strerror()); + msg_perr("Command H failed (%s)!\n", libusb_error_name(ret)); return 1; } return 0; @@ -645,9 +668,9 @@ static int dediprog_command_i(void) { int ret; - ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, 0x06, NULL, 0x0, DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0x42, 0x07, 0x09, 0x06, NULL, 0x0, DEFAULT_TIMEOUT); if (ret != 0x0) { - msg_perr("Command I failed (%s)!\n", usb_strerror()); + msg_perr("Command I failed (%s)!\n", libusb_error_name(ret)); return 1; } return 0; @@ -665,9 +688,9 @@ static int dediprog_command_j(void) { int ret; - ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, 0x07, NULL, 0x0, DEFAULT_TIMEOUT); + ret = libusb_control_transfer(dediprog_handle, 0x42, 0x07, 0x09, 0x07, NULL, 0x0, DEFAULT_TIMEOUT); if (ret != 0x0) { - msg_perr("Command J failed (%s)!\n", usb_strerror()); + msg_perr("Command J failed (%s)!\n", libusb_error_name(ret)); return 1; } return 0; @@ -770,21 +793,18 @@ static int dediprog_shutdown(void *data) if (dediprog_set_spi_voltage(0x0)) return 1; - if (usb_release_interface(dediprog_handle, 0)) { + if (libusb_release_interface(dediprog_handle, 0)) { msg_perr("Could not release USB interface!\n"); return 1; } - if (usb_close(dediprog_handle)) { - msg_perr("Could not close USB device!\n"); - return 1; - } + libusb_close(dediprog_handle); + libusb_exit(usb_ctx); return 0; } /* URB numbers refer to the first log ever captured. */ int dediprog_init(void) { - struct usb_device *dev; char *voltage, *device, *spispeed; int spispeed_idx = 2; int millivolt = 3500; @@ -842,31 +862,29 @@ int dediprog_init(void) free(device); /* Here comes the USB stuff. */ - usb_init(); - usb_find_busses(); - usb_find_devices(); - dev = get_device_by_vid_pid(0x0483, 0xdada, (unsigned int) usedevice); - if (!dev) { + libusb_init(&usb_ctx); + if (!usb_ctx) { + msg_perr("Could not initialize libusb!\n"); + return 1; + } + dediprog_handle = get_device_by_vid_pid_number(0x0483, 0xdada, (unsigned int) usedevice); + if (!dediprog_handle) { msg_perr("Could not find a Dediprog SF100 on USB!\n"); + libusb_exit(usb_ctx); return 1; } - msg_pdbg("Found USB device (%04x:%04x).\n", - dev->descriptor.idVendor, dev->descriptor.idProduct); - dediprog_handle = usb_open(dev); - ret = usb_set_configuration(dediprog_handle, 1); - if (ret < 0) { - msg_perr("Could not set USB device configuration: %i %s\n", - ret, usb_strerror()); - if (usb_close(dediprog_handle)) - msg_perr("Could not close USB device!\n"); + ret = libusb_set_configuration(dediprog_handle, 1); + if (ret != 0) { + msg_perr("Could not set USB device configuration: %i %s\n", ret, libusb_error_name(ret)); + libusb_close(dediprog_handle); + libusb_exit(usb_ctx); return 1; } - ret = usb_claim_interface(dediprog_handle, 0); + ret = libusb_claim_interface(dediprog_handle, 0); if (ret < 0) { - msg_perr("Could not claim USB device interface %i: %i %s\n", - 0, ret, usb_strerror()); - if (usb_close(dediprog_handle)) - msg_perr("Could not close USB device!\n"); + msg_perr("Could not claim USB device interface %i: %i %s\n", 0, ret, libusb_error_name(ret)); + libusb_close(dediprog_handle); + libusb_exit(usb_ctx); return 1; } dediprog_endpoint = 2; -- 1.8.1.1

2 6

FOSDEM deadlines now!
by Carl-Daniel Hailfinger Jan. 13, 2016

Jan. 13, 2016

Hi, we obviously want to participate in FOSDEM. https://fosdem.org/2016/news/2015-09-24-call-for-participation/ ACT NOW! Some deadlines already expired. Some can still be managed. Main track talks: Deadline 2015-10-30 (10 days left) One hour of entertainment, huge audience. Anyone up for the challenge? Stands: Deadline 2015-11-13 (24 days left) I can send in the proposal if I'm not going to be alone there. How many tables do we want for our stand/booth(s)? Who is coming? Lightning talks: Deadline 2015-11-27 (38 days left) Short and to the point. Your 15-minute elevator pitch. Can you sell the project? All deadlines are at 23.59 UTC Developer room proposal: Deadline EXPIRED Maybe some developer room will accept talks/demos from us. Regards, Carl-Daniel

2 3

SST25VF080B: Gigabyte GA-G33M-S2 successfully reflashed
by Александр Трубицын Jan. 3, 2016

Jan. 3, 2016

Hi, Stefan! With best regards, Alexander Trubitsyn

2 1

MX25L4006E: Gigabyte GA-P31DS3L successfully reflashed
by Александр Трубицын Jan. 3, 2016

Jan. 3, 2016

Hi! -- With best regards, Alexander V. Trubitsyn

2 3

FS Esprimo E5730: writing rom images seems to work correctly
by Elmar Stellnberger Dec. 28, 2015

Dec. 28, 2015

Today I was about to try write support for flashrom with the Xi 3650 BIOS and see whether it would work. The two images used for write were not too different (the only difference was a BIOS setting letting you choose between the on-board graphics card and an Nvidia Geforce 9600M GT). Nonetheless it seems to have written (and erased) at least one block of the BIOS ROM correctly. Yours, Elmar P.S. the console screenshot: Proceeding anyway because user forced us to. Found chipset "Intel ICH9M-E". Enabling flash write... OK. Found Winbond flash chip "W25X16" (2048 kB, SPI) at physical address 0xffe00000. Reading flash... done. root@sysresccd /usb/Xi3650-BIOS/flashrom-T6400 % ls intermediate Xi3650-T6400-1.0B-1646-0020.rom Xi3650-T6400-1.0H-1646-0024-IGD-2ndflash.rom root@sysresccd /usb/Xi3650-BIOS/flashrom-T6400 % cmp Xi3650-T6400-1.0H-1646-0024-IGD-2ndflash.rom intermediate/Xi3650-T6400-1.0H-1646-0024-IGD.rom Xi3650-T6400-1.0H-1646-0024-IGD-2ndflash.rom intermediate/Xi3650-T6400-1.0H-1646-0024-IGD.rom differ: char 1575900, line 3706 root@sysresccd /usb/Xi3650-BIOS/flashrom-T6400 % ls intermediate Xi3650-T6400-1.0B-1646-0020.rom Xi3650-T6400-1.0H-1646-0024-IGD-2ndflash.rom root@sysresccd /usb/Xi3650-BIOS/flashrom-T6400 % flashrom -p internal:laptop=force_I_want_a_brick --write intermediate/Xi3650-T6400-1.0H-1646-0024-Nvidia.rom flashrom v0.9.7-r1711 on Linux 3.14.50-std460-amd64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. ======================================================================== WARNING! You seem to be running flashrom on an unsupported laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See the manpage and http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Proceeding anyway because user forced us to. Found chipset "Intel ICH9M-E". Enabling flash write... OK. Found Winbond flash chip "W25X16" (2048 kB, SPI) at physical address 0xffe00000. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. root@sysresccd /usb/Xi3650-BIOS/flashrom-T6400 % flashrom -p internal:laptop=force_I_want_a_brick --write Xi3650-T6400-1.0H-1646-0024-IGD-2ndflash.rom flashrom v0.9.7-r1711 on Linux 3.14.50-std460-amd64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. ======================================================================== WARNING! You seem to be running flashrom on an unsupported laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See the manpage and http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Proceeding anyway because user forced us to. Found chipset "Intel ICH9M-E". Enabling flash write... OK. Found Winbond flash chip "W25X16" (2048 kB, SPI) at physical address 0xffe00000. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. root@sysresccd /usb/Xi3650-BIOS/flashrom-T6400 %

2 7

External programmers
by Carl-Daniel Hailfinger Dec. 25, 2015

Dec. 25, 2015

Hi, I'm trying to find out which external programmers should be supported next. 1. There was talk of an AVR-based new programmer using the serprog protocol on IRC by someone with the nick "coldelectrons", but I have no idea if he/she is reading this mail. IMHO more hardware using the serprog protocol is always a good idea. 2. All those Willem/Sivava variants. People regularly request those, but I don't think anyone in here owns the hardware. 3. RayeR's SPIPGM. I have a preliminary patch which could work, but I don't have the hardware. Will send the patch to the list soon. 4. LPC^2, Milksop, CheapLPC and other programmers from the Xbox modding community. 5. Dozens of SPI programmer hardware projects scattered over the net. Too many to count, and I'm not sure which of them has more than one user. In general, it seems creating a new programmer hardware design is like writing IRC clients: A nice way to get started in the field. I have no problems merging flashrom support for all of them, but I won't implement support for all of them myself. Regards, Carl-Daniel -- http://www.hailfinger.org/

8 13

Macronix Erase/Write Problems
by Adam Clarke Dec. 25, 2015

Dec. 25, 2015

Good morning, I am trying to revive a computer which had a failed BIOS update. I bought a BUS Pirate and started using Flashrom to take a copy of an identical fully working model. Strangely this machine has two chips: MX25L6405D MX25L3205D >From the dump's I have made, I believe the MX25L6405D holds the BIOS and the MX25L3205D possibly holds the ME Firmware. Don't know if this is any use but an output from fptw64 on the working machine shows me the following: C:\FPTw64>fptw64.exe -i Intel (R) Flash Programming Tool. Version: 8.0.10.1464 Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved. Platform: Intel(R) Q77 Express Chipset Reading HSFSTS register... Flash Descriptor: Valid --- Flash Devices Found --- MX25L6405D ID:0xC22017 Size: 8192KB (65536Kb) MX25L3205D ID:0xC22016 Size: 4096KB (32768Kb) --- Flash Image Information -- Signature: VALID Number of Flash Components: 2 Component 1 - 8192KB (65536Kb) Component 2 - 4096KB (32768Kb) Regions: Descriptor - Base: 0x000000, Limit: 0x000FFF BIOS - Base: 0x600000, Limit: 0xBFFFFF ME - Base: 0x005000, Limit: 0x5FFFFF GbE - Base: 0x001000, Limit: 0x004FFF PDR - Not present Master Region Access: CPU/BIOS - ID: 0x0000, Read: 0x0B, Write: 0x0A ME - ID: 0x0000, Read: 0x0D, Write: 0x0C GbE - ID: 0x0118, Read: 0x08, Write: 0x08 Total Accessable SPI Memory: 12288KB, Total Installed SPI Memory : 12288KB I am struggling to properly erase/write to both of these chips so I wondered if you could offer any advise on trying to get this working? These are the errors I am getting on both chips, have tried with both Linux and Windows on each chip and get pretty much the same output: flashrom v0.9.7-r1711 on Linux 3.14.48-std454-amd64 (x86_64) flashrom was built with libpci 3.2.0, GCC 4.8.4, little endian Command line (8 args): flashrom -p buspirate_spi:dev=/dev/ttyUSB0, -c MX25L6405(D) -E -V -o /media/usb/log2.txt Calibrating delay loop... OS timer resolution is 1 usecs, 1456M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 997 us, 10000 myus = 9996 us, 4 myus = 4 us, OK. Initializing buspirate_spi programmer Baud rate is 115200. Detected Bus Pirate hardware v3.a Detected Bus Pirate firmware 6.3 ("v6.3-beta1") Using SPI command set v2. SPI speed is 8MHz Raw bitbang mode version 1 Raw SPI mode version 1 The following protocols are supported: SPI. Probing for Macronix MX25L6405(D), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on buspirate_spi. Chip status register is 0x80. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is set Chip status register: Bit 6 is not set Chip status register: Block Protect 3 (BP3) is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Block protection is disabled. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x00ffff:EFAILED at 0x00001000! Expected=0xff, Found=0x90, failed byte count from 0x00000000-0x0000ffff: 0x3aa8 ERASE FAILED! Reading current flash chip contents... At one point the above was the same output as below that everything was set but still failed on "unsetting lock bits" but I have forgotten to save that output. flashrom was built with GCC 4.9.2, little endian Command line (6 args): flashrom -p buspirate_spi:dev=COM3 -c MX25L3205D/MX25L3208D -E -V Calibrating delay loop... OS timer resolution is 501 usecs, 1771M loops per second, 10 myus = 0 us, 100 myus = 0 us, 1000 myus = 1000 us, 10000 myus = 10008 us, 2004 myus = 2002 us, OK. Initializing buspirate_spi programmer Baud rate is 115200. Detected Bus Pirate hardware v3.a Detected Bus Pirate firmware 6.3 Using SPI command set v2. SPI speed is 8MHz Raw bitbang mode version 1 Raw SPI mode version 1 The following protocols are supported: SPI. Probing for Macronix MX25L3205D/MX25L3208D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 Found Macronix flash chip "MX25L3205D/MX25L3208D" (4096 kB, SPI) on buspirate_spi. Chip status register is 0xff. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is set Chip status register: Bit 6 is set Chip status register: Block Protect 3 (BP3) is set Chip status register: Block Protect 2 (BP2) is set Chip status register: Block Protect 1 (BP1) is set Chip status register: Block Protect 0 (BP0) is set Chip status register: Write Enable Latch (WEL) is set Chip status register: Write In Progress (WIP/BUSY) is set This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Some block protection in effect, disabling... Need to disable the register lock first... Unsetting lock bit(s) failed. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:EFAILED at 0x00000000! Expected=0xff, Found=0xe8, failed byte count from 0x00000000-0x00000fff: 0x1000 ERASE FAILED! Reading current flash chip contents... ^C This is a link to the datasheet for both chips : http://www.macronix.com/Lists/DataSheet/Attachments/2453/MX25L6405D,%203V,%… It mentions something about having to give 9.5v-10.5v to the WP pin so maybe that is the problem? does this mean i would have to externally source this voltage outside of bus pirate to enable write enable properly? Many Thanks

2 1

Can't probe AT26DF321 on OptiPlex 755
by Patrick 'P. J.' McDermott Dec. 25, 2015

Dec. 25, 2015

Hi, I have a Dell OptiPlex 755 USFF which has an Atmel AT26DF321 SPI flash chip (which is like an AT25DF321 and has the same device ID except it doesn't have a HOLD# pin). I've used flashrom to read and write the same chip on another board by ISP using a BeagleBone Black, 10-cm jumper cables, a SOIC clip, and an ATX PSU. However, flashrom with the same ISP setup fails to probe the chip on the OptiPlex. I've tried two different known-working BBBs, different cables, two different Pomona SOIC clips, connecting WP# to 3.3 V, connecting what would be HOLD# on the AT25 to 3.3 V, and different spispeed clock frequencies from 1 kHz to 10 MHz. I've tried powering the chip (and the rest of the board's 3.3-V rail) with a 3.3-V line of the ATX PSU, and I've tried instead powering the whole board with the computer's 12-V PSU. I've also tried running flashrom while holding down the power button to keep the system in reset. Following some advice on <http://flashrom.org/ISP> I even tried removing the DIMMs and CPU. Every time I get only bytes of 0xff from the chip, as in the attached log. In my experience that usually means either the programmer isn't properly connected to the chip or the programmer uses a different data voltage than the chip does. But I've checked and rechecked all of the connections, and I know both the BBB and the AT26DF321 use 3.3-V data signals. Unfortunately there don't seem to be any schematics available for this board (Dell model number 0HX555, ODM model number HX533 A00, ODM might be Asustek or MiTAC). This system does have an Intel Management Engine in the northbridge, but even if that was running I should at least be able to probe the chip and read its contents. Does anyone have any ideas of anything else I could try (short of desoldering the chip from the board) or about what the problem may be? Thanks, -- Patrick "P. J." McDermott http://www.pehjota.net/ Lead Developer, ProteanOS http://www.proteanos.com/

3 4

Support for Rangely Chips with Winboad W25Q64.V tested
by Jeremy Porter Dec. 24, 2015

Dec. 24, 2015

I noticed that both the chip and the chipset show as untested on the wiki. I can confirm that these work, as we use flashrom extensively on our, Netgate RCC-VE 2440, 4860, 8860, and our DFF-2220. systems. (The boards just have differing amounts of Ram/ethernet ports and CPUs) These are based on the Intel Rangely Chipset PCI ID 8086:1f38. So if you want to update the wiki, those can be marked as tested and working. (We've flashed hundreds of systems). ./flashrom -p internal -V flashrom v0.9.8-r1896 on FreeBSD 10.2-RELEASE (amd64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.3.1, LLVM Clang 3.4.1 (tags/RELEASE_34/dot1-final 208032), little endian Command line (3 args): ./flashrom -p internal -V Calibrating delay loop... OS timer resolution is 1 usecs, 600M loops per second, 10 myus = 10 us, 100 myus = 101 us, 1000 myus = 1018 us, 10000 myus = 10066 us, 4 myus = 4 us, OK. Initializing internal programmer Found candidate at: 00000500-00000510 Found coreboot table at 0x00000500. Found candidate at: 00000c00-00000da4 Found coreboot table at 0x00000c00. coreboot table found at 0x7fbf0c00. coreboot header(24) checksum: 913c table(420) checksum: db66 entries: 11 Vendor ID: Intel, part ID: Mohon Peak Using Internal DMI decoder. DMI string chassis-type: "Desktop" DMI string system-manufacturer: "ADI Engineering" DMI string system-product-name: "RCC-VE" DMI string system-version: "1.0" DMI string baseboard-manufacturer: "ADI Engineering" DMI string baseboard-product-name: "RCC-VE" DMI string baseboard-version: "1.0" Found chipset "Intel Avoton/Rangeley" with PCI ID 8086:1f38. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... Root Complex Register Block address = 0xfed1c000 GCS = 0x40000c01: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI) Top Swap: not enabled 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode enabled 0xff600000/0xff200000 FWH decode enabled 0xff500000/0xff100000 FWH decode enabled 0xff400000/0xff000000 FWH decode enabled Maximum FWH chip size: 0x100000 bytes SPI_BASE_ADDRESS = 0xfed01000 SPI Read Configuration: prefetching enabled, caching enabled, BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled 0x04: 0x6000 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=0, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0 Programming OPCODES... done 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x50: 0x00001f1f (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x1f, BRRA 0x1f 0x54: 0x000f0000 FREG0: Flash Descriptor region (0x00000000-0x0000ffff) is read-write. 0x58: 0x07ff0010 FREG1: BIOS region (0x00010000-0x007fffff) is read-write. 0x90: 0x00 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0x91: 0xf84900 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=9, SME=0, SCF=0 0x94: 0x5006 (PREOP) 0x96: 0x463b (OPTYPE) 0x98: 0x05d80302 (OPMENU) 0x9C: 0xc79f0190 (OPMENU+4) 0xC4: 0x00800000 (LVSCC) LVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x0, VCL=1 0xC8: 0x00000000 (UVSCC) UVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x0 0xD0: 0x00000000 (FPB) OK. The following protocols are supported: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25LQ16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25LQ032/A25LQ32A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25LQ64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DL081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DL161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25F512, 64 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F512A, 64 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25F1024(A), 128 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F2048, 256 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F4096, 512 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB321E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ESMT F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ESMT F25L32PA, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25P05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25P10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25P20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25P40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25P32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25P64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25QH64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25QH128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25LQ40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25LQ80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25LQ16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25LQ32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25LQ64(B), 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25LQ128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q20(B), 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q40(B), 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q80(B), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q16(B), 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q32(B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q64(B), 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q128B, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25T80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F160S33B8, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F160S33T8, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F320S33B8, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F320S33T8, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F640S33B8, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F640S33T8, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX23L1654, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX23L3254, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX23L6454, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX23L12854, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L512(E)/MX25V512(C), 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1005(C)/MX25L1006E, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L2005(C)/MX25L2006E, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L4005(A/C)/MX25L4006E, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L8005/MX25L8006E/MX25L8008E/MX25V8005, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1605A/MX25L1606E/MX25L1608E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1605D/MX25L1608D/MX25L1673E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3205(A), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3205D/MX25L3208D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3206E/MX25L3208E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3273E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L6405D, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L6406E/MX25L6408E, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L12805D, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L12835F/MX25L12845E/MX25L12865E, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25U1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25U3235E/F, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25U6435E/F, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25U12835F, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L6495F, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P20-old, 256 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PX80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M45PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M45PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M45PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M45PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M45PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q032..1E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q032..3E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q064..1E, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q064..3E, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q128..1E, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q128..3E, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Nantronics N25S10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Nantronics N25S20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Nantronics N25S40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Nantronics N25S80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Nantronics N25S16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LD256C, 32 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LD512(C), 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LD010(C), 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LD020(C), 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LD040(C), 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LQ020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LQ040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LQ080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LQ016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LQ032C, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV512(A), 64 kB: probe_spi_res2: id1 0x16, id2 0x16 Probing for PMC Pm25LV010, 128 kB: probe_spi_res2: id1 0x16, id2 0x16 Probing for PMC Pm25LV010A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Sanyo LE25FW106, 128 kB: probe_spi_res2: id1 0x16, id2 0x16 Probing for Sanyo LE25FW406A, 512 kB: probe_spi_res2: id1 0x16, id2 0x16 Probing for Sanyo LE25FU406B, 512 kB: probe_spi_res2: id1 0x16, id2 0x16 Probing for Sanyo LE25FW203A, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Sanyo LE25FW403A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Sanyo LE25FW418A, 512 kB: probe_spi_res2: id1 0x16, id2 0x16 Probing for Sanyo LE25FW806, 1024 kB: probe_spi_res2: id1 0x16, id2 0x16 Probing for Sanyo LE25FW808, 1024 kB: probe_spi_res2: id1 0x16, id2 0x16 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL032A/P, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL064A/P, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL204K, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL208K, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL116K/S25FL216K, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL132K, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL164K, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL127S-64kB, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL127S-256kB, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL128P......0, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL128P......1, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL128S......0, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL128S......1, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL129P......0, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL129P......1, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25LF020A, 256 kB: probe_spi_rems: id1 0xef, id2 0x16 Probing for SST SST25LF040A, 512 kB: probe_spi_res2: id1 0x16, id2 0x16 Probing for SST SST25LF080(A), 1024 kB: probe_spi_res2: id1 0x16, id2 0x16 Probing for SST SST25VF512(A), 64 kB: probe_spi_rems: id1 0xef, id2 0x16 Probing for SST SST25VF010(A), 128 kB: probe_spi_rems: id1 0xef, id2 0x16 Probing for SST SST25VF020, 256 kB: probe_spi_rems: id1 0xef, id2 0x16 Probing for SST SST25VF020B, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF040, 512 kB: probe_spi_rems: id1 0xef, id2 0x16 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xef, id2 0x16 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25WF512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25WF010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25WF020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25WF040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25WF080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q40.V, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q80.V, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q16.V, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q32.V, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q64.V, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Found Winbond flash chip "W25Q64.V" (8192 kB, SPI) mapped at physical address 0x00000000ff800000. Chip status register is 0x00. Probing for Winbond W25Q128.V, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q20.W, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q40.W, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q80.W, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q16.W, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q32.W, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q64.W, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Unknown SFDP-capable chip, 0 kB: Parsing JEDEC flash parameter table... done. Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond unknown Winbond (ex Nexcom) SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xef, id2 0x16 Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x8b, id2 0xcf, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH00B4, 512 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH004, 512 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x8b, id2 0xcf, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x8b, id2 0xcf, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x69, id2 0x6c, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x8b, id2 0xcf, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x8b, id2 0xcf, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Found Winbond flash chip "W25Q64.V" (8192 kB, SPI). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). No operations were specified. Restoring MMIO space at 0x8007bb09c Restoring MMIO space at 0x8007bb098 Restoring MMIO space at 0x8007bb096 Restoring MMIO space at 0x8007bb094 root@4gtest:~/flashrom #

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SST49LF040B: ASUS M2N-E-SLI successfully reflashed
by Александр Трубицын Dec. 24, 2015

Dec. 24, 2015

Hello, Stefan! With best regards, Alexander V. Trubitsyn

2 1

MX25L8006E: Gigabyte EP31-DS3L rev 1.0 sucessfully reflashed
by Александр Трубицын Dec. 24, 2015

Dec. 24, 2015

Hi, Stefan! -- With best regards, Alexander V. Trubitsyn

2 1

HP Probook 6450b: programmer initialization failed
by Александр Трубицын Dec. 24, 2015

Dec. 24, 2015

Hi! I try to read flash from friends of mine notebook HP Probook 6450b and have no sucess on it. -- With best regards, Alexander V. Trubitsyn

2 1

W25X80: ASUS P5K SE sucessfully reflashed
by Александр Трубицын Dec. 24, 2015

Dec. 24, 2015

Hi! -- With best regards, Alexander V. Trubitsyn

2 1

W25Q64.V: flashrom can't read flash on ASUS P8H77-V LE
by Александр Трубицын Dec. 23, 2015

Dec. 23, 2015

Hi! -- With best regards, Alexander V. Trubitsyn

2 1

flashrom can successfully read the BIOS image of my Amilo Xi3650 laptop
by Elmar Stellnberger Dec. 17, 2015

Dec. 17, 2015

Lately I have tried > flashrom -p internal:laptop=force_I_want_a_brick --read Xi3650.rom on my Fujitsu Siemens Amilo Xi 3650 laptop and it has worked quite well. ... Found chipset "Intel ICH9M-E". Found Winbond flash chip "W25X16" (2048 kB, SPI) at physical address 0xffe00000. > sha256sum Xi3650.rom 8c5095d38bffe9b87d481ba8da395e48d9dcfadd43176979fd69e5da249b3763 Xi3650.rom BIOS (according to dmidecode) is Vendor: Phoenix Version: 1.0H-1646-0024 Release Date: 04/15/2010 I would love to see it under 'supported boards' in the future. More information can be found in the attachements.

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[PATCH] Add support for SST25WF080B 1 MB flash.
by Ben Gardner Nov. 22, 2015

Nov. 22, 2015

Apart from the JEDEC ID (621614) the difference from the SST25WF080 is that it lacks op codes 0xAD (AAI Word program) and 0x52 (32K erase). Tested under Linux with spidev. Signed-off-by: Ben Gardner <bgardner(a)wabtec.com> --- flashchips.c | 35 +++++++++++++++++++++++++++++++++++ flashchips.h | 3 ++- 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/flashchips.c b/flashchips.c index 8b5d1ec..b71bd2c 100644 --- a/flashchips.c +++ b/flashchips.c @@ -11803,6 +11803,41 @@ const struct flashchip flashchips[] = { { .vendor = "SST", + .name = "SST25WF080B", + .bustype = BUS_SPI, + .manufacture_id = SST_ID_62, + .model_id = SST_SST25WF080B, + .total_size = 1024, + .page_size = 256, + .feature_bits = FEATURE_WRSR_EITHER, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_sst25, /* *does* have a BP3 but it is useless */ + .unlock = spi_disable_blockprotect_bp3_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {1650, 1950}, + }, + + { + .vendor = "SST", .name = "SST28SF040A", .bustype = BUS_PARALLEL, .manufacture_id = SST_ID, diff --git a/flashchips.h b/flashchips.h index 07ae49d..d6b2b8d 100644 --- a/flashchips.h +++ b/flashchips.h @@ -659,6 +659,7 @@ * byte of device ID is related to log(bitsize) at least for some chips. */ #define SST_ID 0xBF /* SST */ +#define SST_ID_62 0x62 /* SST */ #define SST_SST25LF020_REMS 0x43 /* REMS or RES opcode */ #define SST_SST25WF512 0x2501 #define SST_SST25WF010 0x2502 @@ -669,7 +670,7 @@ * IDs and were not spotted in the wild yet. Their datasheets show a 4 byte long response w/o a vendor ID. */ #define SST_SST25WF020A /* 0x62 0x16 0x12 0x00 */ #define SST_SST25WF040B /* 0x62 0x16 0x13 0x00 */ -#define SST_SST25WF080B /* 0x62 0x16 0x14 0x00 */ +#define SST_SST25WF080B 0x1614 /* 0x62 0x16 0x14 0x00 */ #define SST_SST25VF512_REMS 0x48 /* REMS or RES opcode, same as SST25VF512A */ #define SST_SST25VF010_REMS 0x49 /* REMS or RES opcode, same as SST25VF010A */ #define SST_SST25VF020_REMS 0x43 /* REMS or RES opcode, same as SST25LF020A */ -- 1.9.1 This email and any attachments are only for use by the intended recipient(s) and may contain legally privileged, confidential, proprietary or otherwise private information. Any unauthorized use, reproduction, dissemination, distribution or other disclosure of the contents of this e-mail or its attachments is strictly prohibited. If you have received this email in error, please notify the sender immediately and delete the original. Neither this information block, the typed name of the sender, nor anything else in this message is intended to constitute an electronic signature unless a specific statement to the contrary is included in this message.

3 2

Asus M2N-MX/DVI2
by Лисовой Игорь Nov. 21, 2015

Nov. 21, 2015

2 2

Re: [flashrom] flashrom on PowerPC
by Stefan Tauner Nov. 20, 2015

Nov. 20, 2015

On Wed, 27 Jul 2011 18:20:19 +0200 Mattias Mattsson <vitplister(a)gmail.com> wrote: > Hi all, > > I was able to run flashrom under Linux on PPC (big endian) hardware > with two small modifications in internal.c and processor_enable.c (see > attached patch). Not sure if this is the right way to do it but it > seems to work for me. > i am resending this patch (unchanged) because patchwork did not pick it up correctly. please do send one patch per mail only in the future until we have something really working. :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

[PATCH 1/3] 128 bytes write granularity support
by Paul Kocialkowski Nov. 11, 2015

Nov. 11, 2015

Some chips such as the ENE KB9012 internal flash require a write granularity of 128 bytes. Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- flash.h | 1 + flashrom.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/flash.h b/flash.h index 2c2839f..24861ba 100644 --- a/flash.h +++ b/flash.h @@ -85,6 +85,7 @@ enum write_granularity { write_gran_1bit, /* Each bit can be cleared individually. */ write_gran_1byte, /* A byte can be written once. Further writes to an already written byte cause * its contents to be either undefined or to stay unchanged. */ + write_gran_128bytes, /* If less than 128 bytes are written, the unwritten bytes are undefined. */ write_gran_264bytes, /* If less than 264 bytes are written, the unwritten bytes are undefined. */ write_gran_512bytes, /* If less than 512 bytes are written, the unwritten bytes are undefined. */ write_gran_528bytes, /* If less than 528 bytes are written, the unwritten bytes are undefined. */ diff --git a/flashrom.c b/flashrom.c index d51a44c..c9c7e31 100644 --- a/flashrom.c +++ b/flashrom.c @@ -781,6 +781,9 @@ int need_erase(const uint8_t *have, const uint8_t *want, unsigned int len, enum break; } break; + case write_gran_128bytes: + result = need_erase_gran_bytes(have, want, len, 128); + break; case write_gran_256bytes: result = need_erase_gran_bytes(have, want, len, 256); break; @@ -847,6 +850,9 @@ static unsigned int get_next_write(const uint8_t *have, const uint8_t *want, uns case write_gran_1byte_implicit_erase: stride = 1; break; + case write_gran_128bytes: + stride = 128; + break; case write_gran_256bytes: stride = 256; break; -- 1.9.1

4 16

[PATCH v2 1/2] Flag-driven erased bit value
by Paul Kocialkowski Nov. 11, 2015

Nov. 11, 2015

Most flash chips are erased to ones and programmed to zeros. However, some other flash chips, such as the ENE KB9012 internal flash, work the opposite way. Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- flash.h | 5 ++++- flashrom.c | 39 +++++++++++++++++++++------------------ 2 files changed, 25 insertions(+), 19 deletions(-) diff --git a/flash.h b/flash.h index 24861ba..55d02de 100644 --- a/flash.h +++ b/flash.h @@ -123,6 +123,9 @@ enum write_granularity { #define FEATURE_WRSR_EITHER (FEATURE_WRSR_EWSR | FEATURE_WRSR_WREN) #define FEATURE_OTP (1 << 8) #define FEATURE_QPI (1 << 9) +#define FEATURE_ERASED_ZERO (1 << 10) + +#define ERASED_VALUE(flash) ((flash->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff) enum test_state { OK = 0, @@ -275,7 +278,7 @@ int probe_flash(struct registered_master *mst, int startchip, struct flashctx *f int read_flash_to_file(struct flashctx *flash, const char *filename); char *extract_param(const char *const *haystack, const char *needle, const char *delim); int verify_range(struct flashctx *flash, const uint8_t *cmpbuf, unsigned int start, unsigned int len); -int need_erase(const uint8_t *have, const uint8_t *want, unsigned int len, enum write_granularity gran); +int need_erase(const uint8_t *have, const uint8_t *want, unsigned int len, enum write_granularity gran, const uint8_t erased_value); void print_version(void); void print_buildinfo(void); void print_banner(void); diff --git a/flashrom.c b/flashrom.c index c9c7e31..bd8ef3f 100644 --- a/flashrom.c +++ b/flashrom.c @@ -673,12 +673,13 @@ int check_erased_range(struct flashctx *flash, unsigned int start, { int ret; uint8_t *cmpbuf = malloc(len); + const uint8_t erased_value = ERASED_VALUE(flash); if (!cmpbuf) { msg_gerr("Could not allocate memory!\n"); exit(1); } - memset(cmpbuf, 0xff, len); + memset(cmpbuf, erased_value, len); ret = verify_range(flash, cmpbuf, start, len); free(cmpbuf); return ret; @@ -731,7 +732,7 @@ out_free: } /* Helper function for need_erase() that focuses on granularities of gran bytes. */ -static int need_erase_gran_bytes(const uint8_t *have, const uint8_t *want, unsigned int len, unsigned int gran) +static int need_erase_gran_bytes(const uint8_t *have, const uint8_t *want, unsigned int len, unsigned int gran, const uint8_t erased_value) { unsigned int i, j, limit; for (j = 0; j < len / gran; j++) { @@ -741,7 +742,7 @@ static int need_erase_gran_bytes(const uint8_t *have, const uint8_t *want, unsig continue; /* have needs to be in erased state. */ for (i = 0; i < limit; i++) - if (have[j * gran + i] != 0xff) + if (have[j * gran + i] != erased_value) return 1; } return 0; @@ -761,7 +762,7 @@ static int need_erase_gran_bytes(const uint8_t *have, const uint8_t *want, unsig * @gran write granularity (enum, not count) * @return 0 if no erase is needed, 1 otherwise */ -int need_erase(const uint8_t *have, const uint8_t *want, unsigned int len, enum write_granularity gran) +int need_erase(const uint8_t *have, const uint8_t *want, unsigned int len, enum write_granularity gran, const uint8_t erased_value) { int result = 0; unsigned int i; @@ -776,31 +777,31 @@ int need_erase(const uint8_t *have, const uint8_t *want, unsigned int len, enum break; case write_gran_1byte: for (i = 0; i < len; i++) - if ((have[i] != want[i]) && (have[i] != 0xff)) { + if ((have[i] != want[i]) && (have[i] != erased_value)) { result = 1; break; } break; case write_gran_128bytes: - result = need_erase_gran_bytes(have, want, len, 128); + result = need_erase_gran_bytes(have, want, len, 128, erased_value); break; case write_gran_256bytes: - result = need_erase_gran_bytes(have, want, len, 256); + result = need_erase_gran_bytes(have, want, len, 256, erased_value); break; case write_gran_264bytes: - result = need_erase_gran_bytes(have, want, len, 264); + result = need_erase_gran_bytes(have, want, len, 264, erased_value); break; case write_gran_512bytes: - result = need_erase_gran_bytes(have, want, len, 512); + result = need_erase_gran_bytes(have, want, len, 512, erased_value); break; case write_gran_528bytes: - result = need_erase_gran_bytes(have, want, len, 528); + result = need_erase_gran_bytes(have, want, len, 528, erased_value); break; case write_gran_1024bytes: - result = need_erase_gran_bytes(have, want, len, 1024); + result = need_erase_gran_bytes(have, want, len, 1024, erased_value); break; case write_gran_1056bytes: - result = need_erase_gran_bytes(have, want, len, 1056); + result = need_erase_gran_bytes(have, want, len, 1056, erased_value); break; case write_gran_1byte_implicit_erase: /* Do not erase, handle content changes from anything->0xff by writing 0xff. */ @@ -1424,6 +1425,7 @@ static int erase_and_write_block_helper(struct flashctx *flash, unsigned int starthere = 0, lenhere = 0; int ret = 0, skip = 1, writecount = 0; enum write_granularity gran = flash->chip->gran; + const uint8_t erased_value = ERASED_VALUE(flash); /* curcontents and newcontents are opaque to walk_eraseregions, and * need to be adjusted here to keep the impression of proper abstraction @@ -1431,7 +1433,7 @@ static int erase_and_write_block_helper(struct flashctx *flash, curcontents += start; newcontents += start; msg_cdbg(":"); - if (need_erase(curcontents, newcontents, len, gran)) { + if (need_erase(curcontents, newcontents, len, gran, erased_value)) { msg_cdbg("E"); ret = erasefn(flash, start, len); if (ret) @@ -1441,7 +1443,7 @@ static int erase_and_write_block_helper(struct flashctx *flash, return -1; } /* Erase was successful. Adjust curcontents. */ - memset(curcontents, 0xff, len); + memset(curcontents, erased_value, len); skip = 0; } /* get_next_write() sets starthere to a new value after the call. */ @@ -1938,6 +1940,7 @@ int doit(struct flashctx *flash, int force, const char *filename, int read_it, int ret = 0; unsigned long size = flash->chip->total_size * 1024; int read_all_first = 1; /* FIXME: Make this configurable. */ + const uint8_t erased_value = ERASED_VALUE(flash); if (chip_safety_check(flash, force, read_it, write_it, erase_it, verify_it)) { msg_cerr("Aborting.\n"); @@ -1964,15 +1967,15 @@ int doit(struct flashctx *flash, int force, const char *filename, int read_it, msg_gerr("Out of memory!\n"); exit(1); } - /* Assume worst case: All bits are 0. */ - memset(oldcontents, 0x00, size); + /* Assume worst case: All bits are not erased. */ + memset(oldcontents, ~erased_value, size); newcontents = malloc(size); if (!newcontents) { msg_gerr("Out of memory!\n"); exit(1); } - /* Assume best case: All bits should be 1. */ - memset(newcontents, 0xff, size); + /* Assume best case: All bits should be erased. */ + memset(newcontents, erased_value, size); /* Side effect of the assumptions above: Default write action is erase * because newcontents looks like a completely erased chip, and * oldcontents being completely 0x00 means we have to erase everything -- 2.4.3

2 5

Re: [flashrom] Flash chip/chipset not found
by Carl-Daniel Hailfinger Nov. 2, 2015

Nov. 2, 2015

Hi Mark, would it be possible for you to generate a log file using the additional parameter --output logfile.txt when doing a read of the flash chip, then send that log file to us? That would help us to finally merge support for the VT8251 chipset in your point-of-sale IBM/Toshiba AnyPlace Kiosk Model 48xx series. We have a strict rule that flashrom must be 100% reliable and thus we keep log files for any newly supported/tested chipset around for reference. Your log file would be used as reference for VT8251. That said, it would be very interesting to know where the settings are actually stored. Have you looked into the top 128 bytes of NVRAM? Maybe there is another flash chip? Is there any way to trace what the save/restore tool does (i.e. does it run on Linux)? Regards, Carl-Daniel On 28.10.2015 23:25, Rowlinson Mark wrote: > Hi Carl-Daniel, > > That change does allow the chipset to be recognised and it will write out the ROM. It seems to be the BIOS code only (no settings) as it doesn't change if I change any settings within the BIOS. > > I've been directed to a save/restore utility that comes on the BIOS update image and it seems the last version actually accesses the data I'm interested in so I'm investigating this route at the moment. > > Best Regards, > Mark Rowlinson > > -----Original Message----- > From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006@gmx.net] > Sent: 24 October 2015 09:22 > To: Rowlinson Mark <Mark.Rowlinson(a)uk.fujitsu.com>; flashrom(a)flashrom.org > Subject: Re: [flashrom] Flash chip/chipset not found > > Hi Mark, > > this is a VIA VT8251 PCI to ISA Bridge you're using. > > I think Stefan Tauner (in CC) already was discussing something similar here: > http://www.flashrom.org/pipermail/flashrom/2012-July/009552.html > That email even has a patch attached. > > > On 22.10.2015 22:24, Rowlinson Mark wrote: >> Thanks for the swift response, I have attached output from the command requested. >> >> The device in question is an IBM (now Toshiba) AnyPlace Kiosk Model 4838-310. The models we have are a mixture of 4838-310 and 4838-330 and support documentation refers to them as 4838-3xx. > Heh, would be fun to add this to our tests. > > Regards, > Carl-Daniel >

2 1

SOIC8 test clip - cant write to BIOS SPI flash chip
by Robert Brown Nov. 1, 2015

Nov. 1, 2015

Unfortunately I don't have any soldering tools or experience, so if you could give an advice about ISP programming (In-System-Programming/In-Situ-Programming) , it will be super helpful! I teardown a bricked laptop, removed AC power, laptop's power battery, and even a small CMOS battery, and now I am trying to write a working BIOS image to laptop's SPI flash chip using a SOIC8 test clip. But here is a problem: I could read a dump from this BIOS chip without problems, however it fails when I am trying to write - so the contents of BIOS flash chip are remaining unchanged. Luckily I found out this helpful wiki page - http://flashrom.org/ISP , which describes common problems with this ISP method of flashing, as well as gives 3 hints for solution! Sadly this page is currently down, so here is a screenshot: http://i.imgur.com/SJEYHR2.png 1. - tried to make shorter wires, less than 10cm as they recommend - it did not help 2. - soldering is out of possibility, cant do it, and also: wires are already short and they are good quality (pure copper) 3. - This hint looks more promising, but I need help in understanding this piece of information: "disconnect Vcc from the programmer and power it with its normal PSU" If I understand correctly, by Vcc they mean Vcc pin of the BIOS flash chip. But if I disconnect Vcc from the programmer, what is "normal PSU" which should power this Vcc pin? Should I connect to motherboard a laptop's power battery, or small CMOS battery, or AC adapter of laptop, so that this Vcc pin would be powered by them, or it is forbidden to do it while using SPI programmer in the same time? Or its better to try to power Vcc of flash chip from "USB to TTL" adapter - which has this 3V3 (3.3V) voltage pin? Yours faithfully, Robert Brown _______________________________________________________________ Get the Free email that has everyone talking at <a href=http://www.mail2world.com target=new>http://www.mail2world.com</a> Unlimited Email Storage POP3 Calendar SMS Translator Much More!

3 3

[PATCH] Add (implicit) support for musl libc.
by Stefan Tauner Oct. 31, 2015

Oct. 31, 2015

This is mostly achieved by fixing or refining the inclusion of header files and replacing glibc-specific ifdefs with more generic ones. - <sys/io.h>: Contains iopl(2) and x86 I/O port access functions (inb, outb etc). Generally Linux-specific but also availble on debian/kFreeBSD. Provided by glibc as well as musl and uclibc. Include it if we are running Linux or if glibc is detected. - <sys/fcntl.h>: should be (and is) replaced by <fcntl.h> (without the "sys" prefix). - <linux/spi/spidev.h>: Does not include all necessary headers, namely _IOC_SIZEBITS that is used in the definition of SPI_MSGSIZE is not brought in via <linux/ioctl.h> but instead we relied so far on glibc's including it via <sys/ioctl.h>. Change that to explicitly including <linux/ioctl.h>. - <endian.h>: Would also be available in musl but there is no easy way to detect it so we do not try yet. The bug report and initial patches were Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou(a)trabucayre.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- New version because the sys/io.h change was actually breaking Debian/kFreeBSD! Moved it down where all the IN[BWL]/OUT[BWL] definitions are. hwaccess.h | 14 ++++++++------ linux_spi.c | 5 +++-- 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/hwaccess.h b/hwaccess.h index 3e46192..390f0e4 100644 --- a/hwaccess.h +++ b/hwaccess.h @@ -26,12 +26,6 @@ #include "platform.h" -#if IS_X86 -#if defined(__GLIBC__) -#include <sys/io.h> -#endif -#endif - #if NEED_PCI == 1 /* * libpci headers use the variable name "index" which triggers shadowing @@ -115,6 +109,7 @@ #if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__) /* Nonstandard libc-specific macros for determining endianness. */ +/* musl provides an endian.h as well... but it can not be detected from within C. */ #if defined(__GLIBC__) #include <endian.h> #if BYTE_ORDER == LITTLE_ENDIAN @@ -204,6 +199,13 @@ cpu_to_be(64) #if NEED_PCI == 1 #if IS_X86 +/* sys/io.h provides iopl(2) and x86 I/O port access functions (inb, outb etc). + * It is included in glibc (thus available also on debian/kFreeBSD) but also in other libcs that mimic glibc, + * e.g. musl and uclibc. */ +#if defined(__linux__) || defined(__GLIBC__) +#include <sys/io.h> +#endif + #define __FLASHROM_HAVE_OUTB__ 1 /* for iopl and outb under Solaris */ diff --git a/linux_spi.c b/linux_spi.c index 26725e1..19b4965 100644 --- a/linux_spi.c +++ b/linux_spi.c @@ -22,13 +22,14 @@ #include <stdio.h> #include <string.h> #include <stdlib.h> -#include <sys/fcntl.h> +#include <fcntl.h> #include <errno.h> #include <ctype.h> #include <unistd.h> +#include <sys/ioctl.h> #include <linux/types.h> #include <linux/spi/spidev.h> -#include <sys/ioctl.h> +#include <linux/ioctl.h> #include "flash.h" #include "chipdrivers.h" #include "programmer.h" -- Kind regards, Stefan Tauner

1 0

[PATCH 1/2] Add missing header for musl compatibility
by Gwenhael Goavec-Merou Oct. 30, 2015

Oct. 30, 2015

From: Gwenhael Goavec-Merou <gwenhael.goavec-merou(a)trabucayre.com> According to : http://autobuild.buildroot.net/results/3de/3de936d9be79e151e66af15193084d82… linux/ioctl.h header must be included in linux_spi.c to obtain missing _IOC_SIZEBITS. Patch based on : http://git.buildroot.net/buildroot/commit/package/c-periphery/0001-Add-miss… Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou(a)trabucayre.com> --- linux_spi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/linux_spi.c b/linux_spi.c index 26725e1..8d72420 100644 --- a/linux_spi.c +++ b/linux_spi.c @@ -28,6 +28,7 @@ #include <unistd.h> #include <linux/types.h> #include <linux/spi/spidev.h> +#include <linux/ioctl.h> #include <sys/ioctl.h> #include "flash.h" #include "chipdrivers.h" -- 2.4.9

3 6

Re: [flashrom] Flash chip/chipset not found
by Carl-Daniel Hailfinger Oct. 28, 2015

Oct. 28, 2015

Hi Mark, this is a VIA VT8251 PCI to ISA Bridge you're using. I think Stefan Tauner (in CC) already was discussing something similar here: http://www.flashrom.org/pipermail/flashrom/2012-July/009552.html That email even has a patch attached. On 22.10.2015 22:24, Rowlinson Mark wrote: > Thanks for the swift response, I have attached output from the command requested. > > The device in question is an IBM (now Toshiba) AnyPlace Kiosk Model 4838-310. The models we have are a mixture of 4838-310 and 4838-330 and support documentation refers to them as 4838-3xx. Heh, would be fun to add this to our tests. Regards, Carl-Daniel

2 2

CHIPSET: alix 3d3
by John Vacek Oct. 27, 2015

Oct. 27, 2015

Proceeding anyway because user forced us to. Found chipset "AMD CS5536". Enabling flash write... OK. WARNING: unexpected second chipset match: "AMD CS5536" ignoring, please report lspci and board URL to flashrom(a)flashrom.org with 'CHIPSET: your board name' in the subject line. Found AMIC flash chip "A49LF040A" (512 kB, LPC) at physical address 0xfff80000. No operations were specified. http://www.pcengines.ch/alix3d3.htm root@kali-alix:~# lspci -nn 00:01.0 Host bridge [0600]: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge [1022:2080] (rev 33) 00:01.1 VGA compatible controller [0300]: Advanced Micro Devices [AMD] Geode LX Video [1022:2081] 00:01.2 Entertainment encryption device [1010]: Advanced Micro Devices [AMD] Geode LX AES Security Block [1022:2082] 00:09.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96) 00:0c.0 SATA controller [0106]: Silicon Image, Inc. SiI 3512 [SATALink/SATARaid] Serial ATA Controller [1095:3512] (rev 01) 00:0e.0 Network controller [0280]: Broadcom Corporation BCM4306 802.11a/b/g [14e4:4324] (rev 02) 00:0f.0 ISA bridge [0601]: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA [1022:2090] (rev 03) 00:0f.2 IDE interface [0101]: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE [1022:209a] (rev 01) 00:0f.3 Multimedia audio controller [0401]: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio [1022:2093] (rev 01) 00:0f.4 USB controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC [1022:2094] (rev 02) 00:0f.5 USB controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC [1022:2095] (rev 02)

1 0

Re: [flashrom] Flash chip/chipset not found
by Carl-Daniel Hailfinger Oct. 22, 2015

Oct. 22, 2015

Hi Mark, On 21.10.2015 16:18, Rowlinson Mark wrote: > I have a 32bit touch screen device running CentOS 5.2 which has some of its BIOS settings accessible in /dev/nvram and others elsewhere else (that's why I've been loooking at flashrom). > I have tried later distributions (CentOS 6.7 and the System Rescue CD) and they both report the following: > [root@server ~]# /var/tmp/flashrom-0.9.8/flashrom -p internal > flashrom v0.9.8-r1888 on Linux 2.6.32-573.el6.i686 (i686) > [...] > WARNING: No chipset found. Flash detection will most likely fail. > No EEPROM/flash device found. It seems we have to add some PCI IDs to our southbridge table. Do you have an exact name of the machine in question? > What information is needed to identify the chipset in use so support can be added for these devices? (as root) lspci -nnvvvxxx That should be sufficient for us to find out the southbridge and some of its settings. Regards, Carl-Daniel

2 1

[RFC PATCH] add support for N25Q256
by Cédric Le Goater Oct. 22, 2015

Oct. 22, 2015

I needed to reflash a N25Q256 on a host system and hacked flashrom to make this work. For this, I used the 4-Bytes address support developed by Boris Baykov. This is why the patch is an RFC. The whole patchset is available under github here: https://github.com/legoater/flashrom I can help in getting this patchset merged but do the comments in : http://patchwork.coreboot.org/patch/4272/ need to be all addressed or can we rework a bit the patchset to merge the main changes separately : - 4-bytes addressing - W25Q256.V support - SFDP - Progress visualization - ... Tested under Linux with spidev. Signed-off-by: Cédric Le Goater <clg(a)fr.ibm.com> --- flashchips.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) Index: flashrom.git/flashchips.c =================================================================== --- flashrom.git.orig/flashchips.c +++ flashrom.git/flashchips.c @@ -9330,6 +9330,48 @@ const struct flashchip flashchips[] = { }, { + .vendor = "Micron/Numonyx/ST", + .name = "N25Q256..3E", /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q256__3E, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI + | FEATURE_4BA_SUPPORT, + .four_bytes_addr_funcs = + { + .enter_4ba = spi_enter_4ba_b7_we, /* enter 4-bytes addressing mode by CMD B7 + WREN */ + .read_nbyte = spi_nbyte_read_4ba_direct, /* read directly from any mode, no need to enter 4ba */ + .program_byte = spi_byte_program_4ba, /* write from 4-bytes addressing mode */ + .program_nbyte = spi_nbyte_program_4ba /* write from 4-bytes addressing mode */ + }, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192 } }, + .block_erase = spi_block_erase_20_4ba, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8_4ba, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { .vendor = "MoselVitelic", .name = "V29C51000B", .bustype = BUS_PARALLEL,

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Flash chip/chipset not found
by Rowlinson Mark Oct. 21, 2015

Oct. 21, 2015

Hi, I have a 32bit touch screen device running CentOS 5.2 which has some of its BIOS settings accessible in /dev/nvram and others elsewhere else (that's why I've been loooking at flashrom). I have tried later distributions (CentOS 6.7 and the System Rescue CD) and they both report the following: [root@server ~]# /var/tmp/flashrom-0.9.8/flashrom -p internal flashrom v0.9.8-r1888 on Linux 2.6.32-573.el6.i686 (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. WARNING: No chipset found. Flash detection will most likely fail. No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. [root@server ~]# What information is needed to identify the chipset in use so support can be added for these devices? Best Regards, Mark Rowlinson Unless otherwise stated, this email has been sent from Fujitsu Services Limited, from Fujitsu (FTS) Limited, or from Fujitsu Telecommunications Europe Limited, together "Fujitsu". This email is only for the use of its intended recipient. Its contents are subject to a duty of confidence and may be privileged. Fujitsu does not guarantee that this email has not been intercepted and amended or that it is virus-free. Fujitsu Services Limited, registered in England No 96056, registered office 22 Baker Street, London W1U 3BW. Fujitsu (FTS) Limited, registered in England No 03808613, registered office 22 Baker Street, London W1U 3BW. PFU Imaging Solutions Europe Limited, registered in England No 1578652, registered office Hayes Park Central, Hayes End Road, Hayes, Middlesex, UB4 8FE. Fujitsu Telecommunications Europe Limited, registered in England No 2548187, registered office Solihull Parkway, Birmingham Business Park, Birmingham, B37 7YU.

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Re: [flashrom] [coreboot] Trying to flash coreboot onto on-board SPI chip of HP Envy H87 haswell chipset.
by David Hendricks Oct. 20, 2015

Oct. 20, 2015

Cool, glad it worked! To make things slightly easier, you should also try keeping the CMOS battery and DIM (whatever that is) in. On Tue, Oct 20, 2015 at 4:51 PM, Arpita Biswas <arpita.biswas07(a)gmail.com> wrote: > Hi David, > > That did the trick !!! Thanks a bunch ! For anyone else interested, here > is the combination of things I did : > > SOIC config as (1) mentioned earlier + held down the power button for 30 > sec to reset it + removed CMOS battery + removed jumper on SPI header (that > cuts off the processor signal to SPI chip) + plugged in the power cable > (that way enough power was there throughout the board for dediprog to > detect) + removed the DIM (dunno if that made any difference, but did it > since a post mentioned it anyways!). > > Dediprog then detected it sweetly :) :) > > Cheers, > - Arpita > > On Tue, Oct 20, 2015 at 2:05 PM, David Hendricks <dhendrix(a)google.com> > wrote: > >> >> >> On Tue, Oct 20, 2015 at 12:26 PM, Arpita Biswas < >> arpita.biswas07(a)gmail.com> wrote: >> >>> Hi all, >>> >>> I am trying to update BIOS with coreboot onto HP Envy H87 haswell >>> chipset (ipm87_mp) >>> <http://www.newegg.com/Product/Product.aspx?Item=9SIA6392VN4810>. I am >>> using Dediprog + SOIC 8-pin flash clip for flashing the SPI chip (W25Q64). >>> However dediprog doesn't detect the chip when it's soldered on-board. On >>> removing the chip from board, I can detect/read/write onto it without any >>> issues. >>> >>> I've tried (and failed) with the following configurations : >>> (1) SPI pin ------> Dediprog : /CS ---> CS, DO (IO1) ---> MISO, /WP >>> (IO2) ---> 3.3V, GND ---> GND, DI (IO0) ---> MOSI, CLK ---> CLK, /HOLD >>> (IO3) ---> 3.3V, VCC ---> 3.3V with motherboard power ON. >>> >>> (2) Same config as above but I tried to isolate the chip by removing >>> CMOS battery + removing jumper on SPI header + powering OFF the motherboard. >>> >>> (3) Similar as (1) and (2), but let /HOLD, /Vcc and /WP float. >>> >>> (4) I tried using flashrom on the box too as internal programmer, but it >>> did not recognize the SPI chip. Error log says "Found Programmer flash chip >>> "Opaque flash chip" (8192 kB, Programmer-specific)." >>> >>> I've a feeling that something on the motherboard is interfering with the >>> SPI chip since an off-board chip is working fine. Does anybody have any >>> pointers on what could be going wrong ? >>> >> >> I suspect your motherboard does not isolate the SPI ROM's voltage supply >> and thus your Dediprog is effectively powering other components on the >> board. >> >> If you can find a way to hold the PCH and ME in reset while the board is >> powered on, that might work. Or, with the board off, you can try using an >> external power supply (the usual warnings about possibly frying your board >> apply). >> >> >> >>> >>> Thanks in advance, >>> - Arpita >>> >>> -- >>> coreboot mailing list: coreboot(a)coreboot.org >>> http://www.coreboot.org/mailman/listinfo/coreboot >>> >> >> >> >> -- >> David Hendricks (dhendrix) >> Systems Software Engineer, Google Inc. >> > > -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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Re: [flashrom] [coreboot] Trying to flash coreboot onto on-board SPI chip of HP Envy H87 haswell chipset.
by Arpita Biswas Oct. 20, 2015

Oct. 20, 2015

Hi David, That did the trick !!! Thanks a bunch ! For anyone else interested, here is the combination of things I did : SOIC config as (1) mentioned earlier + held down the power button for 30 sec to reset it + removed CMOS battery + removed jumper on SPI header (that cuts off the processor signal to SPI chip) + plugged in the power cable (that way enough power was there throughout the board for dediprog to detect) + removed the DIM (dunno if that made any difference, but did it since a post mentioned it anyways!). Dediprog then detected it sweetly :) :) Cheers, - Arpita On Tue, Oct 20, 2015 at 2:05 PM, David Hendricks <dhendrix(a)google.com> wrote: > > > On Tue, Oct 20, 2015 at 12:26 PM, Arpita Biswas <arpita.biswas07(a)gmail.com > > wrote: > >> Hi all, >> >> I am trying to update BIOS with coreboot onto HP Envy H87 haswell >> chipset (ipm87_mp) >> <http://www.newegg.com/Product/Product.aspx?Item=9SIA6392VN4810>. I am >> using Dediprog + SOIC 8-pin flash clip for flashing the SPI chip (W25Q64). >> However dediprog doesn't detect the chip when it's soldered on-board. On >> removing the chip from board, I can detect/read/write onto it without any >> issues. >> >> I've tried (and failed) with the following configurations : >> (1) SPI pin ------> Dediprog : /CS ---> CS, DO (IO1) ---> MISO, /WP (IO2) >> ---> 3.3V, GND ---> GND, DI (IO0) ---> MOSI, CLK ---> CLK, /HOLD (IO3) ---> >> 3.3V, VCC ---> 3.3V with motherboard power ON. >> >> (2) Same config as above but I tried to isolate the chip by removing CMOS >> battery + removing jumper on SPI header + powering OFF the motherboard. >> >> (3) Similar as (1) and (2), but let /HOLD, /Vcc and /WP float. >> >> (4) I tried using flashrom on the box too as internal programmer, but it >> did not recognize the SPI chip. Error log says "Found Programmer flash chip >> "Opaque flash chip" (8192 kB, Programmer-specific)." >> >> I've a feeling that something on the motherboard is interfering with the >> SPI chip since an off-board chip is working fine. Does anybody have any >> pointers on what could be going wrong ? >> > > I suspect your motherboard does not isolate the SPI ROM's voltage supply > and thus your Dediprog is effectively powering other components on the > board. > > If you can find a way to hold the PCH and ME in reset while the board is > powered on, that might work. Or, with the board off, you can try using an > external power supply (the usual warnings about possibly frying your board > apply). > > > >> >> Thanks in advance, >> - Arpita >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot >> > > > > -- > David Hendricks (dhendrix) > Systems Software Engineer, Google Inc. >

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Re: [flashrom] [coreboot] Trying to flash coreboot onto on-board SPI chip of HP Envy H87 haswell chipset.
by David Hendricks Oct. 20, 2015

Oct. 20, 2015

On Tue, Oct 20, 2015 at 12:26 PM, Arpita Biswas <arpita.biswas07(a)gmail.com> wrote: > Hi all, > > I am trying to update BIOS with coreboot onto HP Envy H87 haswell chipset > (ipm87_mp) > <http://www.newegg.com/Product/Product.aspx?Item=9SIA6392VN4810>. I am > using Dediprog + SOIC 8-pin flash clip for flashing the SPI chip (W25Q64). > However dediprog doesn't detect the chip when it's soldered on-board. On > removing the chip from board, I can detect/read/write onto it without any > issues. > > I've tried (and failed) with the following configurations : > (1) SPI pin ------> Dediprog : /CS ---> CS, DO (IO1) ---> MISO, /WP (IO2) > ---> 3.3V, GND ---> GND, DI (IO0) ---> MOSI, CLK ---> CLK, /HOLD (IO3) ---> > 3.3V, VCC ---> 3.3V with motherboard power ON. > > (2) Same config as above but I tried to isolate the chip by removing CMOS > battery + removing jumper on SPI header + powering OFF the motherboard. > > (3) Similar as (1) and (2), but let /HOLD, /Vcc and /WP float. > > (4) I tried using flashrom on the box too as internal programmer, but it > did not recognize the SPI chip. Error log says "Found Programmer flash chip > "Opaque flash chip" (8192 kB, Programmer-specific)." > > I've a feeling that something on the motherboard is interfering with the > SPI chip since an off-board chip is working fine. Does anybody have any > pointers on what could be going wrong ? > I suspect your motherboard does not isolate the SPI ROM's voltage supply and thus your Dediprog is effectively powering other components on the board. If you can find a way to hold the PCH and ME in reset while the board is powered on, that might work. Or, with the board off, you can try using an external power supply (the usual warnings about possibly frying your board apply). > > Thanks in advance, > - Arpita > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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Trying to flash coreboot onto on-board SPI chip of HP Envy H87 haswell chipset.
by Arpita Biswas Oct. 20, 2015

Oct. 20, 2015

Hi all, I am trying to update BIOS with coreboot onto HP Envy H87 haswell chipset (ipm87_mp) <http://www.newegg.com/Product/Product.aspx?Item=9SIA6392VN4810>. I am using Dediprog + SOIC 8-pin flash clip for flashing the SPI chip (W25Q64). However dediprog doesn't detect the chip when it's soldered on-board. On removing the chip from board, I can detect/read/write onto it without any issues. I've tried (and failed) with the following configurations : (1) SPI pin ------> Dediprog : /CS ---> CS, DO (IO1) ---> MISO, /WP (IO2) ---> 3.3V, GND ---> GND, DI (IO0) ---> MOSI, CLK ---> CLK, /HOLD (IO3) ---> 3.3V, VCC ---> 3.3V with motherboard power ON. (2) Same config as above but I tried to isolate the chip by removing CMOS battery + removing jumper on SPI header + powering OFF the motherboard. (3) Similar as (1) and (2), but let /HOLD, /Vcc and /WP float. (4) I tried using flashrom on the box too as internal programmer, but it did not recognize the SPI chip. Error log says "Found Programmer flash chip "Opaque flash chip" (8192 kB, Programmer-specific)." I've a feeling that something on the motherboard is interfering with the SPI chip since an off-board chip is working fine. Does anybody have any pointers on what could be going wrong ? Thanks in advance, - Arpita

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Re: [flashrom] SOIC8 test clip - cant write to BIOS SPI flash chip
by Robert Brown Oct. 17, 2015

Oct. 17, 2015

Dear Nico, > > It might be easier to help if we knew your Laptop model. Also, please > provide a full log of the failing flashrom run with the -V switch, you > can specify a log file with -o. > Right now I'm away from that laptop and cant remember its model (or provide a flashrom log) However I remember the most important thing: the model of BIOS SPI flash chip is EON EN25QH32 which is supported by flashrom since version 0.9.6 . I got a latest datasheet at official EON website ( here it is - http://www.eonssi.com/upfile/p2013114174725.pdf ) > > Please further define "without problems". Did you try several reads and > compared the contents? > Yes I tried several reads and the contents of flash chip are always the same. Moreover, I was able to successfully write 00s and FFs for a few times, and right now the contents of SPI flash chip: 00's - first 1MB , FF's - last 3MB > > By guessing two possible issues come in mind: 1. Your programmer doesn't provide > enough power for erasure. 2. The write protection pin of your flash chip is asserted. > Because I was able to write at least some stuff, I believe that your 1st theory is true: maybe a part of current that should be going to flash chip for a successfull write, is powering a half of the surrounding circuit instead... > > I'd try with the AC adapter. In that case Vcc must _not_ be connected to > your programmer. GND, OTOH, has to stay connected. > > Not forbidden. It's sometimes even encouraged because there are boards > where the Vcc pin of the flash chip is directly connected to other > chips, which would draw down the power from the programmer. > Thank you very much for advice, Nico! As soon as I get back to equipment I am going to disconnect a Vcc pin from a programmer to avoid the overvoltage (just checked the datasheet above and Vcc is the 8th leg of that flash chip) Hopefully it will be powered good enough by the AC adapter ;-) Just not sure what to do with a CMOS battery, too afraid to connect it back together with AC adapter - if there would be overvoltage I am screwed... > >> >> Or its better to try to power Vcc of flash chip from "USB to TTL" >> adapter - which has this 3V3 (3.3V) voltage pin? >> > > It really depends on your machine. > EN25QH32 datasheet tells that this flash chip supports between 2.7V and 3.6V, 3.3V seems OK and I would probably try taking it to Vcc from "USB to TTL adapter" if the solution with a laptop's AC adapter will not work... AC adapter would also powering EC controller, so what if EC will setup a write protect? Best wishes, Robert Brown <-----Original Message-----> >From: Nico Huber [nico.h at gmx.de] >Subject: Re: [flashrom] SOIC8 test clip - cant write to BIOS SPI flash chip > > >On 17.10.2015 02:07, Robert Brown wrote: >> But here is a problem: I could read a dump from this BIOS chip without >> problems, however > > >> it fails when I am trying to write - so the contents of BIOS flash chip >> are remaining unchanged. >Log please. By guessing two possible issues come in mind: 1. Your pro- >grammer doesn't provide enough power for erasure. 2. The write protec- >tion pin of your flash chip is asserted. > >> Should I connect to motherboard a laptop's power battery, or small CMOS >> battery, or AC adapter of laptop, >I'd try with the AC adapter. In that case Vcc must _not_ be connected to >your programmer. GND, OTOH, has to stay connected. > >> so that this Vcc pin would be powered by them, or it is forbidden to do >> it while using SPI programmer in the same time? >Not forbidden. It's sometimes even encouraged because there are boards >where the Vcc pin of the flash chip is directly connected to other >chips, which would draw down the power from the programmer. > >> Or its better to try to power Vcc of flash chip from "USB to TTL" >> adapter - which has this 3V3 (3.3V) voltage pin? >It really depends on your machine. > >Nico >. > _______________________________________________________________ Get the Free email that has everyone talking at <a href=http://www.mail2world.com target=new>http://www.mail2world.com</a> Unlimited Email Storage POP3 Calendar SMS Translator Much More!

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SOIC8 test clip - cant write to BIOS SPI flash chip
by r_brown100r＠aim.com Oct. 16, 2015

Oct. 16, 2015

Unfortunately I don't have any soldering tools or experience, so if you could give an advice about ISP programming (In-System-Programming/In-Situ-Programming) , it will be super helpful! I teardown a bricked laptop, removed AC power, laptop's power battery, and even a small CMOS battery, and now I am trying to write a working BIOS image to laptop's SPI flash chip using a SOIC8 test clip. But here is a problem: I could read a dump from this BIOS chip without problems, however it fails when I am trying to write - so the contents of BIOS flash chip are remaining unchanged. Luckily I found out this helpful wiki page - http://flashrom.org/ISP , which describes common problems with this ISP method of flashing, as well as gives 3 hints for solution! Sadly this page is currently down, so here is a screenshot: http://i.imgur.com/SJEYHR2.png 1. - tried to make shorter wires, less than 10cm as they recommend - it did not help 2. - soldering is out of possibility, cant do it, and also: wires are already short and they are good quality (pure copper) 3. - This hint looks more promising, but I need help in understanding this piece of information: "disconnect Vcc from the programmer and power it with its normal PSU" If I understand correctly, by Vcc they mean Vcc pin of the BIOS flash chip. But if I disconnect Vcc from the programmer, what is "normal PSU" which should power this Vcc pin? Should I connect to motherboard a laptop's power battery, or small CMOS battery, or AC adapter of laptop, so that this Vcc pin would be powered by them, or it is forbidden to do it while using SPI programmer in the same time? Or its better to try to power Vcc of flash chip from "USB to TTL" adapter - which has this 3V3 (3.3V) voltage pin? Yours faithfully, Robert Brown

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M25P10-A write success confirmed and verified
by Stefan Tauner Oct. 16, 2015

Oct. 16, 2015

We got a mail by a reporter who does not want to get his email address published, therefore I will quote his email verbatim below. > Hello, > > I can confirm that I have just successfully flashed an ST 25P10VP flash > chip, in circuit, using a Raspberry Pi, its onboard SPI, a Pomona 5250 SOIC > clip and some female jumper wires. > > I updated the Raspberry Pi B+ with rpi-update to the latest firmware and > kernel, and compiled the code from svn://flashrom.org/flashrom/trunk on the > Raspberry device itself. I just used the -p and -w parameters to make this > work, no other magic. Flashrom reported write success and verified status > on the chip. > > According to Micron documentation, the markings 25P10VP correspond to a > M25P10-A, and flashrom recognizes this type indeed. Since the status for > writing this chip is still a question mark, I thought I should report a > success. > > I encountered zero errors during the use of flashrom, everything worked in > one go. Flashrom allowed me to recover a friend's WD HDD with a burnt-out > PCB. So a big thank you is in order! > > Thank you so much! > > P.S. Could you please keep my e-mail address private? > > Kind regards, > Martijn Schiedon I'll add the respective flag for the M25P10-A. Thanks Martijn for the report! Please include a verbose log file next time. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1897 - trunk
by repository service Oct. 16, 2015

Oct. 16, 2015

Author: stefanct Date: Fri Oct 16 04:16:20 2015 New Revision: 1897 URL: http://flashrom.org/trac/flashrom/changeset/1897 Log: Add support for 128 bytes write granularity. Some chips such as the ENE KB9012 internal flash require a write granularity of 128 bytes. Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> Acked-by: Nico Huber <nico.h(a)gmx.de> Modified: trunk/flash.h trunk/flashrom.c Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Sun Jul 5 18:53:22 2015 (r1896) +++ trunk/flash.h Fri Oct 16 04:16:20 2015 (r1897) @@ -85,6 +85,7 @@ write_gran_1bit, /* Each bit can be cleared individually. */ write_gran_1byte, /* A byte can be written once. Further writes to an already written byte cause * its contents to be either undefined or to stay unchanged. */ + write_gran_128bytes, /* If less than 128 bytes are written, the unwritten bytes are undefined. */ write_gran_264bytes, /* If less than 264 bytes are written, the unwritten bytes are undefined. */ write_gran_512bytes, /* If less than 512 bytes are written, the unwritten bytes are undefined. */ write_gran_528bytes, /* If less than 528 bytes are written, the unwritten bytes are undefined. */ Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sun Jul 5 18:53:22 2015 (r1896) +++ trunk/flashrom.c Fri Oct 16 04:16:20 2015 (r1897) @@ -781,6 +781,9 @@ break; } break; + case write_gran_128bytes: + result = need_erase_gran_bytes(have, want, len, 128); + break; case write_gran_256bytes: result = need_erase_gran_bytes(have, want, len, 256); break; @@ -847,6 +850,9 @@ case write_gran_1byte_implicit_erase: stride = 1; break; + case write_gran_128bytes: + stride = 128; + break; case write_gran_256bytes: stride = 256; break;

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Re: [flashrom] Report: Intel DH67CF BLH6710H.86A.0160.2012.1204.1156 read
by Leonardo Villarreal Cortez Oct. 15, 2015

Oct. 15, 2015

hello, i have an intel board series dh67, i need bios dump. can help me facilitating the file of dump ? thanks -- Atentamente, Leonardo Villarreal.

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flashrom output on HP 425 Notebook
by bleoal＠openmailbox.org Oct. 12, 2015

Oct. 12, 2015

Hello: My name is Bruno, last few days ago I founded information about the coreboot project. My question is: Why flashrom says it doesn't support my motherboard if my chipset is supported on the coreboot project wiki. Northbridge: AMD Fam10h Support:OK Southbridge: AMD SB7x0/SB8x0/SB9x0 1002:439d Support:OK SuperI/O: SMSC® FDC37B72x Support:OK CPU: AMD Athlon II P340 Dual-Core Here is the output: Flashrom 0.9.5.2-r1517 : $ sudo flashrom -p internal -V flashrom v0.9.5.2-r1517 on Linux 3.2.0-29-generic (x86_64), built with libpci 3.1.8, GCC 4.6.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 731M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 999 us, 10000 myus = 10009 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Hewlett-Packard" DMI string system-product-name: "HP 425" DMI string system-version: " " DMI string baseboard-manufacturer: "Hewlett-Packard" DMI string baseboard-product-name: "1475" DMI string baseboard-version: "KBC Version 72.13" DMI string chassis-type: "Notebook" Laptop detected via DMI. ======================================================================== WARNING! You seem to be running flashrom on an unsupported laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Aborting. lspci -nnvvxxx $ sudo lspci -nnvvxxx 00:00.0 Host bridge [0600]: Advanced Micro Devices [AMD] RS880 Host Bridge [1022:9601] Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- Latency: 0 Capabilities: [c4] HyperTransport: Slave or Primary Interface Command: BaseUnitID=0 UnitCnt=12 MastHost- DefDir- DUL- Link Control 0: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 3.00 Link Frequency 0: 1.6GHz Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- Link Frequency 1: 200MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- 500MHz- 600MHz- 800MHz- 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE- OFlE- PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [54] HyperTransport: UnitID Clumping Capabilities: [40] HyperTransport: Retry Mode Capabilities: [9c] HyperTransport: #1a Capabilities: [f8] HyperTransport: #1c 00: 22 10 01 96 06 00 30 22 00 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 00 00 c4 00 00 00 00 00 00 00 00 00 00 00 40: 08 9c 00 c0 c1 00 00 00 0b 00 00 00 42 20 05 00 50: 3c 10 75 14 08 40 00 90 08 10 05 00 08 10 05 00 60: 00 00 00 00 8e 00 00 00 00 02 20 00 0f 80 86 81 70: 00 00 00 00 00 00 00 00 a5 00 01 11 00 00 00 20 80: 00 00 00 00 10 00 04 03 20 c8 00 00 13 26 00 10 90: 00 00 00 80 3d 01 00 00 47 00 00 00 08 f8 7c d0 a0: 26 00 66 00 00 00 00 83 00 00 00 00 79 01 c0 07 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 80 08 54 80 01 20 00 11 00 d0 00 00 00 d0: 60 09 75 1e 02 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 ff ff ff ff 0d 02 00 00 64 40 05 00 f0: 00 00 00 00 01 00 00 00 08 00 00 e0 00 00 00 00 00:01.0 PCI bridge [0604]: Hewlett-Packard Company Device [103c:9602] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 00005000-00005fff Memory behind bridge: 94200000-943fffff Prefetchable memory behind bridge: 0000000080000000-000000008fffffff Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [44] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [b0] Subsystem: Hewlett-Packard Company Device [103c:1475] Kernel modules: shpchp 00: 3c 10 02 96 07 00 30 02 00 00 04 06 00 40 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 51 51 20 02 20: 20 94 30 94 01 80 f1 8f 00 00 00 00 00 00 00 00 30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 00 08 00 40: 00 00 00 00 08 b0 03 a8 00 00 00 00 3c 10 75 14 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 0d 00 00 00 3c 10 75 14 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:04.0 PCI bridge [0604]: Advanced Micro Devices [AMD] RS780/RS880 PCI to PCI bridge (PCIE port 0) [1022:9604] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 00003000-00004fff Memory behind bridge: 93200000-941fffff Prefetchable memory behind bridge: 0000000090000000-00000000910fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #1, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #4, PowerLimit 0.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Not Supported, TimeoutDis- ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0300c Data: 4159 Capabilities: [b0] Subsystem: Hewlett-Packard Company Device [103c:1475] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [110 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Kernel driver in use: pcieport Kernel modules: shpchp 00: 22 10 04 96 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 31 41 00 00 20: 20 93 10 94 01 90 01 91 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 03 c8 00 00 00 00 10 a0 42 01 20 80 00 00 60: 10 08 00 00 12 0c 30 01 43 00 11 78 00 00 24 00 70: 00 00 48 01 00 00 01 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 b0 01 00 0c 30 e0 fe 59 41 00 00 00 00 00 00 b0: 0d b8 00 00 3c 10 75 14 08 00 03 a8 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:07.0 PCI bridge [0604]: Advanced Micro Devices [AMD] RS780 PCI to PCI bridge (PCIE port 3) [1022:9607] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=03, subordinate=05, sec-latency=0 I/O behind bridge: 00002000-00002fff Memory behind bridge: 92200000-931fffff Prefetchable memory behind bridge: 0000000091100000-00000000920fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #247, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed unknown, Width x16, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Slot #7, PowerLimit 0.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Not Supported, TimeoutDis- ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0300c Data: 4161 Capabilities: [b0] Subsystem: Hewlett-Packard Company Device [103c:1475] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [110 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Kernel driver in use: pcieport Kernel modules: shpchp 00: 22 10 07 96 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 03 05 00 21 21 00 00 20: 20 92 10 93 11 91 01 92 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 03 c8 00 00 00 00 10 a0 42 01 20 80 00 00 60: 10 08 00 00 12 0c 30 f7 00 00 00 11 60 00 3c 00 70: 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 b0 01 00 0c 30 e0 fe 61 41 00 00 00 00 00 00 b0: 0d b8 00 00 3c 10 75 14 08 00 03 a8 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:09.0 PCI bridge [0604]: Advanced Micro Devices [AMD] RS780/RS880 PCI to PCI bridge (PCIE port 4) [1022:9608] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=06, subordinate=06, sec-latency=0 Memory behind bridge: 92100000-921fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #9, PowerLimit 0.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Not Supported, TimeoutDis- ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0300c Data: 4169 Capabilities: [b0] Subsystem: Hewlett-Packard Company Device [103c:1475] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [110 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Kernel driver in use: pcieport Kernel modules: shpchp 00: 22 10 08 96 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 06 06 00 f1 01 00 20 20: 10 92 10 92 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 03 c8 00 00 00 00 10 a0 42 01 20 80 00 00 60: 10 08 00 00 12 0c 30 00 42 00 11 70 00 00 4c 00 70: 00 00 48 01 00 00 01 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 b0 01 00 0c 30 e0 fe 69 41 00 00 00 00 00 00 b0: 0d b8 00 00 3c 10 75 14 08 00 03 a8 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:11.0 SATA controller [0106]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] [1002:4391] (prog-if 01 [AHCI 1.0]) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 19 Region 0: I/O ports at 6018 [size=8] Region 1: I/O ports at 6024 [size=4] Region 2: I/O ports at 6010 [size=8] Region 3: I/O ports at 6020 [size=4] Region 4: I/O ports at 6000 [size=16] Region 5: Memory at 9440b000 (32-bit, non-prefetchable) [size=1K] Capabilities: [70] SATA HBA v1.0 InCfgSpace Capabilities: [a4] PCI Advanced Features AFCap: TP+ FLR+ AFCtrl: FLR- AFStatus: TP- Kernel driver in use: ahci 00: 02 10 91 43 07 00 30 02 00 01 06 01 10 40 00 00 10: 19 60 00 00 25 60 00 00 11 60 00 00 21 60 00 00 20: 01 60 00 00 00 b0 40 94 00 00 00 00 3c 10 75 14 30: 00 00 00 00 70 00 00 00 00 00 00 00 0a 01 00 00 40: 14 80 bc 00 01 00 20 00 00 00 80 00 00 00 00 00 50: 05 70 86 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 01 50 22 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 12 a4 10 00 0f 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 06 14 14 00 ab 01 08 00 f0 00 00 00 90: 27 60 74 c7 00 43 06 00 00 01 00 00 01 58 b1 02 a0: 0c 00 00 00 13 00 06 03 00 00 64 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 20 00 00 e0: 80 00 00 00 00 00 00 00 00 00 00 00 10 00 00 3f f0: 00 00 00 00 00 00 00 00 77 77 77 00 00 00 00 00 00:12.0 USB controller [0c03]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] (prog-if 10 [OHCI]) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin A routed to IRQ 18 Region 0: Memory at 9440a000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00: 02 10 97 43 13 00 a0 02 00 10 03 0c 10 40 80 00 10: 00 a0 40 94 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00 40: 80 01 00 00 11 00 00 00 00 00 00 00 00 00 00 00 50: 40 00 00 f0 00 00 00 00 ff ff ff ff 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 ff 00 00 80 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 01 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:12.2 USB controller [0c03]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] (prog-if 20 [EHCI]) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin B routed to IRQ 17 Region 0: Memory at 94409000 (32-bit, non-prefetchable) [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Bridge: PM- B3+ Capabilities: [e4] Debug port: BAR=1 offset=00e0 Kernel driver in use: ehci_hcd 00: 02 10 96 43 17 00 b0 02 00 20 03 0c 10 40 00 00 10: 00 90 40 94 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 00 00 c0 00 00 00 00 00 00 00 05 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 40 21 80 a0 01 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 20 00 00 01 00 00 00 00 00 00 00 00 a0: 01 00 00 00 00 00 08 c0 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 e4 02 7e 00 00 40 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 0a 00 e0 20 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:13.0 USB controller [0c03]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] (prog-if 10 [OHCI]) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin A routed to IRQ 18 Region 0: Memory at 94408000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00: 02 10 97 43 13 00 a0 02 00 10 03 0c 10 40 80 00 10: 00 80 40 94 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00 40: 80 01 14 00 11 00 00 00 00 00 00 00 00 00 00 00 50: 40 00 00 f0 00 00 00 00 ff ff ff ff 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 ff 00 00 80 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 01 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:13.2 USB controller [0c03]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] (prog-if 20 [EHCI]) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin B routed to IRQ 17 Region 0: Memory at 94407000 (32-bit, non-prefetchable) [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D3 NoSoftRst- PME-Enable+ DSel=0 DScale=0 PME- Bridge: PM- B3+ Capabilities: [e4] Debug port: BAR=1 offset=00e0 Kernel driver in use: ehci_hcd 00: 02 10 96 43 13 00 b0 02 00 20 03 0c 10 40 00 00 10: 00 70 40 94 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 00 00 c0 00 00 00 00 00 00 00 05 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 40 21 80 a0 01 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 20 00 00 01 00 00 00 00 00 00 00 00 a0: 01 00 00 00 00 00 08 c0 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 e4 02 7e 03 01 40 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 0a 00 e0 20 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.0 SMBus [0c05]: Advanced Micro Devices [AMD] nee ATI SBx00 SMBus Controller [1002:4385] (rev 42) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Kernel modules: sp5100_tco, i2c-piix4 00: 02 10 85 43 03 04 20 02 42 00 05 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.2 Audio device [0403]: Advanced Micro Devices [AMD] nee ATI SBx00 Azalia (Intel HDA) [1002:4383] (rev 40) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 16 Region 0: Memory at 94400000 (64-bit, non-prefetchable) [size=16K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: snd_hda_intel Kernel modules: snd-hda-intel 00: 02 10 83 43 06 00 10 04 40 00 03 04 08 40 00 00 10: 04 00 40 94 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 00 00 50 00 00 00 00 00 00 00 07 01 00 00 40: 00 00 02 00 01 10 00 00 00 00 00 00 01 00 00 00 50: 01 00 42 c8 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.3 ISA bridge [0601]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 LPC host controller [1002:439d] (rev 40) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 00: 02 10 9d 43 0f 00 20 02 40 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 04 00 00 00 41 ff 03 ff 07 ff 20 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 90 0e 00 fe 00 00 0f 00 b8 ff ff ff 70: 67 45 23 00 01 00 00 00 1c 00 00 00 05 0a 00 00 80: 08 00 03 a8 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 d6 fe a0: 02 00 c1 fe 2f 01 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 09 39 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.4 PCI bridge [0604]: Advanced Micro Devices [AMD] nee ATI SBx00 PCI to PCI Bridge [1002:4384] (rev 40) (prog-if 01 [Subtractive decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 Bus: primary=00, secondary=07, subordinate=07, sec-latency=64 I/O behind bridge: 00001000-00001fff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 00: 02 10 84 43 07 00 a0 02 40 01 04 06 00 40 81 00 10: 00 00 00 00 00 00 00 00 00 07 07 40 10 10 80 22 20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 26 00 3c ff 00 00 00 00 0c 0f 3d d1 00 00 00 00 50: 01 00 00 00 08 00 03 a8 00 00 00 00 85 00 ff ff 60: ca 0e 17 00 ba 98 10 02 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 02 06 e0: 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.5 USB controller [0c03]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI2 Controller [1002:4399] (prog-if 10 [OHCI]) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin C routed to IRQ 18 Region 0: Memory at 94406000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00: 02 10 99 43 17 00 a0 02 00 10 03 0c 10 40 00 00 10: 00 60 40 94 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 03 00 00 40: 80 01 03 00 11 00 00 00 00 00 00 00 00 00 00 00 50: 40 00 00 f0 00 00 00 00 ff ff ff ff 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 ff 00 00 80 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 01 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:16.0 USB controller [0c03]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] (prog-if 10 [OHCI]) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 18 Region 0: Memory at 94405000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00: 02 10 97 43 17 00 a0 02 00 10 03 0c 10 40 80 00 10: 00 50 40 94 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00 40: 80 01 0f 00 11 00 00 00 00 00 00 00 00 00 00 00 50: 40 00 00 f0 00 00 00 00 ff ff ff ff 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 ff 00 00 80 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 01 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:16.2 USB controller [0c03]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] (prog-if 20 [EHCI]) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin B routed to IRQ 17 Region 0: Memory at 94404000 (32-bit, non-prefetchable) [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D3 NoSoftRst- PME-Enable+ DSel=0 DScale=0 PME- Bridge: PM- B3+ Capabilities: [e4] Debug port: BAR=1 offset=00e0 Kernel driver in use: ehci_hcd 00: 02 10 96 43 13 00 b0 02 00 20 03 0c 10 40 00 00 10: 00 40 40 94 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 00 00 c0 00 00 00 00 00 00 00 05 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 40 21 80 a0 01 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 20 00 00 01 00 00 00 00 00 00 00 00 a0: 01 00 00 00 00 00 00 c0 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 e4 02 7e 03 01 40 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 0a 00 e0 20 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor HyperTransport Configuration [1022:1200] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn+ ExtCTL- 64b+ Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 3.00 Link Frequency: 1.6GHz Link Error: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz+ 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA+ UIDRD- ExtRS- UCnfE- 00: 22 10 00 12 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 01 02 04 00 01 02 04 00 01 02 04 00 01 02 04 00 50: 01 02 04 00 01 02 04 00 01 02 04 00 01 02 04 00 60: 00 00 01 00 e0 00 00 00 20 a8 2e 01 10 fe 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 00 01 21 20 a0 11 00 60 09 f5 83 13 00 00 00 90: d0 02 85 80 00 00 00 00 07 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.1 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor Address Map [1022:1201] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 01 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 7f 00 00 00 00 00 01 00 00 00 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 80: 03 00 80 00 80 ff 8f 00 03 00 90 00 00 1f 94 00 90: 03 20 94 00 80 3f 94 00 03 40 94 00 00 ff df 00 a0: 03 00 e0 00 80 ff e0 00 03 00 e1 00 00 bf fe 00 b0: 03 c0 fe 00 80 fe ff 00 03 ff ff 00 00 ff ff 00 c0: 13 00 00 00 00 f0 ff 00 00 00 00 00 16 82 00 00 d0: 00 00 00 00 0a 30 f0 00 00 00 00 00 18 10 60 00 e0: 03 00 00 1f 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00:18.2 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor DRAM Controller [1022:1202] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Kernel modules: amd64_edac_mod 00: 22 10 02 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 04 00 00 0b 00 00 00 00 80: 00 00 00 00 04 00 00 00 00 00 00 ff 00 00 00 00 90: 00 00 01 08 00 41 08 00 0a 00 00 80 e7 88 71 0e a0: 00 02 00 00 00 00 00 00 00 00 01 00 00 00 00 00 b0: 29 62 51 8c 7f 00 00 00 1c 08 3e 04 40 01 e8 1f c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 78 3c 00 f0 01 30 03 01 f9 19 18 0e e7 11 18 20 e0: 44 c2 1d 0e 2f eb 30 00 14 2c 30 1e 00 90 87 c1 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.3 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor Miscellaneous Control [1022:1203] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [f0] Secure device <?> Kernel driver in use: k10temp Kernel modules: k10temp 00: 22 10 03 12 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00 40: ff ff ff 3f 58 00 b0 4a 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 05 00 60 1a 00 00 00 10 51 80 01 60 70: 51 11 32 60 01 01 98 00 14 0c 20 00 11 08 07 00 80: 81 f6 0b e6 e6 41 e6 01 08 00 00 00 00 60 58 02 90: 00 00 00 00 80 00 00 00 90 0f 88 70 00 00 00 00 a0: b9 0a 0d b0 ef 0f 88 2b 28 07 04 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 24 0f 81 c8 14 0b 39 03 43 52 27 70 e0: 00 00 00 00 30 06 40 01 61 5f 07 00 00 00 00 00 f0: 0f 00 10 00 00 00 00 00 00 00 00 00 63 0f 10 00 00:18.4 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor Link Control [1022:1204] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 04 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:05.0 VGA compatible controller [0300]: Advanced Micro Devices [AMD] nee ATI RS880M [Mobility Radeon HD 4200 Series] [1002:9712] (prog-if 00 [VGA controller]) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 18 Region 0: Memory at 80000000 (32-bit, prefetchable) [size=256M] Region 1: I/O ports at 5000 [size=256] Region 2: Memory at 94300000 (32-bit, non-prefetchable) [size=64K] Region 5: Memory at 94200000 (32-bit, non-prefetchable) [size=1M] Expansion ROM at <unassigned> [disabled] Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Kernel driver in use: fglrx_pci Kernel modules: fglrx, radeon 00: 02 10 12 97 07 00 10 00 00 00 00 03 10 00 80 00 10: 08 00 00 80 01 50 00 00 00 00 30 94 00 00 00 00 20: 00 00 00 00 00 00 20 94 00 00 00 00 3c 10 75 14 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 50: 01 a0 03 06 00 00 00 00 10 a0 12 00 a0 8f 00 00 60: 10 08 0a 00 01 0d 00 00 00 00 01 11 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 01 00 01 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:05.1 Audio device [0403]: Advanced Micro Devices [AMD] nee ATI RS880 HDMI Audio [Radeon HD 4200 Series] [1002:970f] Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin B routed to IRQ 19 Region 0: Memory at 94310000 (32-bit, non-prefetchable) [size=16K] Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Kernel driver in use: snd_hda_intel Kernel modules: snd-hda-intel 00: 02 10 0f 97 07 00 10 00 00 00 03 04 10 00 80 00 10: 00 00 31 94 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 75 14 50: 01 a0 03 06 00 00 00 00 10 a0 12 00 a0 8f 00 00 60: 10 08 0a 00 01 0d 00 00 00 00 01 11 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8101E/RTL8102E PCI Express Fast Ethernet controller [10ec:8136] (rev 02) Subsystem: Hewlett-Packard Company Device [103c:1475] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 43 Region 0: I/O ports at 3000 [size=256] Region 2: Memory at 90010000 (64-bit, prefetchable) [size=4K] Region 4: Memory at 90000000 (64-bit, prefetchable) [size=64K] Expansion ROM at 90020000 [disabled] [size=128K] Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000fee0300c Data: 4171 Capabilities: [70] Express (v2) Endpoint, MSI 01 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 4096 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <64us ClockPM+ Surprise- LLActRep- BwNot- LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [ac] MSI-X: Enable- Count=2 Masked- Vector table: BAR=4 offset=00000000 PBA: BAR=4 offset=00000800 Capabilities: [cc] Vital Product Data Unknown small resource type 00, will not decode more. Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr+ BadTLP+ BadDLLP- Rollover- Timeout- NonFatalErr+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- Capabilities: [140 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Capabilities: [160 v1] Device Serial Number 01-00-00-00-ff-ff-00-00 Kernel driver in use: r8169 Kernel modules: r8169 00: ec 10 36 81 07 04 10 00 02 00 00 02 10 00 00 00 10: 01 30 00 00 00 00 00 00 0c 00 01 90 00 00 00 00 20: 0c 00 00 90 00 00 00 00 00 00 00 00 3c 10 75 14 30: 00 00 fe ff 40 00 00 00 00 00 00 00 07 01 00 00 40: 01 50 c3 ff 08 00 00 00 00 00 00 00 00 00 00 00 50: 05 70 81 00 0c 30 e0 fe 00 00 00 00 71 41 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 10 ac 02 02 c1 8c 00 00 10 50 19 00 11 3c 07 00 80: 43 00 11 10 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 11 cc 01 00 b0: 04 00 00 00 04 08 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 80 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 06:00.0 Network controller [0280]: Broadcom Corporation BCM4313 802.11b/g/n Wireless LAN Controller [14e4:4727] (rev 01) Subsystem: Hewlett-Packard Company Device [103c:1483] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 17 Region 0: Memory at 92100000 (64-bit, non-prefetchable) [size=16K] Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=2 PME- Capabilities: [58] Vendor Specific Information: Len=78 <?> Capabilities: [48] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [d0] Express (v1) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <4us, L1 unlimited ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <4us, L1 <64us ClockPM+ Surprise- LLActRep+ BwNot- LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 14, GenCap+ CGenEn- ChkCap+ ChkEn- Capabilities: [13c v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Capabilities: [160 v1] Device Serial Number 00-00-af-ff-ff-0d-cc-52 Capabilities: [16c v1] Power Budgeting <?> Kernel driver in use: wl Kernel modules: wl, bcma, brcmsmac 00: e4 14 27 47 06 00 10 00 01 00 80 02 10 00 00 00 10: 04 00 10 92 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 83 14 30: 00 00 00 00 40 00 00 00 00 00 00 00 05 01 00 00 40: 01 58 03 06 08 40 00 00 05 d0 80 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 09 48 78 00 11 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 10 00 18 00 00 00 00 80 00 00 00 03 00 00 00 90: 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 03 00 00 10 10 18 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 10 00 01 00 a0 8f 00 00 00 00 10 00 11 6c 17 00 e0: 42 00 11 30 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Superiotool output: $ sudo superiotool -deV superiotool r6637 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x0400, id=0x014c Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0x4c01, rev=0x0 Probing for ITE Super I/O (init=it8502e) at 0x2e... Failed. Returned data: id=0x4c01, rev=0x0 Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0x4c01, rev=0x0 Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0x4c01, rev=0x0 Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0x4c01, rev=0x0 Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x164e... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O at 0x164e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x2e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x4e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Found SMSC FDC37B72x (id=0x4c, rev=0x01) at 0x2e Register dump: idx 03 20 21 22 23 24 26 27 28 2b 2c 2d 2e 2f val 00 4c 01 00 00 04 2e 00 00 00 00 00 00 00 def 03 4c 00 00 00 04 MM MM 00 NA NA NA NA NA LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 f2 f4 f5 val 00 00 00 00 00 00 00 00 00 00 def 00 03 f0 06 02 0e 00 ff 00 00 LDN 0x03 (Parallel port) idx 30 60 61 70 74 f0 f1 val 00 00 00 00 00 00 00 def 00 00 00 00 04 3c 00 LDN 0x04 (COM1) idx 30 60 61 70 f0 val 00 00 00 00 00 def 00 00 00 00 00 LDN 0x05 (COM2) idx 30 60 61 70 f0 f1 f2 val 00 00 00 00 00 00 00 def NA 00 00 00 00 02 03 LDN 0x07 (Keyboard) idx 30 70 72 f0 val 01 01 0c 00 def 00 00 00 00 LDN 0x08 (Aux I/O) idx 30 b0 b1 b2 b3 b8 c0 c1 c2 c3 c4 c5 c6 c8 ca cb cc d0 d1 d2 d3 d4 d5 d6 d7 e0 e1 e2 e3 e4 e5 e6 e7 ef f0 f1 f2 f3 f4 f6 f9 fa val 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 def 00 NA NA NA NA NA 00 01 NA NA NA 00 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 00 00 00 MM NA NA NA LDN 0x0a (ACPI) idx 30 60 61 70 f0 val 00 00 00 00 00 def 00 00 00 NA NA No extra registers known for this chip. Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O at 0x3f0... PCI device 1106:0686 not found. Probing for Server Engines Super I/O at 0x2e... Failed. Returned data: id=0xffff, rev=0xff

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Re: [flashrom] Flashrom failed on Acer C720P, using Fedora 23
by Jonathan Alfonso Oct. 12, 2015

Oct. 12, 2015

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Flashrom failed on Acer C720P, using Fedora 23
by Jonathan Alfonso Oct. 12, 2015

Oct. 12, 2015

Hi, I have this output... http://paste.flashrom.org/view.php?id=2803 I can't reboot right now, so I'm looking for a fix... I don't know what to do though. Help is definitely appreciated...

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Re: [flashrom] trouble flashing EN25S64 on Lenovo N21 chromebook
by Kyle Stanevich Oct. 8, 2015

Oct. 8, 2015

Hi, This is just a follow up email. I was wondering what the status is of support for the EN25S64 bios chip. I have tried to flash it many times and it always fails. See my message below for more details. I would like to help out with any testing for this chip, however if I don't hear back from you soon, I will probably be returning the laptop I have which contains the EN25S64 chip. Thanks, Kyle Stanevich On Oct 4, 2015 6:22 PM, "Kyle Stanevich" <kstanevich(a)imsa.edu> wrote: > Hi, > > I am still having trouble flashing the EN25S64 chip on my Lenovo N21 > chromebook. I have connected a raspberry pi to the EN25S64 on the Lenovo > N21 motherboard chip via this clip ( > http://www.amazon.com/Qunqi-Soic8-Flash-Clips-Programmer/dp/B014IXR9RG) > On the raspberry pi (which is running raspbian) I run the command "sudo > ./flashrom -VVV -p linux_spi:dev=/dev/spidev0.0 -w ~/Downloads/bios.bin". I > have removed the write protect screw, but I don't think that matters > because I am connecting to the chip directly. > > I have tried to compile google's (chromiumos') version of flashrom, but I > could not get it to compile due to many errors. Therefore, I am using the > latest version of flashrom which compiles fine. > > It seams to me that the problem is there is something not working > correctly writing/erasing/reading to the chip. Erase functions 1 through 3 > all fail when using the command shown above. It hangs up on erase function > 2 for a very long time. I had to run it overnight until erase function 2 > failed. I have tried running the same command again, and it is currently > still stuck at "Trying erase function 2... 0x000000-0x7fffff:E". It has > been stuck at this line for 16 hours, with the raspberry pi at 100% cpu > usage the entire time. > > The line "This flash part has status UNTESTED for operations: PROBE READ > ERASE WRITE" indicates to me that this chip has not yet been tested. I > would like to help out with testing for this chip since I have one and have > the hardware required to flash it. What can I do to help out? > > Thanks, > Kyle Stanevich > > > > On Sat, Oct 3, 2015 at 3:56 PM, Stefan Tauner < > stefan.tauner(a)alumni.tuwien.ac.at> wrote: > >> On Sat, 3 Oct 2015 10:13:36 -0700 >> Kyle Stanevich <kstanevich(a)imsa.edu> wrote: >> >> > Hi, >> > >> > I have attached all the output from my command line. Hopefully it will >> > be useful for you. >> > >> > Do you think that I will ever have a chance to flash this chip, or >> > should I go and buy another laptop? >> >> Hi, >> >> first of all you should not reboot before fixing the issue. >> If you made a backup first, you should try to write that instead. >> If that works you are at least safe... >> >> I am not familiar with the N21 but you probably have to disable a write >> protection. Also, chromebooks work best with google's (chromiumos') >> version of flashrom. >> >> -- >> Kind regards/Mit freundlichen Grüßen, Stefan Tauner >> > >

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Re: [flashrom] MX25L25635E / 4 byte addressing
by Michaël Zweers Oct. 5, 2015

Oct. 5, 2015

Hello, I have used the same patch set on trunk to flash W25Q256 (WSON version). I still need to build a system to check what was actually written. (I'll try to flash Openwrt to the chip and run in on a MT7620 with modded U-boot). If there is anything I can do to move this along, please let me know. Kind regards, Michaël Zweers On 21-9-2015 14:59, Peter Martini wrote: > On Tue, Sep 15, 2015 at 3:12 AM, Stefan Tauner > <stefan.tauner(a)alumni.tuwien.ac.at > <mailto:stefan.tauner@alumni.tuwien.ac.at>> wrote: > > On Tue, 15 Sep 2015 02:26:39 -0400 > Peter Martini <petercmartini(a)gmail.com > <mailto:petercmartini@gmail.com>> wrote: > > > Hello, > > > > I've checked out master from the flashrom svn repo, compiled, and was able > > to see my chip (MX25L25635E). The id wasn't recognized, but after a quick > > patch to copy a MX25L128... to ..L256.., I got it to successfully read the > > first 16MB of the chip - however, I can't get any further than that, > > because changing the values in the table to the right values moves me from > > 3 byte addressing to 4 byte addressing territory (if I understand this > > correctly), and it looks like there aren't any patches merged for that yet. > > > > Is there a patch set actively in the works? > > Nope, there isn't, at least nothing that I know about or that will hit > vanilla flashrom soon. > > -- > Kind regards/Mit freundlichen Grüßen, Stefan Tauner > > > Thanks for the quick reply. I did some digging, and found a patch set > from January, resurrected and forward ported to the current tip of > flashrom on github.com/petermartini/flashrom > <http://github.com/petermartini/flashrom>, and confirmed it worked well > enough that it worked on my chipset. > > This was Boris' work, and I guess it was incomplete / petered out before > being committed; does it ring any bells? > > It seems the thread petered out around > http://www.flashrom.org/pipermail/flashrom/2015-January/013168.html. > > I'm happy to help, if I can, get that patch set merged in if there's > work to be done on it so I can upstream my chipset's specs. > > Thanks! > Peter > > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom >

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Re: [flashrom] trouble flashing EN25S64 on Lenovo N21 chromebook
by Stefan Tauner Oct. 4, 2015

Oct. 4, 2015

On Sat, 3 Oct 2015 10:13:36 -0700 Kyle Stanevich <kstanevich(a)imsa.edu> wrote: > Hi, > > I have attached all the output from my command line. Hopefully it will > be useful for you. > > Do you think that I will ever have a chance to flash this chip, or > should I go and buy another laptop? Hi, first of all you should not reboot before fixing the issue. If you made a backup first, you should try to write that instead. If that works you are at least safe... I am not familiar with the N21 but you probably have to disable a write protection. Also, chromebooks work best with google's (chromiumos') version of flashrom. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[PATCH] ft2232: Hack to delay SPI command after CS# assertion
by Nico Huber Oct. 4, 2015

Oct. 4, 2015

Here's a tiny hack that I use to externally flash my X200s with an FT2232H. It delays the SPI command by repeating the CS# assertion command many times. Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- ft2232_spi.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/ft2232_spi.c b/ft2232_spi.c index 08742ec..a85925c 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -419,15 +419,16 @@ static int ft2232_spi_send_command(struct flashctx *flash, struct ftdi_context *ftdic = &ftdic_context; static unsigned char *buf = NULL; /* failed is special. We use bitwise ops, but it is essentially bool. */ - int i = 0, ret = 0, failed = 0; + int i = 0, j, ret = 0, failed = 0; int bufsize; static int oldbufsize = 0; + const int extra_assert_time = 288; if (writecnt > 65536 || readcnt > 65536) return SPI_INVALID_LENGTH; /* buf is not used for the response from the chip. */ - bufsize = max(writecnt + 9, 260 + 9); + bufsize = max(writecnt, 260) + 9 + extra_assert_time * 3; /* Never shrink. realloc() calls are expensive. */ if (bufsize > oldbufsize) { buf = realloc(buf, bufsize); @@ -446,9 +447,11 @@ static int ft2232_spi_send_command(struct flashctx *flash, * operations. */ msg_pspew("Assert CS#\n"); - buf[i++] = SET_BITS_LOW; - buf[i++] = 0 & ~cs_bits; /* assertive */ - buf[i++] = pindir; + for (j = 0; j <= extra_assert_time; ++j) { + buf[i++] = SET_BITS_LOW; + buf[i++] = 0 & ~cs_bits; /* assertive */ + buf[i++] = pindir; + } if (writecnt) { buf[i++] = MPSSE_DO_WRITE | MPSSE_WRITE_NEG; -- 2.4.6

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trouble flashing EN25S64 on Lenovo N21 chromebook
by Kyle Stanevich Oct. 3, 2015

Oct. 3, 2015

Hi, I have attached all the output from my command line. Hopefully it will be useful for you. Do you think that I will ever have a chance to flash this chip, or should I go and buy another laptop? Thanks, Kyle Stanevich

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