February 2013 - flashrom - mail.coreboot.org

flashrom ignoring ROM layout region
by John Gainsborough Feb. 5, 2013

Feb. 5, 2013

With BusPirate (v3a, firmware 5.10) and flashrom (v0.9.5.2, little endian) I am attempting to read a region of the flash ROM defined by a ROM layout file as in: flashrom -p buspirate_spi:dev=/dev/ ttyUSB0,spispeed=200k -l romlayout -i region1 -r read file Where file romlayout contains: 003f0000:003fffff region1 The flash ROM IC is correctly identified, and region1 is listed as being used, however flashrom then proceeds to read all ROM memory, not just the area defined by region1. I have run this procedure with flash ROMs: Eon EN25Q32 and EN25Q64. also Micronix MX25L6445 Eventually I plan to use this procedure for writing to a defined region. Any help/suggestions gratefully received. John G

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flashrom OPCODES for SPI
by Николай Николаев Feb. 5, 2013

Feb. 5, 2013

Hi Stefan Sorry but i don't want disprove you, i just have a many free time and i want to improve this project. But the dispute burning truth. 8) All time from my last mail i'm searching spi flash chips documentation and I found about 445 chips different brand and sorted them. May be it will be useful for all community. We will made host with SPI(Parallel and other) flash chips documentations and add link on wiki page. for example Eon EN25Q64(link to pdf) 8192 SPI ? ? ? ? 2.700 3.600 Studied documentation i regularity see that all chips has a support standard OPcodes like this WR DATA 0X02 READ DATA 0X03 WR DIS 0X04 READ STATUS 0X05 WR ENA 0X06 ... exclude 10 Atmel chips from amount 445 and for him we will must write special driver and special OPcodes like a Fast Dual read 0x3B Auto Address increment 0xAD and others - that codes is a different fetches spi flash chips What does this mean. This mean that a spi controller has a standard OPcodes for all flash chips and special OPcodes for each one flash chip. But if we will change flash chip on other flash chip with different special OPcodes that we will must replace special OPcodes. If we will not do it that we can't use special OPcodes, but we can use standard OPcodes. So, for more compatibility we will must verify - Does flash chip support special OPcodes?. And if chip will support them that we will use them, but if chip will not support them that we will use a standard OPcodes. for example: MX25L6405 The function write chip used standard OPcodes flash chip called function spi_chip_write_256 SST25VF016B The function write chip used fetches OPcodes flash chip called function spi_aai_write If we can't change OPcodes in registers our SPI controller that we will not write data to chip if we replace them. But we will make a program check supporting OPcodes and switch a function from spi_aai_write on spi_chip_write_256 After that we can easy write to flash or fast - our SPI controller has supporting fetches OPcodes or slow - our SPI controller hasn't supporting fetches OPcodes Also i want to suggest exclude from struct flashchip {} parameters voltage, name and add array of struct like a chipdata. The struct chipdata contains information about all possible chip names and various parameters Because looked chips documents i see chips that have a one model_id but have a various chips name, various voltage and various capacity for example MX25U6435F and MX25L6439E MX25L12805D and MX25L25835E .... -- With best regards Nikolay Nikolaev С Уважением Николаев Николай

1 0

Simple diagram for modern laptop booting flow
by Антон Кочков Feb. 4, 2013

Feb. 4, 2013

Hello! Here is simple diagram for booting flow of modern Intel laptops. Feel free to ask questions, request for improvements, giving hints. Why Intel? Just because it is more complex than modern AMD systems. Why laptop? Same reason - more complex than desktop. If you have an idea howto merge laptop and desktop booting in one diagram - please share. Attaching both png result and MS Visio 2010 source. Best regards, Anton Kochkov.

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[commit] r1648 - trunk
by repository service Feb. 4, 2013

Feb. 4, 2013

Author: stefanct Date: Mon Feb 4 05:38:42 2013 New Revision: 1648 URL: http://flashrom.org/trac/flashrom/changeset/1648 Log: Fix building for MacOSX. - Add a new macro named IS_MACOSX to hwaccess.c and use it to enable iopl(). This was broken since r1638. This fix does *not* restore the very permissive concept where iopl() was activated in an #else branch that was inplace before r1638. - Make printing the image file's size in flashrom.c platform independent. Bonus: remove definitions of off64_t and lseek64 which are not necessary anymore for about 1000 commits. Thanks to SJ for reporting the issue and testing the solution. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/flashrom.c trunk/hwaccess.c trunk/hwaccess.h Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sat Feb 2 16:35:44 2013 (r1647) +++ trunk/flashrom.c Mon Feb 4 05:38:42 2013 (r1648) @@ -1121,8 +1121,8 @@ return 1; } if (image_stat.st_size != size) { - msg_gerr("Error: Image size (%ld B) doesn't match the flash chip's size (%ld B)!\n", - image_stat.st_size, size); + msg_gerr("Error: Image size (%jd B) doesn't match the flash chip's size (%ld B)!\n", + (intmax_t)image_stat.st_size, size); fclose(image); return 1; } Modified: trunk/hwaccess.c ============================================================================== --- trunk/hwaccess.c Sat Feb 2 16:35:44 2013 (r1647) +++ trunk/hwaccess.c Mon Feb 4 05:38:42 2013 (r1648) @@ -28,7 +28,8 @@ #define IS_BSD (defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__OpenBSD__)) #define IS_LINUX (defined(__gnu_linux__) || defined(__linux__)) -#if !(IS_BSD || IS_LINUX || defined(__DJGPP__) || defined(__LIBPAYLOAD__) || defined(__sun)) +#define IS_MACOSX (defined(__APPLE__) && defined(__MACH__)) +#if !(IS_BSD || IS_LINUX || IS_MACOSX || defined(__DJGPP__) || defined(__LIBPAYLOAD__) || defined(__sun)) #error "Unknown operating system" #endif @@ -72,7 +73,7 @@ sysi86(SI86V86, V86SC_IOPL, 0); #elif IS_BSD close(io_fd); -#elif IS_LINUX +#elif IS_LINUX || IS_MACOSX iopl(0); #endif return 0; @@ -87,7 +88,7 @@ if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) { #elif IS_BSD if ((io_fd = open("/dev/io", O_RDWR)) < 0) { -#elif IS_LINUX +#elif IS_LINUX || IS_MACOSX if (iopl(3) != 0) { #endif msg_perr("ERROR: Could not get I/O privileges (%s).\n" Modified: trunk/hwaccess.h ============================================================================== --- trunk/hwaccess.h Sat Feb 2 16:35:44 2013 (r1647) +++ trunk/hwaccess.h Mon Feb 4 05:38:42 2013 (r1648) @@ -189,8 +189,6 @@ * versions. Use machine/cpufunc.h only for plain FreeBSD/DragonFlyBSD. */ #include <machine/cpufunc.h> - #define off64_t off_t - #define lseek64 lseek #define OUTB(x, y) do { u_int outb_tmp = (y); outb(outb_tmp, (x)); } while (0) #define OUTW(x, y) do { u_int outw_tmp = (y); outw(outw_tmp, (x)); } while (0) #define OUTL(x, y) do { u_int outl_tmp = (y); outl(outl_tmp, (x)); } while (0) @@ -201,8 +199,6 @@ #if defined(__MACH__) && defined(__APPLE__) /* Header is part of the DirectHW library. */ #include <DirectHW/DirectHW.h> - #define off64_t off_t - #define lseek64 lseek #endif #if defined (__sun) && (defined(__i386) || defined(__amd64)) /* Note different order for outb */ @@ -241,8 +237,6 @@ #endif #if defined(__NetBSD__) || defined (__OpenBSD__) - #define off64_t off_t - #define lseek64 lseek #if defined(__i386__) || defined(__x86_64__) #include <sys/types.h> #include <machine/sysarch.h>

1 0

Flashrom ignoring ROM layout regions
by John Gainsborough Feb. 4, 2013

Feb. 4, 2013

With BusPirate (v3a, firmware 5.10) and flashrom (v0.9.5.2, little endian) I am attempting to read a region of the flash ROM defined by a ROM layout file as in: flashrom -p buspirate_spi:dev=/dev/ttyUSB0,spispeed=200k -l romlayout -i region1 -r read file Where file romlayout contains: 003f0000:003fffff region1 The flash ROM IC is correctly identified, and region1 is listed as being used, however flashrom then proceeds to read all ROM memory, not just the area defined by region1. I have run this procedure with flash ROMs: Eon EN25Q32 and EN25Q64. also Micronix MX25L6445 Eventually I plan to use this procedure for writing to a defined region. Any help/suggestions gratefully received. John G

1 0

chip W25Q80 chipset NVIDIA MCP61 motherboard Asrock N68C-S UCC
by Александр Трубицын Feb. 3, 2013

Feb. 3, 2013

Hello! i try to use flashrom with motherboard Asrock N68C-S UCC http://www.asrock.com/mb/manual.asp?Model=N68C-S%20UCC http://www.asrock.com/mb/overview.ru.asp?cat=Manual&Model=N68C-S%20UCC with NVIDIA MCP61 chipset and W25Q80 chip. It is a part of russian manufacture'r computer Depo Ego 9730 http://www.depo.ru/download/drivers/2010/User_Manual/DEPO_Ego_manual_2010.p… I don't find any switches to enabe/disable flash writing on motherboard and in the bios menu. i use OpenSuse 12.2 with this script #!/bin/bash # get information about flash chip & BIOS name="W25Q80_chipset_NVIDIA_MCP61_on_Asrock_N68C-S_UCC" sudo /usr/sbin/flashrom -V > $name.V.txt sudo /usr/sbin/flashrom -VVVr $name.flash > $name.Vr.txt sudo /usr/sbin/flashrom -VVVE > $name.VE.txt sudo /usr/sbin/lspci -nnvvxxx > $name.lspci_nnvvxxx.txt sudo /usr/sbin/superiotool -deV > $name.superiotool.txt and get some warnings from flashrom. There are script's output files in attachment.

2 1

ASUS M5A97: success
by Melchior FRANZ Feb. 3, 2013

Feb. 3, 2013

Hey, a few days ago I successfully flashed an ASUS M5A97 bios (version 0705 to 1605). No problems whatsoever, whereas the BIOS-builtin "AZ Flash 2" turned out to be useless: it didn't even recognize my FAT usb stick. $ sudo /usr/local/sbin/flashrom --programmer internal -w M5A97-ASUS-1605.ROM flashrom v0.9.6.1-r1646 on Linux 3.7.5 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "AMD SB7x0/SB8x0/SB9x0". Enabling flash write... OK. Found Winbond flash chip "W25Q32" (4096 kB, SPI) at physical address 0xffc00000. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. Output from "flashrom -V --programmer=internal" attached. W25Q32 ... chip already listed as supported AMD SB7x0/SB8x0/SB9x0 ... chipset already listed as supported -> ASUS M5A97 ... mainboard *NOT* listed yet Thanks for flashrom! m.

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[PATCH] Fix evil twins of Macronix MX25L1605, MX25L3205, MX25L6405.
by Stefan Tauner Feb. 3, 2013

Feb. 3, 2013

Similarly to the previous patch this one updates the chips identified as above with references to and data about their respective twins. Unlike previously this one deals with the more evil details. Helge Wagner from GE discovered some problems with chips sharing IDs and proposed a patch to tackle (some of) them, see: http://patchwork.coreboot.org/patch/3709/ That patch was bitrotting in our mailboxes for a long time and it is still not ready for merge, but we increasingly get reports about problems (e.g. http://paste.flashrom.org/view.php?id=1525) regarding these chips and hence must act to ensure users' safety. This patch splits the chip definitions of evil twins into separate ones which correctly declare the respective attributes (the main problems are the erase block sizes for the 0x20 opcode and hence my changes combine different chips with partly different attributes apart from their names as long as the erasers layout it the same). This forces the user to select the (right) chip definition with the -c/--chip parameter and hence will break a number of previously perfectly working environments. 0x2015 is used by and split to - MX25L1605 (64kB sectors in 0x20 erases) - MX25L1605A (4kB in 0x20 erases and an additional 0x52 opcode with 64kB blocks) - MX25L1605D/MX25L1608D (4k sectors in 0x20 erases) 0x2016 is used by and split to - MX25L3205, MX25L3205A (64kB 0x20) - MX25L3205D/MX25L3208D (4kB 0x20) - MX25L3206E (4k 0x20, 64k 0x52) 0x2017 is used by and split to - MX25L6405 MX25L6405D (64k 0x20) - MX25L6406E/MX25L6436E (4k 0x20) - MX25L6445E (4k 0x20, 64k 0x52) Bonus: add some minor details to MX25L1635D, MX25L1635E, MX25L3235D, MX25L12805D. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- TODO after merging this: - implement probing methods that are able to distinguish at least some of the evil twins. - where this is not possible discuss alternatives like the somewhat fail-safe spi_block_erase_20_4or64k() by Helge - find and spank the ones reponsible for this whole mess. --- flashchips.c | 270 +++++++++++++++++++++++++++++++++++++++++++++++++++++----- flashchips.h | 8 +- 2 files changed, 252 insertions(+), 26 deletions(-) diff --git a/flashchips.c b/flashchips.c index b976ee6..1783fe7 100644 --- a/flashchips.c +++ b/flashchips.c @@ -5270,10 +5270,45 @@ const struct flashchip flashchips[] = { .block_erasers = { { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_default_bp2, /* bit6: error flag */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX25L1605A", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L1605, + .total_size = 2048, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { .eraseblocks = { {4 * 1024, 512} }, - .block_erase = spi_block_erase_20, /* This erase function has 64k blocksize for eLiteFlash */ + .block_erase = spi_block_erase_20, }, { - .eraseblocks = { {64 * 1024, 32} }, /* Not supported in MX25L1605 (eLiteFlash) and MX25L1605D */ + .eraseblocks = { {64 * 1024, 32} }, .block_erase = spi_block_erase_52, }, { .eraseblocks = { {64 * 1024, 32} }, @@ -5286,10 +5321,45 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, }, }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp2, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX25L1605D/MX25L1608D", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L1605, + .total_size = 2048, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6: CP mode */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */ .voltage = {2700, 3600}, }, @@ -5301,7 +5371,8 @@ const struct flashchip flashchips[] = { .model_id = MACRONIX_MX25L1635D, .total_size = 2048, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, + /* OTP: 64B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5321,10 +5392,10 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 is quad enable */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, @@ -5336,7 +5407,8 @@ const struct flashchip flashchips[] = { .model_id = MACRONIX_MX25L1635E, .total_size = 2048, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, + /* OTP: 64B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5356,16 +5428,16 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 is quad enable */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, { .vendor = "Macronix", - .name = "MX25L3205", + .name = "MX25L3205(A)", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L3205, @@ -5378,12 +5450,87 @@ const struct flashchip flashchips[] = { .block_erasers = { { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_default_bp2, /* bit6: error flag */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX25L3205D/MX25L3208D", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L3205, + .total_size = 4096, + .page_size = 256, + /* OTP: 64B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { .eraseblocks = { {4 * 1024, 1024} }, .block_erase = spi_block_erase_20, }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6: CP mode */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and dual I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX25L3206E", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L3205, + .total_size = 4096, + .page_size = 256, + /* OTP: 64B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 64} }, .block_erase = spi_block_erase_d8, }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_52, + }, { .eraseblocks = { {4 * 1024 * 1024, 1} }, .block_erase = spi_block_erase_60, }, { @@ -5391,10 +5538,10 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, }, }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp3, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) and dual I/O supported */ .voltage = {2700, 3600}, }, @@ -5406,7 +5553,8 @@ const struct flashchip flashchips[] = { .model_id = MACRONIX_MX25L3235D, .total_size = 4096, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, + /* OTP: 256B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5426,7 +5574,7 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 is quad enable */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -5435,13 +5583,14 @@ const struct flashchip flashchips[] = { { .vendor = "Macronix", - .name = "MX25L6405", + .name = "MX25L6405(D)", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L6405, .total_size = 8192, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, + /* MX25L6405D has 64B of OTP; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5461,7 +5610,7 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 has different meanings */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -5470,13 +5619,90 @@ const struct flashchip flashchips[] = { { .vendor = "Macronix", - .name = "MX25L12805", + .name = "MX25L6406E/MX25L6436E", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L6405, + .total_size = 8192, + .page_size = 256, + /* OTP: 06E 64B/36E 512B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 for 36E is quad enable */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX25L6445E", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L6405, + .total_size = 8192, + .page_size = 256, + /* supports SFDP */ + /* OTP: 512B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 is quad enable */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", + .name = "MX25L12805(D)", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L12805, .total_size = 16384, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, + /* MX25L12805D has 64B of OTP; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PROBE, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5496,10 +5722,10 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp3, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* MX25L12805D: Fast read (0x0B) supported */ .voltage = {2700, 3600}, }, diff --git a/flashchips.h b/flashchips.h index d123ab0..22af0e3 100644 --- a/flashchips.h +++ b/flashchips.h @@ -387,10 +387,10 @@ #define MACRONIX_MX25L2005 0x2012 /* Same as MX25L2005C */ #define MACRONIX_MX25L4005 0x2013 /* Same as MX25L4005A, MX25L4005C */ #define MACRONIX_MX25L8005 0x2014 /* Same as MX25V8005 */ -#define MACRONIX_MX25L1605 0x2015 /* MX25L1605{,A,D} */ -#define MACRONIX_MX25L3205 0x2016 /* MX25L3205{,A} */ -#define MACRONIX_MX25L6405 0x2017 /* MX25L6405{,D}, MX25L6406E, MX25L6436E */ -#define MACRONIX_MX25L12805 0x2018 /* MX25L12805 */ +#define MACRONIX_MX25L1605 0x2015 /* MX25L1605 (64k 0x20); MX25L1605A (4k 0x20, 64k 0x52); MX25L1605D/MX25L1608D (4k 0x20) */ +#define MACRONIX_MX25L3205 0x2016 /* MX25L3205, MX25L3205A (64k 0x20); MX25L3205D/MX25L3208D (4k 0x20); MX25L3206E (4k 0x20, 64k 0x52) */ +#define MACRONIX_MX25L6405 0x2017 /* MX25L6405, MX25L6405D (64k 0x20); MX25L6406E/MX25L6436E (4k 0x20); MX25L6445E (4k 0x20, 64k 0x52) */ +#define MACRONIX_MX25L12805 0x2018 /* Same as MX25L12805D */ #define MACRONIX_MX25L1635D 0x2415 #define MACRONIX_MX25L1635E 0x2515 /* MX25L1635{E} */ #define MACRONIX_MX25U1635E 0x2535 -- Kind regards, Stefan Tauner

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[commit] r1647 - trunk
by repository service Feb. 2, 2013

Feb. 2, 2013

Author: stefanct Date: Sat Feb 2 16:35:44 2013 New Revision: 1647 URL: http://flashrom.org/trac/flashrom/changeset/1647 Log: Update Macronix MX25L512, MX25L1005, MX25L2005, MX25L4005, MX25L8005. Update MX25L512 with references to and data about MX25L512E, MX25V512, MX25V512C. Update MX25L1005 with references to and data about MX25L1005C, MX25L1006E. Update MX25L2005 with references to and data about MX25L2005C. Update MX25L4005 with references to and data about MX25L4005A, MX25L4005C. Update MX25L8005 with references to and data about MX25V8005. Bonus: add chip IDs of MX25U1635E, MX25U3235E/F, MX25U6435E/F. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Tue Jan 15 18:37:48 2013 (r1646) +++ trunk/flashchips.c Sat Feb 2 16:35:44 2013 (r1647) @@ -5068,12 +5068,13 @@ { .vendor = "Macronix", - .name = "MX25L512", + .name = "MX25L512(E)/MX25V512(C)", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L512, .total_size = 64, .page_size = 256, + /* MX25L512E supports SFDP */ .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, @@ -5097,21 +5098,22 @@ .block_erase = spi_block_erase_c7, }, }, - .printlock = spi_prettyprint_status_register_default_bp1, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp1, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, - .voltage = {2700, 3600}, + .read = spi_chip_read, /* Fast read (0x0B) supported, MX25L512E supports dual I/O */ + .voltage = {2700, 3600}, /* 2.35-3.6V for MX25V512(C) */ }, { .vendor = "Macronix", - .name = "MX25L1005", + .name = "MX25L1005(C)/MX25L1006E", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L1005, .total_size = 128, .page_size = 256, + /* MX25L1006E supports SFDP */ .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, @@ -5132,16 +5134,16 @@ .block_erase = spi_block_erase_c7, }, }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp1, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) supported, MX25L1006E supports dual I/O */ .voltage = {2700, 3600}, }, { .vendor = "Macronix", - .name = "MX25L2005", + .name = "MX25L2005(C)", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L2005, @@ -5170,16 +5172,16 @@ .block_erase = spi_block_erase_c7, }, }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp1, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) supported */ .voltage = {2700, 3600}, }, { .vendor = "Macronix", - .name = "MX25L4005", + .name = "MX25L4005(A/C)", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L4005, @@ -5208,16 +5210,16 @@ .block_erase = spi_block_erase_c7, }, }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp2, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) supported */ .voltage = {2700, 3600}, }, { .vendor = "Macronix", - .name = "MX25L8005", + .name = "MX25L8005/MX25V8005", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L8005, @@ -5246,11 +5248,11 @@ .block_erase = spi_block_erase_c7, }, }, - .printlock = spi_prettyprint_status_register_default_bp3, /* TODO: check */ + .printlock = spi_prettyprint_status_register_default_bp2, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, - .read = spi_chip_read, - .voltage = {2700, 3600}, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, /* 2.35-3.6V for MX25V8005 */ }, { Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Tue Jan 15 18:37:48 2013 (r1646) +++ trunk/flashchips.h Sat Feb 2 16:35:44 2013 (r1647) @@ -382,10 +382,10 @@ * and use the same set of IDs. */ #define MACRONIX_ID 0xC2 /* Macronix (MX) */ -#define MACRONIX_MX25L512 0x2010 /* Same as MX25V512 */ -#define MACRONIX_MX25L1005 0x2011 -#define MACRONIX_MX25L2005 0x2012 -#define MACRONIX_MX25L4005 0x2013 /* MX25L4005{,A} */ +#define MACRONIX_MX25L512 0x2010 /* Same as MX25L512E, MX25V512, MX25V512C */ +#define MACRONIX_MX25L1005 0x2011 /* Same as MX25L1005C, MX25L1006E */ +#define MACRONIX_MX25L2005 0x2012 /* Same as MX25L2005C */ +#define MACRONIX_MX25L4005 0x2013 /* Same as MX25L4005A, MX25L4005C */ #define MACRONIX_MX25L8005 0x2014 /* Same as MX25V8005 */ #define MACRONIX_MX25L1605 0x2015 /* MX25L1605{,A,D} */ #define MACRONIX_MX25L3205 0x2016 /* MX25L3205{,A} */ @@ -393,6 +393,9 @@ #define MACRONIX_MX25L12805 0x2018 /* MX25L12805 */ #define MACRONIX_MX25L1635D 0x2415 #define MACRONIX_MX25L1635E 0x2515 /* MX25L1635{E} */ +#define MACRONIX_MX25U1635E 0x2535 +#define MACRONIX_MX25U3235E 0x2536 /* Same as MX25U6435F */ +#define MACRONIX_MX25U6435E 0x2537 /* Same as MX25U6435F */ #define MACRONIX_MX25L3235D 0x5E16 /* MX25L3225D/MX25L3235D/MX25L3237D */ #define MACRONIX_MX29F001B 0x19 #define MACRONIX_MX29F001T 0x18

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Re: [flashrom] Fw: Appreciate for developing HM65 BIOS R\W tool SW
by zhuzhihui Feb. 1, 2013

Feb. 1, 2013

Dear Stefan Nice to hear from you,we follow your kindly suggestion to upgrade Flashrom from 0.9.4 to 0.9.6, and run command #flashrom -p internal –VV in mentioned Topstar TEB-H8100 manboard,but below the outputt information: flashrom v0.9.6.1-r1564 on Linux 2.6.35.6-45.fc14.i686 (i686) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.7, GCC 4.5.1 20100924 (Red Hat 4.5.1-4), little endian Command line (3 args): flashrom -p internal -VV Calibrating delay loop... OS timer resolution is 6 usecs, 1096M loops per second, 10 myus = 11 us, 100 myus = 102 us, 1000 myus = 1001 us, 10000 myus = 10005 us, 24 myus = 24 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Topstar Corporation" DMI string system-product-name: "TEB-H8100" DMI string system-version: "0.1" DMI string baseboard-manufacturer: "Topstar Corp." DMI string baseboard-product-name: "TEB-H8100" DMI string baseboard-version: "FAB1" DMI string chassis-type: "Laptop" Laptop detected via DMI. Found ITE Super I/O, ID 0x8782 on port 0x2e Would you pls help analyze above info and give us more indication on restrictions? Thanks. Have a nice weekend! Brs\Jake zhu & David Du From: 杜新雷 Date: 2013-02-01 11:04 To: zhuzhihui Subject: Fw: Re: [flashrom] Appreciate for developing HM65 BIOS R\W tool SW 杜新雷 From: 杜新雷 Date: 2013-01-23 09:44 To: flashrom CC: 缪总; zhuzhihui Subject: Re: Re: [flashrom] Appreciate for developing HM65 BIOS R\W tool SW Hello Stefan , I am very pleased to receive your letter，depending on your tips flashrom version upgrade from 0.9.4 to 0.9.6 OS: FC14 Core Ver.2.6.35.6--45.fc14.i686 (i686) and used following command #flashrom -p internal –VV Following is the output information: flashrom v0.9.6.1-r1564 on Linux 2.6.35.6-45.fc14.i686 (i686) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.7, GCC 4.5.1 20100924 (Red Hat 4.5.1-4), little endian Command line (3 args): flashrom -p internal -VV Calibrating delay loop... OS timer resolution is 6 usecs, 1096M loops per second, 10 myus = 11 us, 100 myus = 102 us, 1000 myus = 1001 us, 10000 myus = 10005 us, 24 myus = 24 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Topstar Corporation" DMI string system-product-name: "TEB-H8100" DMI string system-version: "0.1" DMI string baseboard-manufacturer: "Topstar Corp." DMI string baseboard-product-name: "TEB-H8100" DMI string baseboard-version: "FAB1" DMI string chassis-type: "Laptop" Laptop detected via DMI. Found ITE Super I/O, ID 0x8782 on port 0x2e we do appreciate for your great help to develop the mentioned tools SW within next week，thank you! Kind regards/David From: Stefan Tauner Date: 2013-01-19 10:03 To: 朱智会 CC: flashrom; 'duxinlei' Subject: Re: [flashrom] Appreciate for developing HM65 BIOS R\W tool SW On Thu, 17 Jan 2013 17:28:53 +0800 朱智会 <zhuzhihui(a)chinalotsynergy.com> wrote: > Dear Sir/Madam > > > > This is Jake zhu and David Du from China Lotsynergy, our company is an IPC > based system integrated provider located in Guangzhou, China. To meet our > customer’s requirement of providing a BIOS R\W tool (OS: FC14 Core Ver. 2. > 6.35.6--45.fc14.i686 (i686)), we tried to seek proper tool in internet and > found FlashRom at the first time. > > We downloaded FlashRom Ver L: v0.9.4-r1455 and used following command > #flashrom -r sysbios.bin, but fail with below error info: > > > > After double check the supported chipset list in website, we found the South > Bridge Chipset HM65 is not supported; however BIOS Flash Chip (W25Q32) is > supported (see below). > > > > So write to you for help to develop a BIOS R\W tools SW (/OS: FC14 Core Ver. > 2.6.35.6--45.fc14.i686 (i686), and below the necessary info for your > reference, due to tight schedule of project, we do appreciate for your great > help to develop the mentioned tools SW within next week. Hello David, in general the chipset as well as the flash chip are well supported by flashrom. The Intel chipsets can however be configured to restrict flash access very firmly. There are various ways to restrict it (forbidden opcodes, write- and read-protected addresses ranges of different kinds etc.). If the board does not set up too many restrictions, flashrom will work for you without problems. The "error" (it is a warning actually, and you can and should read about the details in the man page how to force flashrom to continue) is because the SMBIOS/DMI table in the firmware indicates that it is a mobile device and those sometimes behave in dangerous ways. This is especially the case if the flash chip is not attached to the southbridge but and EC which is sitting between the southbridge and the flash chip. You should also update to a newer version, 0.9.4 is pretty old and I have done quite some work on the intel-related code. When you found out how to tell flashrom to continue even though it thinks it is running on a laptop please send us the output of flashrom -p internal -VV I can then tell you some details about the restrictions set up in the current firmware. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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