November 2009 - flashrom - mail.coreboot.org

flash erase failure
by Thao Hoang Dec. 22, 2009

Dec. 22, 2009

Hi there. I'm trying to use flashrom and although the program can detect both my chipset and my flash part (which are both tested & supported), the erase routine fails. (Although I don't think it even erase since the content read after this failure was the same and the board does boot up properly.) What do you think is going on? Do you think it's something with my mainboard (per some of the discussion I have seen?) Here is what I get when I do a write.... Thanks also for all the good work! root@slax:/home/user/flashrom_folder/flashrom_unrelease# ./flashrom -f -w backup.rom flashrom v0.9.1-runknown No coreboot table found. Found chipset "Intel ICH7M", enabling flash write... OK. This chipset supports the following protocols: LPC,FWH. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000- 0x0000ffff: 0x13de ERASE FAILED! ERASE FAILED! ERASE FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF!

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[PATCH] Refactor ITE SuperI/O detection/access
by Carl-Daniel Hailfinger Dec. 22, 2009

Dec. 22, 2009

Refactor ITE SuperI/O detection/access. The new code reduces duplications and paves the way for generic SuperI/O detection. Additional cost: We enter/exit the SuperI/O configuration mode twice. Once for detecting which SuperI/O it is, and once for actually changing the settings. Additional benefit: This has the potential of allowing some sort of primitive laptop detection (by way of checking whether an EC or a simple SuperI/O is present). I have added a call to a not yet implemented Winbond SuperI/O detection function inside #if 0 to make extension more straighforward. This affects most SiS chipsets and IT87 SPI translation, so tests in verbose mode would be appreciated. In theory, functionality should be unchanged. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-superio_ite_refactor/flash.h =================================================================== --- flashrom-superio_ite_refactor/flash.h (Revision 761) +++ flashrom-superio_ite_refactor/flash.h (Arbeitskopie) @@ -388,6 +388,11 @@ #endif /* internal.c */ +struct superio { + uint16_t vendor; + uint16_t port; + uint16_t model; +}; struct pci_dev *pci_dev_find_filter(struct pci_filter filter); struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class); struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device); @@ -395,6 +400,7 @@ uint16_t card_vendor, uint16_t card_device); void get_io_perms(void); void release_io_perms(void); +struct superio probe_superio(void); int internal_init(void); int internal_shutdown(void); void internal_chip_writeb(uint8_t val, chipaddr addr); @@ -611,9 +617,12 @@ int ich_spi_send_multicommand(struct spi_command *cmds); /* it87spi.c */ +#define SUPERIO_VENDOR_NONE 0x0 +#define SUPERIO_VENDOR_ITE 0x1 extern uint16_t it8716f_flashport; void enter_conf_mode_ite(uint16_t port); void exit_conf_mode_ite(uint16_t port); +struct superio probe_superio_ite(void); int it87spi_init(void); int it87xx_probe_spi_flash(const char *name); int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, Index: flashrom-superio_ite_refactor/it87spi.c =================================================================== --- flashrom-superio_ite_refactor/it87spi.c (Revision 761) +++ flashrom-superio_ite_refactor/it87spi.c (Arbeitskopie) @@ -54,19 +54,56 @@ sio_write(port, 0x02, 0x02); } -static uint16_t find_ite_spi_flash_port(uint16_t port) +uint16_t probe_id_ite(uint16_t port) { - uint8_t tmp = 0; - char *portpos = NULL; - uint16_t id, flashport = 0; + uint16_t id; enter_conf_mode_ite(port); - id = sio_read(port, CHIP_ID_BYTE1_REG) << 8; id |= sio_read(port, CHIP_ID_BYTE2_REG); + exit_conf_mode_ite(port); - /* TODO: Handle more IT87xx if they support flash translation */ - if (0x8716 == id || 0x8718 == id) { + return id; +} + +struct superio probe_superio_ite(void) +{ + struct superio ret = {}; + uint16_t ite_ports[] = {ITE_SUPERIO_PORT1, ITE_SUPERIO_PORT2, 0}; + uint16_t *i = ite_ports; + + i++; + ret.vendor = SUPERIO_VENDOR_ITE; + for (; *i; i++) { + ret.port = *i; + ret.model = probe_id_ite(ret.port); + switch (ret.model >> 8) { + case 0x82: + case 0x86: + case 0x87: + printf_debug("Found ITE SuperI/O, id %04hx\n", + ret.model); + return ret; + } + } + + /* No good ID found. */ + ret.vendor = SUPERIO_VENDOR_NONE; + ret.port = 0; + ret.model = 0; + return ret; +} + +static uint16_t find_ite_spi_flash_port(uint16_t port, uint16_t id) +{ + uint8_t tmp = 0; + char *portpos = NULL; + uint16_t flashport = 0; + + switch (id) { + case 0x8716: + case 0x8718: + enter_conf_mode_ite(port); /* NOLDN, reg 0x24, mask out lowest bit (suspend) */ tmp = sio_read(port, 0x24) & 0xFE; printf("Serial flash segment 0x%08x-0x%08x %sabled\n", @@ -105,18 +142,26 @@ sio_write(port, 0x64, (flashport >> 8)); sio_write(port, 0x65, (flashport & 0xff)); } + exit_conf_mode_ite(port); + break; + /* TODO: Handle more IT87xx if they support flash translation */ + default: + printf("SuperI/O ID %04hx is not on the controller list.\n", id); } - exit_conf_mode_ite(port); return flashport; } int it87spi_common_init(void) { - it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT1); - if (!it8716f_flashport) - it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT2); + struct superio superio; + superio = probe_superio_ite(); + if (superio.vendor == SUPERIO_VENDOR_NONE) + return 1; + + it8716f_flashport = find_ite_spi_flash_port(superio.port, superio.model); + if (it8716f_flashport) spi_controller = SPI_CONTROLLER_IT87XX; Index: flashrom-superio_ite_refactor/chipset_enable.c =================================================================== --- flashrom-superio_ite_refactor/chipset_enable.c (Revision 761) +++ flashrom-superio_ite_refactor/chipset_enable.c (Arbeitskopie) @@ -225,37 +225,40 @@ return ret; } -static int enable_flash_sis630(struct pci_dev *dev, const char *name) +static int enable_flash_decode_superio(void) { + int ret; uint8_t tmp; - uint16_t siobase; - int ret; + struct superio superio; - ret = enable_flash_sis540(dev, name); - - /* The same thing on SiS 950 Super I/O side... */ - - /* First probe for Super I/O on config port 0x2e. */ - siobase = 0x2e; - enter_conf_mode_ite(siobase); - - if (INB(siobase + 1) != 0x87) { - /* If that failed, try config port 0x4e. */ - siobase = 0x4e; - enter_conf_mode_ite(siobase); - if (INB(siobase + 1) != 0x87) { - printf("Can not find SuperI/O.\n"); - return -1; - } + superio = probe_superio(); + switch (superio.vendor) { + case SUPERIO_VENDOR_NONE: + ret = -1; + break; + case SUPERIO_VENDOR_ITE: + enter_conf_mode_ite(superio.port); + /* Enable flash mapping. Works for most old ITE style SuperI/O. */ + tmp = sio_read(superio.port, 0x24); + tmp |= 0xfc; + sio_write(superio.port, 0x24, tmp); + exit_conf_mode_ite(superio.port); + ret = 0; + break; + default: + printf_debug("Unhandled SuperI/O type!\n"); + ret = -1; + break; } + return ret; +} - /* Enable flash mapping. Works for most old ITE style SuperI/O. */ - tmp = sio_read(siobase, 0x24); - tmp |= 0xfc; - sio_write(siobase, 0x24, tmp); +static int enable_flash_sis630(struct pci_dev *dev, const char *name) +{ + int ret; - exit_conf_mode_ite(siobase); - + ret = enable_flash_sis540(dev, name); + ret |= enable_flash_decode_superio(); return ret; } Index: flashrom-superio_ite_refactor/internal.c =================================================================== --- flashrom-superio_ite_refactor/internal.c (Revision 761) +++ flashrom-superio_ite_refactor/internal.c (Arbeitskopie) @@ -122,6 +122,18 @@ #endif } +struct superio probe_superio(void) +{ + struct superio superio; + + superio = probe_superio_ite(); +#if 0 /* Winbond SuperI/O code is not yet available. */ + if (superio.vendor == SUPERIO_VENDOR_NONE) + superio = probe_superio_winbond(); +#endif + return superio; +} + int internal_init(void) { int ret = 0; -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

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Board enable requested
by Bill Maidment Dec. 21, 2009

Dec. 21, 2009

Hello there. My motherboard is a Gigabyte GA-M51GM-S2G no version number apparent. The requested diagnostics are attached. BIOS downloads are available from http://www.giga-byte.com/Support/Motherboard/BIOS_Model.aspx?ProductID=2281 Please let me know when the board enable patch is available. Many thanks for the excellent service. Regards Bill -- Bill Maidment Maidment Enterprises Pty Ltd www.maidment.vu Consultant to Elgas Ltd Phone: 02 9904 3364

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Re: [flashrom] flash erase failure
by Thao Hoang Dec. 18, 2009

Dec. 18, 2009

Opps sorry... This time the files are attached! The output.txt has both the flashrom and lspci results. This is for the ibase motherboard. I'll send you the the set of files for the laptop in the next e-mail. :) Thao --- On Mon, 11/23/09, Adrian Glaubitz <adrian.glaubitz(a)googlemail.com> wrote: From: Adrian Glaubitz <adrian.glaubitz(a)googlemail.com> Subject: Re: [flashrom] flash erase failure To: "Thao Hoang" <thao_hoang(a)yahoo.com>, flashrom(a)flashrom.org Date: Monday, November 23, 2009, 5:57 PM Hi, On Mon, Nov 23, 2009 at 10:52 PM, Thao Hoang <thao_hoang(a)yahoo.com> wrote: > > Thanks Adrian! I appreciate the advice and insight. You're welcome, again. > I was not able to run superiotool because it wasn't install on my system, however I did run the other two. > See attachment. If you really need me to run superiotool, I can download it and run it. > Yes, please install it. It would be nice to have a full output of: lspci -nnvvvxx superiotool -dV flashrom -V By the way, I don't see your attachments, did you forget them (thats what I usually do :)). Please post the put of all three tools like I suggested to the mailing list (flashrom(a)flashrom.org) that will help us with your board. > Don't laugh... but I haven't used IRC chat before. Never had a reason to until now I guess. Is there a way to post the chats somewhere so that anyone with a similar problem can go there without taking up your time? hum... > Well, really, IRC is nothing magical or mystical. Just use any IRC-capable software to connect (like irssi, pidgin, xchat or mIRC). Set the server to irc.freenode.org and the channel to #flashrom. Then just start asking questions and many people will be happy to help you and answer all your questions. > Also, did I get the syntax correct to force a write <./flashrom -f -w (filename) -c (chipname)>. Yes, think so. Check the manpage. > I have a laptop also that doesn't seem to work off the bat. I was able to force the read and > find some chips that successfullly read the bios. (i.e.... forced read and compared the result > using the original binary which I extracted using a dos bios utility.) Mhh, okey. Don't hesitate to post all your results to the mailing list. Please post every laptop and mainboard and whatever your try to flash in a single mail to the mailing list. And seriously, join the IRC-channel. You'll learn alot of stuff there. Adrian

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[PATCH 1/2] Error out when chipset/board doesn't decode full ROM
by Carl-Daniel Hailfinger Dec. 17, 2009

Dec. 17, 2009

Add infrastructure to check and report to the user the maximum supported decode size for chipsets and tested mainboards. The rationale is to warn users when they, for example, try to flash a 512KB parallel flash chip but their chipset only supports 256KB, or they try to flash 512KB and the chipset _does_ theoretically support 512KB but their special board doesn't wire all address lines and thus supports only 256 KB ROM chips at maximum. This has cost Uwe hours of debugging on some board already, until he figured out what was going on. We should try warn our users where possible about this. The chipset and the chip may have more than one bus in common (e.g. SB600 and Pm49* can both speak LPC+FWH) and on SB600/SB7x0/SB8x0 there are different limits for LPC and FWH. The only way to tell the user about the exact circumstances is to spew error messages per bus. The code will issue a warning during probe (which does fail for some chips if the size is too big) and abort before the first real read/write/erase action. That way, a user can find out why probe might not have worked, and will be stopped before he/she gets incorrect results. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-rom_decode_check_infrastructure/flash.h =================================================================== --- flashrom-rom_decode_check_infrastructure/flash.h (Revision 753) +++ flashrom-rom_decode_check_infrastructure/flash.h (Arbeitskopie) @@ -352,9 +352,17 @@ void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask); int board_flash_enable(const char *vendor, const char *part); +struct decode_sizes { + uint32_t parallel; + uint32_t lpc; + uint32_t fwh; + uint32_t spi; +}; + /* chipset_enable.c */ extern enum chipbustype buses_supported; int chipset_flash_enable(void); +extern struct decode_sizes max_rom_decode; extern unsigned long flashbase; Index: flashrom-rom_decode_check_infrastructure/chipset_enable.c =================================================================== --- flashrom-rom_decode_check_infrastructure/chipset_enable.c (Revision 753) +++ flashrom-rom_decode_check_infrastructure/chipset_enable.c (Arbeitskopie) @@ -42,6 +42,17 @@ enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI; +/** + * Programmers supporting multiple buses can have differing size limits on + * each bus. Store the limits for each bus in a common struct. + */ +struct decode_sizes max_rom_decode = { + .parallel = 0xffffffff, + .lpc = 0xffffffff, + .fwh = 0xffffffff, + .spi = 0xffffffff +}; + extern int ichspi_lock; static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) Index: flashrom-rom_decode_check_infrastructure/flashrom.c =================================================================== --- flashrom-rom_decode_check_infrastructure/flashrom.c (Revision 753) +++ flashrom-rom_decode_check_infrastructure/flashrom.c (Arbeitskopie) @@ -299,6 +299,15 @@ return (a > b) ? a : b; } +int bitcount(unsigned long a) +{ + int i = 0; + for (; a != 0; a >>= 1) + if (a & 1) + i++; + return i; +} + char *strcat_realloc(char *dest, const char *src) { dest = realloc(dest, strlen(dest) + strlen(src) + 1); @@ -398,10 +407,63 @@ return ret; } +int check_max_decode(enum chipbustype buses, unsigned int size) +{ + int limitexceeded = 0; + if ((buses & CHIP_BUSTYPE_PARALLEL) && + (max_rom_decode.parallel < size)) { + limitexceeded++; + printf_debug("Chip size %u is bigger than supported " + "size %u of chipset/board/programmer " + "for Parallel interface, " + "probe/read/erase/write may fail. ", size, + max_rom_decode.parallel); + } + if ((buses & CHIP_BUSTYPE_LPC) && + (max_rom_decode.lpc < size)) { + limitexceeded++; + printf_debug("Chip size %u is bigger than supported " + "size %u of chipset/board/programmer " + "for LPC interface, " + "probe/read/erase/write may fail. ", size, + max_rom_decode.lpc); + } + if ((buses & CHIP_BUSTYPE_FWH) && + (max_rom_decode.fwh < size)) { + limitexceeded++; + printf_debug("Chip size %u is bigger than supported " + "size %u of chipset/board/programmer " + "for FWH interface, " + "probe/read/erase/write may fail. ", size, + max_rom_decode.fwh); + } + if ((buses & CHIP_BUSTYPE_SPI) && + (max_rom_decode.spi < size)) { + limitexceeded++; + printf_debug("Chip size %u is bigger than supported " + "size %u of chipset/board/programmer " + "for SPI interface, " + "probe/read/erase/write may fail. ", size, + max_rom_decode.spi); + } + if (!limitexceeded) + return 0; + /* Sometimes chip and programmer have more than one bus in common, + * and the limit is not exceeded on all buses. Tell the user. + */ + if (bitcount(buses) > limitexceeded) + printf_debug("There is at least one common chip/programmer " + "interface which can support a chip of this size. " + "You can try --force at your own risk.\n"); + return 1; +} + struct flashchip *probe_flash(struct flashchip *first_flash, int force) { struct flashchip *flash; - unsigned long base = 0, size; + unsigned long base = 0; + unsigned int size; + enum chipbustype buses_common; char *tmp; for (flash = first_flash; flash && flash->name; flash++) { @@ -413,7 +475,8 @@ printf_debug("failed! flashrom has no probe function for this flash chip.\n"); continue; } - if (!(buses_supported & flash->bustype)) { + buses_common = buses_supported & flash->bustype; + if (!buses_common) { tmp = flashbuses_to_text(buses_supported); printf_debug("skipped. Host bus type %s ", tmp); free(tmp); @@ -424,6 +487,7 @@ } size = flash->total_size * 1024; + check_max_decode(buses_common, size); base = flashbase ? flashbase : (0xffffffff - size + 1); flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); @@ -975,6 +1039,14 @@ verify_it = 1; size = flash->total_size * 1024; + if (check_max_decode((buses_supported & flash->bustype), size) && + (!force)) { + fprintf(stderr, "This chip is too big for this programmer. " + "Details are given in verbose mode. You can override " + "this check with --force."); + programmer_shutdown(); + return 1; + } buf = (uint8_t *) calloc(size, sizeof(char)); if (erase_it) { -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

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Verbose output of lspci, superiotool and flashrom - AsRock K7VT2
by Adrian Glaubitz Dec. 16, 2009

Dec. 16, 2009

Attaching the output of: "flashrom -V", "lspci -nnvvvxxx", "superiotool -dV" for AsRock K7VT2 on flashrom r761. Adrian

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Flash failed on ASUS P4C-800E Deluxe
by Adrian Glaubitz Dec. 16, 2009

Dec. 16, 2009

Hi, I was just trying to flash the BIOS (version 1023) into an old ASUS P4C-800E Deluxe on ArchLinux (current updates as of 13-11-2009) and the latest version of flashrom from SVN. I get the following error: [root@bart flashrom]# flashrom -w Display all 101 possibilities? (y or n) [root@bart flashrom]# flashrom w P4CED23.ROM -bash: flashrom: command not found [root@bart flashrom]# ./flashrom -w P4CED23.ROM flashrom v0.9.1-r756 No coreboot table found. Found chipset "Intel ICH5/ICH5R", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... ERASE FAILED at 0x000038d0! Expected=0xff, Read=0x44, failed byte count from 0x00000000-0x0000ffff: 0xc648 ERASE FAILED! ERASE FAILED! ERASE FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! [root@bart flashrom]# Any hints? Adrian

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Flash failed on ASUS A8V-E, flash still intact
by Adrian Glaubitz Dec. 15, 2009

Dec. 15, 2009

Hi, tried flashing an ASUS A8V-E which didn't work. However, the flash rom is still intact and the machine still boots fine. Please see the attached logs of lspci -nnvvvxxx, superiotool -dV and flashrom -V plus the output for the failed flash attempt. Adrian

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not supported motherboard
by Szőgyényi Gábor Dec. 15, 2009

Dec. 15, 2009

Hi! I have a P4-M266 AMPTRON motherboard. It's not supported by flashrom-0.9.1. It has SST(MPF)39SF020A. The board looks like this: http://www.motherboard.cz/mb/amptron/P4-M266A.htm The wiki page says, flashrom supports PM266 - Albatron. It looks like: http://www.motherboard.cz/mb/albatron/PM266A.htm I attached the "./flashrom" output, and an "lspi -v -v" output. I hope, this helps for You. I have another motherboards, which are not supported. Thanks for Your reply, Gabor Szogyenyi --------------------------Hirdetés----------------------------- Kötelező biztosítási díjak 2010 Számolja ki és váltson kedvezőbbre!

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Verbose output of lspci, superiotool and flashrom - MSI MS-6590
by Adrian Glaubitz Dec. 15, 2009

Dec. 15, 2009

Attaching the output of: "flashrom -V", "lspci -nnvvvxxx", "superiotool -dV" for MSI MS-MS6590 on flashrom r761 with ITE refactoring patch by Carl-Daniel. Adrian

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