October 2009 - flashrom - mail.coreboot.org

[commit] r755 - trunk
by svn＠flashrom.org Oct. 30, 2009

Oct. 30, 2009

Author: hailfinger Date: 2009-10-31 02:53:09 +0100 (Sat, 31 Oct 2009) New Revision: 755 Modified: trunk/chipset_enable.c trunk/flash.h trunk/flashrom.c Log: Add infrastructure to check and report to the user the maximum supported decode size for chipsets and tested mainboards. The rationale is to warn users when they, for example, try to flash a 512KB parallel flash chip but their chipset only supports 256KB, or they try to flash 512KB and the chipset _does_ theoretically support 512KB but their special board doesn't wire all address lines and thus supports only 256 KB ROM chips at maximum. This has cost Uwe hours of debugging on some board already, until he figured out what was going on. We should try warn our users where possible about this. The chipset and the chip may have more than one bus in common (e.g. SB600 and Pm49* can both speak LPC+FWH) and on SB600/SB7x0/SB8x0 there are different limits for LPC and FWH. The only way to tell the user about the exact circumstances is to spew error messages per bus. The code will issue a warning during probe (which does fail for some chips if the size is too big) and abort before the first real read/write/erase action. If no action is specified, the warning is printed anyway. That way, a user can find out why probe might not have worked, and will be stopped before he/she gets incorrect results. Add a bitcount function to the infrastructure. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-10-30 21:12:39 UTC (rev 754) +++ trunk/chipset_enable.c 2009-10-31 01:53:09 UTC (rev 755) @@ -42,6 +42,17 @@ enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI; +/** + * Programmers supporting multiple buses can have differing size limits on + * each bus. Store the limits for each bus in a common struct. + */ +struct decode_sizes max_rom_decode = { + .parallel = 0xffffffff, + .lpc = 0xffffffff, + .fwh = 0xffffffff, + .spi = 0xffffffff +}; + extern int ichspi_lock; static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-10-30 21:12:39 UTC (rev 754) +++ trunk/flash.h 2009-10-31 01:53:09 UTC (rev 755) @@ -352,9 +352,17 @@ void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask); int board_flash_enable(const char *vendor, const char *part); +struct decode_sizes { + uint32_t parallel; + uint32_t lpc; + uint32_t fwh; + uint32_t spi; +}; + /* chipset_enable.c */ extern enum chipbustype buses_supported; int chipset_flash_enable(void); +extern struct decode_sizes max_rom_decode; extern unsigned long flashbase; Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-10-30 21:12:39 UTC (rev 754) +++ trunk/flashrom.c 2009-10-31 01:53:09 UTC (rev 755) @@ -299,6 +299,15 @@ return (a > b) ? a : b; } +int bitcount(unsigned long a) +{ + int i = 0; + for (; a != 0; a >>= 1) + if (a & 1) + i++; + return i; +} + char *strcat_realloc(char *dest, const char *src) { dest = realloc(dest, strlen(dest) + strlen(src) + 1); @@ -398,10 +407,60 @@ return ret; } +int check_max_decode(enum chipbustype buses, uint32_t size) +{ + int limitexceeded = 0; + if ((buses & CHIP_BUSTYPE_PARALLEL) && + (max_rom_decode.parallel < size)) { + limitexceeded++; + printf_debug("Chip size %u kB is bigger than supported " + "size %u kB of chipset/board/programmer " + "for %s interface, " + "probe/read/erase/write may fail. ", size / 1024, + max_rom_decode.parallel / 1024, "Parallel"); + } + if ((buses & CHIP_BUSTYPE_LPC) && (max_rom_decode.lpc < size)) { + limitexceeded++; + printf_debug("Chip size %u kB is bigger than supported " + "size %u kB of chipset/board/programmer " + "for %s interface, " + "probe/read/erase/write may fail. ", size / 1024, + max_rom_decode.lpc / 1024, "LPC"); + } + if ((buses & CHIP_BUSTYPE_FWH) && (max_rom_decode.fwh < size)) { + limitexceeded++; + printf_debug("Chip size %u kB is bigger than supported " + "size %u kB of chipset/board/programmer " + "for %s interface, " + "probe/read/erase/write may fail. ", size / 1024, + max_rom_decode.fwh / 1024, "FWH"); + } + if ((buses & CHIP_BUSTYPE_SPI) && (max_rom_decode.spi < size)) { + limitexceeded++; + printf_debug("Chip size %u kB is bigger than supported " + "size %u kB of chipset/board/programmer " + "for %s interface, " + "probe/read/erase/write may fail. ", size / 1024, + max_rom_decode.spi / 1024, "SPI"); + } + if (!limitexceeded) + return 0; + /* Sometimes chip and programmer have more than one bus in common, + * and the limit is not exceeded on all buses. Tell the user. + */ + if (bitcount(buses) > limitexceeded) + printf_debug("There is at least one common chip/programmer " + "interface which can support a chip of this size. " + "You can try --force at your own risk.\n"); + return 1; +} + struct flashchip *probe_flash(struct flashchip *first_flash, int force) { struct flashchip *flash; - unsigned long base = 0, size; + unsigned long base = 0; + uint32_t size; + enum chipbustype buses_common; char *tmp; for (flash = first_flash; flash && flash->name; flash++) { @@ -413,7 +472,8 @@ printf_debug("failed! flashrom has no probe function for this flash chip.\n"); continue; } - if (!(buses_supported & flash->bustype)) { + buses_common = buses_supported & flash->bustype; + if (!buses_common) { tmp = flashbuses_to_text(buses_supported); printf_debug("skipped. Host bus type %s ", tmp); free(tmp); @@ -424,6 +484,7 @@ } size = flash->total_size * 1024; + check_max_decode(buses_common, size); base = flashbase ? flashbase : (0xffffffff - size + 1); flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); @@ -956,6 +1017,15 @@ "mainboard you tested. Thanks for your help!\n===\n"); } + size = flash->total_size * 1024; + if (check_max_decode((buses_supported & flash->bustype), size) && + (!force)) { + fprintf(stderr, "Chip is too big for this programmer " + "(-V gives details). Use --force to override.\n"); + programmer_shutdown(); + return 1; + } + if (!(read_it | write_it | verify_it | erase_it)) { printf("No operations were specified.\n"); // FIXME: flash writes stay enabled! @@ -974,7 +1044,6 @@ if (write_it && !dont_verify_it) verify_it = 1; - size = flash->total_size * 1024; buf = (uint8_t *) calloc(size, sizeof(char)); if (erase_it) {

1 0

[commit] r754 - trunk
by svn＠flashrom.org Oct. 30, 2009

Oct. 30, 2009

Author: hailfinger Date: 2009-10-30 22:12:39 +0100 (Fri, 30 Oct 2009) New Revision: 754 Modified: trunk/pcidev.c Log: Adjust a help text for external PCI programmers to the new parameter scheme. Pointed out by Maciej Pijanka. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/pcidev.c =================================================================== --- trunk/pcidev.c 2009-10-22 15:07:30 UTC (rev 753) +++ trunk/pcidev.c 2009-10-30 21:12:39 UTC (rev 754) @@ -100,7 +100,7 @@ exit(1); } else if (found > 1) { fprintf(stderr, "Error: Multiple supported PCI devices found. " - "Use 'flashrom -p xxxx=bb:dd.f' \n" + "Use 'flashrom -p xxxx:bb:dd.f' \n" "to explicitly select the card with the given BDF " "(PCI bus, device, function).\n"); exit(1);

1 0

Need help to flash bios HP Omnibook 4150B
by guillaumeg Oct. 29, 2009

Oct. 29, 2009

Good evening i installed fedora 11 in my laptop Intel pentium III coppermine i'd like to flash the bios using flashrom the objectif is ( i hope) to fix a display problem - stripes on the screen, especially when i move the mouse. i tried to fix the problem with Xorg.conf and system-config-display withoot any success. Some people drived me in the french fedora forum. They invite my to join the flashrom IRC chat. for your information here a report when i launch flashrom with a terminal. flashrom v0.9.1-r710 No coreboot table found. Found chipset "Intel PIIX4/4E/4M", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically. i will stay connect on #flashrom as much as I can. Thank you for your help hope to hear from you soon regards guillaume de bamako

2 1

[PATCH] Error out when chipset/board doesn't decode full ROM
by Uwe Hermann Oct. 29, 2009

Oct. 29, 2009

See patch. I'm thankful for better suggestions to track which chipsets and especially boards can decode how much. For boards we need to autodetect them (not possible for all boards unfortunately). For those with board-enables we could reuse that table and enhance/add board-enables, whether that's a good idea is another issue. For boards that cannot be autodetected we should at least have a table of the max. supported ROM chip size, which can be printed in "flashrom -L" and in the wiki. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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Board: Acorp 6A815EPD autodetectable.
by Luc Verhaegen Oct. 27, 2009

Oct. 27, 2009

3 4

new board enable type: attacking intel bios
by ron minnich Oct. 26, 2009

Oct. 26, 2009

http://www.blackhat.com/presentations/bh-usa-09/WOJTCZUK/BHUSA09-Wojtczuk-A… interesting. Install a shell by changing the OEM logo. Would this be an "external flasher" in flashrom :-) it seems that more than ever the rule in the closed bios world is security through obscurity. we know how well that one works. ron

2 1

[PATCH] Boards: Yet another way to set an intel ICH GPIO line.
by Luc Verhaegen Oct. 25, 2009

Oct. 25, 2009

Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 371 ++++++++++++++++++++++++++++++++++---------------------- 1 files changed, 225 insertions(+), 146 deletions(-) diff --git a/board_enable.c b/board_enable.c index 21b91f1..35f43ba 100644 --- a/board_enable.c +++ b/board_enable.c @@ -523,32 +523,6 @@ static int board_epox_ep_bx3(const char *name) } /** - * Suited for Acorp 6A815EPD. - */ -static int board_acorp_6a815epd(const char *name) -{ - struct pci_dev *dev; - uint16_t port; - uint8_t val; - - dev = pci_dev_find(0x8086, 0x2440); /* Intel ICH2 LPC */ - if (!dev) { - fprintf(stderr, "\nERROR: ICH2 LPC bridge not found.\n"); - return -1; - } - - /* Use GPIOBASE register to find where the GPIO is mapped. */ - port = (pci_read_word(dev, 0x58) & 0xFFC0) + 0xE; - - val = INB(port); - val |= 0x80; /* Top Block Lock -- pin 8 of PLCC32 */ - val |= 0x40; /* Lower Blocks Lock -- pin 7 of PLCC32 */ - OUTB(val, port); - - return 0; -} - -/** * Suited for Artec Group DBE61 and DBE62. */ static int board_artecgroup_dbe6x(const char *name) @@ -590,105 +564,262 @@ static int board_artecgroup_dbe6x(const char *name) } /** - * Set the specified GPIO on the specified ICHx southbridge to high. - * - * @param name The name of this board. - * @param ich_vendor PCI vendor ID of the specified ICHx southbridge. - * @param ich_device PCI device ID of the specified ICHx southbridge. - * @param gpiobase_reg GPIOBASE register offset in the LPC bridge. - * @param gp_lvl Offset of GP_LVL register in I/O space, relative to GPIOBASE. - * @param gp_lvl_bitmask GP_LVL bitmask (set GPIO bits to 1, all others to 0). - * @param gpio_bit The bit (GPIO) which shall be set to high. - * @return If the write-enable was successful return 0, otherwise return -1. + * Set a GPIO line on a given intel ICH LPC controller. */ -static int ich_gpio_raise(const char *name, uint16_t ich_vendor, - uint16_t ich_device, uint8_t gpiobase_reg, - uint8_t gp_lvl, uint32_t gp_lvl_bitmask, - unsigned int gpio_bit) +static int intel_ich_gpio_set(int gpio, int raise) { + /* table mapping the different intel ICH LPC chipsets. */ + static struct { + uint16_t id; + uint8_t base_reg; + uint32_t bank0; + uint32_t bank1; + uint32_t bank2; + } intel_ich_gpio_table[] = { + {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */ + {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */ + {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */ + {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */ + {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */ + {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */ + {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */ + {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */ + {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */ + {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */ + {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */ + {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */ + {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */ + {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */ + {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */ + {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */ + {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */ + {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */ + {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */ + {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */ + {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */ + {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */ + {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */ + {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */ + {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */ + {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */ + {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */ + {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */ + {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */ + {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */ + {0, 0, 0, 0, 0} /* end marker */ + }; + struct pci_dev *dev; - uint16_t gpiobar; - uint32_t reg32; + uint16_t base; + uint32_t tmp; + int i, allowed; + + /* First, look for a known LPC bridge */ + for (dev = pacc->devices; dev; dev = dev->next) + if ((dev->vendor_id == 0x8086) && + (dev->device_class == 0x0601)) { /* ISA Bridge */ + /* Is this device in our list? */ + for (i = 0; intel_ich_gpio_table[i].id; i++) + if (dev->device_id == intel_ich_gpio_table[i].id) + break; + + if (intel_ich_gpio_table[i].id) + break; + } - dev = pci_dev_find(ich_vendor, ich_device); /* Intel ICHx LPC */ if (!dev) { - fprintf(stderr, "\nERROR: ICHx LPC dev %4x:%4x not found.\n", - ich_vendor, ich_device); + fprintf(stderr, "\nERROR: No Known Intel LPC Bridge found.\n"); return -1; } - /* Use GPIOBASE register to find the I/O space for GPIO. */ - gpiobar = pci_read_word(dev, gpiobase_reg) & gp_lvl_bitmask; + /* According to the datasheets, all intel ICHs have the gpio bar 5:1 + strapped to zero. From some mobile ich9 version on, this becomes + 6:1. The mask below catches all. */ + base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0; - /* Set specified GPIO to high. */ - reg32 = INL(gpiobar + gp_lvl); - reg32 |= (1 << gpio_bit); - OUTL(reg32, gpiobar + gp_lvl); + /* check whether the line is allowed */ + if (gpio < 32) + allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01; + else if (gpio < 64) + allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01; + else + allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01; + + if (!allowed) { + fprintf(stderr, "\nERROR: This Intel LPC Bridge does not allow" + " setting GPIO%02d\n", gpio); + return -1; + } + + printf("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n", + raise ? "Rais" : "Dropp", gpio); + + if (gpio < 32) { + /* Set line to GPIO */ + tmp = INL(base); + /* ICH/ICH0 multiplexes 27/28 on the line set. */ + if ((gpio == 28) && + ((dev->device_id == 0x2410) || (dev->device_id == 0x2420))) + tmp |= 1 << 27; + else + tmp |= 1 << gpio; + OUTL(tmp, base); + + /* As soon as we are talking to ICH8 and above, this register + decides whether we can set the gpio or not. */ + if (dev->device_id > 0x2800) { + tmp = INL(base); + if (!(tmp & (1 << gpio))) { + fprintf(stderr, "\nERROR: This Intel LPC Bridge" + " does not allow setting GPIO%02d\n", + gpio); + return -1; + } + } + + /* Set GPIO to OUTPUT */ + tmp = INL(base + 0x04); + tmp &= ~(1 << gpio); + OUTL(tmp, base + 0x04); + + /* Raise GPIO line */ + tmp = INL(base + 0x0C); + if (raise) + tmp |= 1 << gpio; + else + tmp &= ~(1 << gpio); + OUTL(tmp, base + 0x0C); + } else if (gpio < 64) { + gpio -= 32; + + /* Set line to GPIO */ + tmp = INL(base + 0x30); + tmp |= 1 << gpio; + OUTL(tmp, base + 0x30); + + /* As soon as we are talking to ICH8 and above, this register + decides whether we can set the gpio or not. */ + if (dev->device_id > 0x2800) { + tmp = INL(base + 30); + if (!(tmp & (1 << gpio))) { + fprintf(stderr, "\nERROR: This Intel LPC Bridge" + " does not allow setting GPIO%02d\n", + gpio + 32); + return -1; + } + } + + /* Set GPIO to OUTPUT */ + tmp = INL(base + 0x34); + tmp &= ~(1 << gpio); + OUTL(tmp, base + 0x34); + + /* Raise GPIO line */ + tmp = INL(base + 0x38); + if (raise) + tmp |= 1 << gpio; + else + tmp &= ~(1 << gpio); + OUTL(tmp, base + 0x38); + } else { + gpio -= 64; + + /* Set line to GPIO */ + tmp = INL(base + 0x40); + tmp |= 1 << gpio; + OUTL(tmp, base + 0x40); + + tmp = INL(base + 40); + if (!(tmp & (1 << gpio))) { + fprintf(stderr, "\nERROR: This Intel LPC Bridge does " + "not allow setting GPIO%02d\n", gpio + 64); + return -1; + } + + /* Set GPIO to OUTPUT */ + tmp = INL(base + 0x44); + tmp &= ~(1 << gpio); + OUTL(tmp, base + 0x44); + + /* Raise GPIO line */ + tmp = INL(base + 0x48); + if (raise) + tmp |= 1 << gpio; + else + tmp &= ~(1 << gpio); + OUTL(tmp, base + 0x48); + } return 0; } /** - * Suited for ASUS P4B266. + * Suited for Abit IP35: Intel P35 + ICH9R. */ -static int ich2_gpio22_raise(const char *name) +static int intel_ich_gpio16_raise(const char *name) { - return ich_gpio_raise(name, 0x8086, 0x2440, 0x58, 0x0c, 0xffc0, 22); + return intel_ich_gpio_set(16, 1); } /** - * Suited for the Dell PowerEdge 1850. All parameters except the last one are - * documented in the public Intel 82801EB ICH5 / 82801ER ICH5R datasheet. The - * last parameter (GPIO number) has to be in the range [16,31] according to - * said Intel datasheet and was found by exhaustive search. + * Suited for MSI MS-7046: LGA775 + 915P + ICH6. */ -static int ich5_gpio23_raise(const char *name) +static int intel_ich_gpio19_raise(const char *name) { - return ich_gpio_raise(name, 0x8086, 0x24d0, 0x58, 0x0c, 0xffc0, 23); + return intel_ich_gpio_set(19, 1); } /** - * Suited for MSI MS-7046. + * Suited for Asus P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R. */ -static int ich6_gpio19_raise(const char *name) +static int intel_ich_gpio21_raise(const char *name) { - return ich_gpio_raise(name, 0x8086, 0x2640, 0x48, 0x0c, 0xffc0, 19); + return intel_ich_gpio_set(21, 1); } -static int board_kontron_986lcd_m(const char *name) +/** + * Suited for ASUS P4B266: socket478 + intel 845D + ICH2. + */ +static int intel_ich_gpio22_raise(const char *name) { - struct pci_dev *dev; - uint16_t gpiobar; - uint32_t val; + return intel_ich_gpio_set(22, 1); +} -#define ICH7_GPIO_LVL2 0x38 +/** + * Suited for Dell Poweredge 1850: Intel PPGA604 + E7520 + ICH5R. + */ +static int intel_ich_gpio23_raise(const char *name) +{ + return intel_ich_gpio_set(23, 1); +} - dev = pci_dev_find(0x8086, 0x27b8); /* Intel ICH7 LPC */ - if (!dev) { - // This will never happen on this board - fprintf(stderr, "\nERROR: ICH7 LPC bridge not found.\n"); - return -1; - } +/** + * Suited for Acorp 6A815EPD: socket 370 + intel 815 + ICH2. + */ +static int board_acorp_6a815epd(const char *name) +{ + int ret; - /* Use GPIOBASE register to find where the GPIO is mapped. */ - gpiobar = pci_read_word(dev, 0x48) & 0xfffc; + /* Lower Blocks Lock -- pin 7 of PLCC32 */ + ret = intel_ich_gpio_set(22, 1); + if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */ + ret = intel_ich_gpio_set(23, 1); - val = INL(gpiobar + ICH7_GPIO_LVL2); /* GP_LVL2 */ - printf_debug("\nGPIOBAR=0x%04x GP_LVL: 0x%08x\n", gpiobar, val); + return ret; +} - /* bit 2 (0x04) = 0 #TBL --> bootblock locking = 1 - * bit 2 (0x04) = 1 #TBL --> bootblock locking = 0 - * bit 3 (0x08) = 0 #WP --> block locking = 1 - * bit 3 (0x08) = 1 #WP --> block locking = 0 - * - * To enable full block locking, you would do: - * val &= ~ ((1 << 2) | (1 << 3)); - */ - val |= (1 << 2) | (1 << 3); +/** + * Suited for Kontron 986LCD-M: socket478 + 915GM + ICH7R. + */ +static int board_kontron_986lcd_m(const char *name) +{ + int ret; - OUTL(val, gpiobar + ICH7_GPIO_LVL2); + ret = intel_ich_gpio_set(34, 1); /* #TBL */ + if (!ret) + ret = intel_ich_gpio_set(35, 1); /* #WP */ - return 0; + return ret; } /** @@ -881,32 +1012,6 @@ static int board_mitac_6513wu(const char *name) } /** - * Suited for Abit IP35: Intel P35 + ICH9R. - */ -static int board_abit_ip35(const char *name) -{ - struct pci_dev *dev; - uint16_t base; - uint8_t tmp; - - dev = pci_dev_find(0x8086, 0x2916); /* Intel ICH9R LPC Interface */ - if (!dev) { - fprintf(stderr, "\nERROR: Intel ICH9R LPC not found.\n"); - return -1; - } - - /* get LPC GPIO base */ - base = pci_read_long(dev, 0x48) & 0x0000FFC0; - - /* Raise GPIO 16 */ - tmp = INB(base + 0x0E); - tmp |= 0x01; - OUTB(tmp, base + 0x0E); - - return 0; -} - -/** * Suited for Asus A7V8X: VIA KT400 + VT8235 + IT8703F-A */ static int board_asus_a7v8x(const char *name) @@ -1009,32 +1114,6 @@ static int board_asus_a7v600x(const char *name) } /** - * Suited for Asus P4P800-E Deluxe: Intel Intel 865PE + ICH5R. - */ -static int board_asus_p4p800(const char *name) -{ - struct pci_dev *dev; - uint16_t base; - uint8_t tmp; - - dev = pci_dev_find(0x8086, 0x24D0); /* Intel ICH5R ISA Bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: Intel ICH5R ISA Bridge not found.\n"); - return -1; - } - - /* get PM IO base */ - base = pci_read_long(dev, 0x58) & 0x0000FFC0; - - /* Raise GPIO 21 */ - tmp = INB(base + 0x0E); - tmp |= 0x20; - OUTB(tmp, base + 0x0E); - - return 0; -} - -/** * Below is the list of boards which need a special "board enable" code in * flashrom before their ROM chip can be accessed/written to. * @@ -1063,7 +1142,7 @@ static int board_asus_p4p800(const char *name) /* Please keep this list alphabetically ordered by vendor/board name. */ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], coreboot id [2], vendor name board name flash enable */ - {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, "Abit", "IP35", board_abit_ip35}, + {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, "Abit", "IP35", intel_ich_gpio16_raise}, {0x8086, 0x1130, 0, 0, 0x105a, 0x0d30, 0x105a, 0x4d33, "acorp", "6a815epd", "Acorp", "6A815EPD", board_acorp_6a815epd}, {0x1022, 0x746B, 0x1022, 0x36C0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A*", board_epox_ep_8k5a2}, @@ -1073,12 +1152,12 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, "ASUS", "A7V600-X", board_asus_a7v600x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, "ASUS", "A7V8X", board_asus_a7v8x}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", board_asus_a7v8x_mx}, - {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", ich2_gpio22_raise}, - {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", board_asus_p4p800}, + {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", intel_ich_gpio22_raise}, + {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", intel_ich_gpio21_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", board_asus_p5nd2_sli}, {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable}, - {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "PowerEdge 1850", ich5_gpio23_raise}, + {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "PowerEdge 1850", intel_ich_gpio23_raise}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", board_epox_ep_8k5a2}, {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", board_epox_ep_8rda3plus}, @@ -1103,7 +1182,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, "msi", "kt4ultra", "MSI", "MS-6590 (KT4 Ultra)",board_msi_kt4v}, {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)",w83627thf_gpio4_4_raise_2e}, {0x1106, 0x0571, 0x1462, 0x7120, 0, 0, 0, 0, "msi", "kt4v", "MSI", "MS-6712 (KT4V)", board_msi_kt4v}, - {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", ich6_gpio19_raise}, + {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", intel_ich_gpio19_raise}, {0x10de, 0x005e, 0, 0, 0, 0, 0, 0, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25}, -- 1.6.0.2 --cNdxnHkX5QqsyA0e--

1 0

Flashing of ASUS M2N4-SLI BIOS
by Michael Stephenson Oct. 25, 2009

Oct. 25, 2009

Hi, My motherboard is an ASUS M2N4-SLI, and I attempted to flash it with the 1205 BIOS available from the ASUS website, the flash went without incident as can be seen here http://www.pastebin.ca/1642685 When I rebooted everything seemed to work fine until I reached GDM where I found my usb mouse no longer worked, so I dropped to console (fortunately am using a PS/2 keyboard) where I discovered my ethernet card had not been discovered, after rebooting a few times and tinkering with the BIOS to no effect I decided to restore my backup. Where everything worked fine again. Speaking to Carldani in irc he made the comments: > carldani: they store the ethernet address in the bios image, so if you reflash, you lose the ethernet address... > carldani: if you have a hex editor, you could try to locate your mac address in the backup file > carldani: the mac address may be stored in reverse... > carldani: maybe someone on the mailing list knows the mac extraction procedure better than I do I have attached the output of lspci -nnvvvxxx and flashrom -V Thanks Michael

1 0

motherboard report - TYAN S2885, PMC 4Mbit
by Mick Reed Oct. 25, 2009

Oct. 25, 2009

I can confirm that flashrom works on TYAN S2885, for at least read and write. The S2885 has a socketed 32-PLCC, the same as the S2881. I have glued over the part numbers?? but I know it comes with a PMC 4Mbit, the exact same chip as the S2881 (I have an old broken one of those). I was able to read out the old 2.05 bios and write the latest 2.08 into the chip. I can't remember whether it was automatically "verified" or whether I did it manually, but I know it worked (it's my main machine, which I am using now). FYI I am going to use an SST49LF016C-33-4C-NHE (8Mbit) for a fun coreboot project. It's been a while, I haven't touched that one yet, I'll report on that if it works. Anything else, let me know. Thanks. Mick Reed # flashrom -V flashrom v0.9.1-r753 No coreboot table found. Found chipset "AMD AMD8111", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... 536M loops per second, 100 myus = 216 us. OK. Probing for AMD Am29F010A/B, 128 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F080B, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29LV081B, 1024 KB: probe_29f040b: id1 0xff, id2 0xff Probing for ASD AE49F2008, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT29C010A, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N), 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for AMIC A25L40P, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for AMIC A29002T, 256 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for AMIC A29040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMIC A49LF040A, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for EMST F49B002UA, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Eon EN25B05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Fujitsu MBM29F004BC, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Fujitsu MBM29F004TC, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Intel 28F001BX-B, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Intel 28F001BX-T, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Macronix MX25L512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for Macronix MX29F001T, 128 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for Macronix MX29F002B, 256 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for Macronix MX29F002T, 256 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for Macronix MX29LV040, 512 KB: probe_29f002: id1 0x9d, id2 0x6e Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm29F0002T, 256 KB: probe_29f040b: id1 0x04, id2 0x36 Probing for PMC Pm29F0002B, 256 KB: probe_29f040b: id1 0x04, id2 0x36 Probing for PMC Pm39LV010, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for PMC Pm49FL002, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for PMC Pm49FL004, 512 KB: probe_jedec: id1 0x9d, id2 0x6e (here it is!!) Found chip "PMC Pm49FL004" (512 KB, LPC,FWH) at physical address 0xfff80000. Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0xff, id2 0xff Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0xff, id2 0xff Probing for SST SST29EE010, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST29LE010, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST29EE020A, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST29LE020, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST39VF080, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF003A/B, 384 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF008A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF020, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF040B, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for ST M29F002T/NT, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29W010B, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for ST M29W040B, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for ST M50FLW040A, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for ST M50FLW040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for ST M50FLW080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: probe_49lfxxxc: id1 0x04, id2 0x36 Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50LPW116, 2048 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C31004T, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SyncMOS S29C51001T, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SyncMOS S29C51002T, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for SyncMOS S29C51004T, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for TI TMS29F002RB, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for TI TMS29F002RT, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W25x10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W29EE011, 128 KB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W49V002FA, 256 KB: probe_jedec: id1 0x9d, id2 0x6e Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x9d, id2 0x6e Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. No operations were specified.

1 1

[PATCH] Boards: Unify all intel ICH GPIO raising.
by Luc Verhaegen Oct. 25, 2009

Oct. 25, 2009

Ok, big change here which will require several of the people on the list below to test and Ack this patch. But one has to admit; the result is worth it. Jonathan, can you verify this patch on your acorp 6A815EPD (preferably also with the previous patch)? Thanks for having replied that swiftly last time :) Uwe, it seems that the Asus P4B266 is yours, the code was committed as r247. Can you send in an lspci -vvnnxxx to the list as well? Carl-Daniel, the Dell is from your commit, r728. Any lspci on that? David, i would guess that the MSI MS-7046 is your board (original commit r414), can you go and verify this code on this hardware? We would like to have an lspci -vvnnxxx for this board too. Stepan, it seems that you committed the kontron 986LCD-M board enable. Can you check whether this code still works with your board, and can you also provide an lspci -vvnnxxx? I would also like to get rid of the entry which just matches one pci devices, and the coreboot ids in the table. Richie, can you give this code a spin on your Abit IP35? (original commit r642) Bojan? Asus P4P800-E seems to be yours and it was added just under two months ago in r682. Can you give this code a run too? I would like to see at least 4 of these boards get an Ack before this can be committed. Thanks all, now i can send in at least two more board enables which go on top of this stuff. Luc Verhaegen.

4 18

[PATCH] Board match for ASRock P4i65GV.
by Luc Verhaegen Oct. 23, 2009

Oct. 23, 2009

Same board enable as the Dell PowerEdge 1850: raise gpio23 on ich5r. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/board_enable.c b/board_enable.c index 03930f4..19825eb 100644 --- a/board_enable.c +++ b/board_enable.c @@ -739,7 +739,9 @@ static int board_asus_p4p800(const char *name) } /** - * Suited for Dell Poweredge 1850: Intel PPGA604 + E7520 + ICH5R. + * Suited for: + * - Dell Poweredge 1850: Intel PPGA604 + E7520 + ICH5R. + * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R. * * The GPIO number has to be in the range [16,31] according to the public Intel * 82801EB ICH5 / 82801ER ICH5R datasheet and was found by exhaustive search. @@ -1136,6 +1138,7 @@ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], coreboot id [2], vendor name board name flash enable */ {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, "Abit", "IP35", board_abit_ip35}, {0x8086, 0x1130, 0, 0, 0x105a, 0x0d30, 0x105a, 0x4d33, "acorp", "6a815epd", "Acorp", "6A815EPD", board_acorp_6a815epd}, + {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, "ASRock", "P4i65GV", board_dell_pe_1850}, {0x1022, 0x746B, 0x1022, 0x36C0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A*", board_epox_ep_8k5a2}, {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, "AOpen", "vKM400Am-S", board_aopen_vkm400}, -- 1.6.0.2 --Qxx1br4bt0+wmkIi--

1 0

[PATCH] Board enable for Asus P4B266-LM.
by Luc Verhaegen Oct. 23, 2009

Oct. 23, 2009

Board shipped in the Sony Vaio PCV-RX650. Raises GPIO21 on intel ICH2. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 20 ++++++++++++++++++++ 1 files changed, 20 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 2332209..03930f4 100644 --- a/board_enable.c +++ b/board_enable.c @@ -665,6 +665,25 @@ static void intel_ich_gpio_raise(struct pci_dev *dev, unsigned int gpio) } /** + * Suited for Asus P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2. + */ +static int board_asus_p4b266_lm(const char *name) +{ + struct pci_dev *dev; + + dev = pci_dev_find(0x8086, 0x2440); /* Intel ICH2 ISA Bridge */ + if (!dev) { + fprintf(stderr, "\nERROR: Intel ICH2 ISA Bridge not found.\n"); + return -1; + } + + intel_ich_gpio_raise(dev, 21); + + return 0; +} + + +/** * Suited for ASUS P4B266: socket478 + intel 845D + ICH2. */ static int board_asus_p4b266(const char *name) @@ -1126,6 +1145,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, "ASUS", "A7V8X", board_asus_a7v8x}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", board_asus_a7v8x_mx}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", board_asus_p4b266}, + {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, "ASUS", "P4B266-LM", board_asus_p4b266_lm}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", board_asus_p4p800}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", board_asus_p5nd2_sli}, -- 1.6.0.2 --ftEhullJWpWg/VHq--

1 0

[PATCH] Boards: Unify all intel ICH GPIO setting in one function.
by Luc Verhaegen Oct. 23, 2009

Oct. 23, 2009

The new intel_ich_gpio_raise function should be general for all intel ich southbridges. There are a few comments to this function, which should be considered before using this function. Plus, this function does not only raise the gpio line, it switches the signal to gpio and sets it to output as well. A few boards have been moved around to sit below the intel_ich_gpio_raise function which makes this patch more unsightly than it could be. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 326 ++++++++++++++++++++++++++++++++------------------------ 1 files changed, 189 insertions(+), 137 deletions(-) diff --git a/board_enable.c b/board_enable.c index 21b91f1..2332209 100644 --- a/board_enable.c +++ b/board_enable.c @@ -523,32 +523,6 @@ static int board_epox_ep_bx3(const char *name) } /** - * Suited for Acorp 6A815EPD. - */ -static int board_acorp_6a815epd(const char *name) -{ - struct pci_dev *dev; - uint16_t port; - uint8_t val; - - dev = pci_dev_find(0x8086, 0x2440); /* Intel ICH2 LPC */ - if (!dev) { - fprintf(stderr, "\nERROR: ICH2 LPC bridge not found.\n"); - return -1; - } - - /* Use GPIOBASE register to find where the GPIO is mapped. */ - port = (pci_read_word(dev, 0x58) & 0xFFC0) + 0xE; - - val = INB(port); - val |= 0x80; /* Top Block Lock -- pin 8 of PLCC32 */ - val |= 0x40; /* Lower Blocks Lock -- pin 7 of PLCC32 */ - OUTB(val, port); - - return 0; -} - -/** * Suited for Artec Group DBE61 and DBE62. */ static int board_artecgroup_dbe6x(const char *name) @@ -590,103 +564,233 @@ static int board_artecgroup_dbe6x(const char *name) } /** - * Set the specified GPIO on the specified ICHx southbridge to high. + * Raises a GPIO line on intel ICH, ICH0 and ICH2 through ICH10 southbridges. * - * @param name The name of this board. - * @param ich_vendor PCI vendor ID of the specified ICHx southbridge. - * @param ich_device PCI device ID of the specified ICHx southbridge. - * @param gpiobase_reg GPIOBASE register offset in the LPC bridge. - * @param gp_lvl Offset of GP_LVL register in I/O space, relative to GPIOBASE. - * @param gp_lvl_bitmask GP_LVL bitmask (set GPIO bits to 1, all others to 0). - * @param gpio_bit The bit (GPIO) which shall be set to high. - * @return If the write-enable was successful return 0, otherwise return -1. + * GPIO lines are not actually checked. + * More than 32 GPIO pins only become available with the ICH3. + * From ICH10, a third bank appears, but ICH10 only implements GPIO72. + * + * In hardware, the GPIO BARs have the lower bits (5:1) zeroed, starting + * with a mobile ich9 version bits 6:1 are zeroed. The 0xFFC0 mask should + * catch all just fine. + */ +static void intel_ich_gpio_raise(struct pci_dev *dev, unsigned int gpio) +{ + uint16_t base; + uint32_t tmp; + + /* get PM IO base */ + switch (dev->device_id) { + case 0x2410: /* 82801AA (ICH) */ + case 0x2420: /* 82801AB (ICH0) */ + case 0x2440: /* 82801BA (ICH2) */ + case 0x244C: /* 82801BAM (ICH2M) */ + case 0x2450: /* 82801E (C-ICH) */ + case 0x2480: /* 82801CA (ICH3-S) */ + case 0x248C: /* 82801CAM (ICH3-M) */ + case 0x24C0: /* 82801DB/DBL (ICH4/ICH4-L) */ + case 0x24CC: /* 82801DBM (ICH4-M) */ + case 0x24D0: /* 82801EB/ER (ICH5/ICH5R) */ + case 0x24DC: /* 82801EB (ICH5) */ + base = pci_read_long(dev, 0x58) & 0x0000FFC0; + break; + case 0x2640: /* 82801FB/FR (ICH6/ICH6R) */ + case 0x2641: /* 82801FBM (ICH6M) */ + case 0x2642: /* 82801FW/FRW (ICH6W/ICH6RW) */ + case 0x27B0: /* 82801GH (ICH7DH) */ + case 0x27B8: /* 82801GB/GR (ICH7 Family) */ + case 0x27B9: /* 82801GBM (ICH7-M) */ + case 0x27BD: /* 82801GHM (ICH7-M DH) */ + case 0x2810: /* 82801HB/HR (ICH8/R) */ + case 0x2811: /* 82801HBM (ICH8M-E) */ + case 0x2812: /* 82801HH (ICH8DH) */ + case 0x2814: /* 82801HO (ICH8DO) */ + case 0x2815: /* 82801HEM (ICH8M) */ + case 0x2912: /* 82801IH (ICH9DH) */ + case 0x2914: /* 82801IO (ICH9DO) */ + case 0x2916: /* 82801IR (ICH9R) */ + case 0x2917: /* 82801IEM (ICH9M-E) */ + case 0x2918: /* 82801IB (ICH9) */ + case 0x2919: /* 82801IBM (ICH9M) */ + case 0x3A14: /* 82801JDO (ICH10DO) */ + case 0x3A16: /* 82801JIR (ICH10R) */ + case 0x3A18: /* 82801JIB (ICH10) */ + case 0x3A1A: /* 82801JD (ICH10D) */ + base = pci_read_long(dev, 0x48) & 0x0000FFC0; + break; + default: + fprintf(stderr, "\nERROR: Unknown Intel ICH: 0x%04X.\n", + dev->device_id); + return; + } + + if (gpio < 32) { + /* Set line to GPIO */ + tmp = INL(base); + /* ICH/ICH0 multiplexes 27/28 on the line set. */ + if ((gpio == 28) && + ((dev->device_id == 0x2410) || (dev->device_id == 0x2420))) + tmp |= 1 << 27; + else + tmp |= 1 << gpio; + OUTL(tmp, base); + + /* Set GPIO to OUTPUT */ + tmp = INL(base + 0x04); + tmp &= ~(1 << gpio); + OUTL(tmp, base + 0x04); + + /* Raise GPIO line */ + tmp = INL(base + 0x0C); + tmp |= 1 << gpio; + OUTL(tmp, base + 0x0C); + } else { + gpio -= 32; + + /* Set line to GPIO */ + tmp = INL(base + 0x30); + tmp |= 1 << gpio; + OUTL(tmp, base + 0x30); + + /* Set GPIO to OUTPUT */ + tmp = INL(base + 0x34); + tmp &= ~(1 << gpio); + OUTL(tmp, base + 0x34); + + /* Raise GPIO line */ + tmp = INL(base + 0x38); + tmp |= 1 << gpio; + OUTL(tmp, base + 0x38); + } +} + +/** + * Suited for ASUS P4B266: socket478 + intel 845D + ICH2. */ -static int ich_gpio_raise(const char *name, uint16_t ich_vendor, - uint16_t ich_device, uint8_t gpiobase_reg, - uint8_t gp_lvl, uint32_t gp_lvl_bitmask, - unsigned int gpio_bit) +static int board_asus_p4b266(const char *name) { struct pci_dev *dev; - uint16_t gpiobar; - uint32_t reg32; - dev = pci_dev_find(ich_vendor, ich_device); /* Intel ICHx LPC */ + dev = pci_dev_find(0x8086, 0x2440); /* Intel ICH2 ISA Bridge */ if (!dev) { - fprintf(stderr, "\nERROR: ICHx LPC dev %4x:%4x not found.\n", - ich_vendor, ich_device); + fprintf(stderr, "\nERROR: Intel ICH2 ISA Bridge not found.\n"); return -1; } - /* Use GPIOBASE register to find the I/O space for GPIO. */ - gpiobar = pci_read_word(dev, gpiobase_reg) & gp_lvl_bitmask; + intel_ich_gpio_raise(dev, 22); + + return 0; +} - /* Set specified GPIO to high. */ - reg32 = INL(gpiobar + gp_lvl); - reg32 |= (1 << gpio_bit); - OUTL(reg32, gpiobar + gp_lvl); +/** + * Suited for Acorp 6A815EPD: socket 370 + intel 815 + ICH2. + */ +static int board_acorp_6a815epd(const char *name) +{ + struct pci_dev *dev; + + dev = pci_dev_find(0x8086, 0x2440); /* Intel ICH2 LPC */ + if (!dev) { + fprintf(stderr, "\nERROR: Intel ICH2 ISA bridge not found.\n"); + return -1; + } + + intel_ich_gpio_raise(dev, 22); /* Lower Blocks Lock -- pin 7 of PLCC32 */ + intel_ich_gpio_raise(dev, 23); /* Top Block Lock -- pin 8 of PLCC32 */ return 0; } /** - * Suited for ASUS P4B266. + * Suited for Asus P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R. */ -static int ich2_gpio22_raise(const char *name) +static int board_asus_p4p800(const char *name) { - return ich_gpio_raise(name, 0x8086, 0x2440, 0x58, 0x0c, 0xffc0, 22); + struct pci_dev *dev; + + dev = pci_dev_find(0x8086, 0x24D0); /* Intel ICH5R ISA Bridge */ + if (!dev) { + fprintf(stderr, "\nERROR: Intel ICH5 ISA Bridge not found.\n"); + return -1; + } + + intel_ich_gpio_raise(dev, 21); + + return 0; } /** - * Suited for the Dell PowerEdge 1850. All parameters except the last one are - * documented in the public Intel 82801EB ICH5 / 82801ER ICH5R datasheet. The - * last parameter (GPIO number) has to be in the range [16,31] according to - * said Intel datasheet and was found by exhaustive search. + * Suited for Dell Poweredge 1850: Intel PPGA604 + E7520 + ICH5R. + * + * The GPIO number has to be in the range [16,31] according to the public Intel + * 82801EB ICH5 / 82801ER ICH5R datasheet and was found by exhaustive search. */ -static int ich5_gpio23_raise(const char *name) +static int board_dell_pe_1850(const char *name) { - return ich_gpio_raise(name, 0x8086, 0x24d0, 0x58, 0x0c, 0xffc0, 23); + struct pci_dev *dev; + + dev = pci_dev_find(0x8086, 0x24D0); /* Intel ICH5R ISA Bridge */ + if (!dev) { + fprintf(stderr, "\nERROR: Intel ICH5 ISA Bridge not found.\n"); + return -1; + } + + intel_ich_gpio_raise(dev, 23); + + return 0; } /** - * Suited for MSI MS-7046. + * Suited for MSI MS-7046: LGA775 + 915P + ICH6. */ -static int ich6_gpio19_raise(const char *name) +static int board_msi_ms7046(const char *name) { - return ich_gpio_raise(name, 0x8086, 0x2640, 0x48, 0x0c, 0xffc0, 19); + struct pci_dev *dev; + + dev = pci_dev_find(0x8086, 0x2640); /* Intel ICH6 LPC Interface */ + if (!dev) { + fprintf(stderr, "\nERROR: Intel ICH9R LPC not found.\n"); + return -1; + } + + intel_ich_gpio_raise(dev, 19); + + return 0; } +/** + * Suited for Kontron 986LCD-M: socket478 + 915GM + ICH7R. + */ static int board_kontron_986lcd_m(const char *name) { struct pci_dev *dev; - uint16_t gpiobar; - uint32_t val; - -#define ICH7_GPIO_LVL2 0x38 dev = pci_dev_find(0x8086, 0x27b8); /* Intel ICH7 LPC */ if (!dev) { - // This will never happen on this board - fprintf(stderr, "\nERROR: ICH7 LPC bridge not found.\n"); + fprintf(stderr, "\nERROR: Intel ICH7 LPC bridge not found.\n"); return -1; } - /* Use GPIOBASE register to find where the GPIO is mapped. */ - gpiobar = pci_read_word(dev, 0x48) & 0xfffc; + intel_ich_gpio_raise(dev, 34); /* #TBL */ + intel_ich_gpio_raise(dev, 35); /* #WP */ - val = INL(gpiobar + ICH7_GPIO_LVL2); /* GP_LVL2 */ - printf_debug("\nGPIOBAR=0x%04x GP_LVL: 0x%08x\n", gpiobar, val); + return 0; +} - /* bit 2 (0x04) = 0 #TBL --> bootblock locking = 1 - * bit 2 (0x04) = 1 #TBL --> bootblock locking = 0 - * bit 3 (0x08) = 0 #WP --> block locking = 1 - * bit 3 (0x08) = 1 #WP --> block locking = 0 - * - * To enable full block locking, you would do: - * val &= ~ ((1 << 2) | (1 << 3)); - */ - val |= (1 << 2) | (1 << 3); +/** + * Suited for Abit IP35: Intel P35 + ICH9R. + */ +static int board_abit_ip35(const char *name) +{ + struct pci_dev *dev; + + dev = pci_dev_find(0x8086, 0x2916); /* Intel ICH9R LPC Interface */ + if (!dev) { + fprintf(stderr, "\nERROR: Intel ICH9R LPC not found.\n"); + return -1; + } - OUTL(val, gpiobar + ICH7_GPIO_LVL2); + intel_ich_gpio_raise(dev, 16); return 0; } @@ -881,32 +985,6 @@ static int board_mitac_6513wu(const char *name) } /** - * Suited for Abit IP35: Intel P35 + ICH9R. - */ -static int board_abit_ip35(const char *name) -{ - struct pci_dev *dev; - uint16_t base; - uint8_t tmp; - - dev = pci_dev_find(0x8086, 0x2916); /* Intel ICH9R LPC Interface */ - if (!dev) { - fprintf(stderr, "\nERROR: Intel ICH9R LPC not found.\n"); - return -1; - } - - /* get LPC GPIO base */ - base = pci_read_long(dev, 0x48) & 0x0000FFC0; - - /* Raise GPIO 16 */ - tmp = INB(base + 0x0E); - tmp |= 0x01; - OUTB(tmp, base + 0x0E); - - return 0; -} - -/** * Suited for Asus A7V8X: VIA KT400 + VT8235 + IT8703F-A */ static int board_asus_a7v8x(const char *name) @@ -1009,32 +1087,6 @@ static int board_asus_a7v600x(const char *name) } /** - * Suited for Asus P4P800-E Deluxe: Intel Intel 865PE + ICH5R. - */ -static int board_asus_p4p800(const char *name) -{ - struct pci_dev *dev; - uint16_t base; - uint8_t tmp; - - dev = pci_dev_find(0x8086, 0x24D0); /* Intel ICH5R ISA Bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: Intel ICH5R ISA Bridge not found.\n"); - return -1; - } - - /* get PM IO base */ - base = pci_read_long(dev, 0x58) & 0x0000FFC0; - - /* Raise GPIO 21 */ - tmp = INB(base + 0x0E); - tmp |= 0x20; - OUTB(tmp, base + 0x0E); - - return 0; -} - -/** * Below is the list of boards which need a special "board enable" code in * flashrom before their ROM chip can be accessed/written to. * @@ -1073,12 +1125,12 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, "ASUS", "A7V600-X", board_asus_a7v600x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, "ASUS", "A7V8X", board_asus_a7v8x}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", board_asus_a7v8x_mx}, - {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", ich2_gpio22_raise}, + {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", board_asus_p4b266}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", board_asus_p4p800}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", board_asus_p5nd2_sli}, {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable}, - {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "PowerEdge 1850", ich5_gpio23_raise}, + {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "PowerEdge 1850", board_dell_pe_1850}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", board_epox_ep_8k5a2}, {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", board_epox_ep_8rda3plus}, @@ -1103,7 +1155,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, "msi", "kt4ultra", "MSI", "MS-6590 (KT4 Ultra)",board_msi_kt4v}, {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)",w83627thf_gpio4_4_raise_2e}, {0x1106, 0x0571, 0x1462, 0x7120, 0, 0, 0, 0, "msi", "kt4v", "MSI", "MS-6712 (KT4V)", board_msi_kt4v}, - {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", ich6_gpio19_raise}, + {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", board_msi_ms7046}, {0x10de, 0x005e, 0, 0, 0, 0, 0, 0, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25}, -- 1.6.0.2 --KsGdsel6WgEHnImy--

1 0

Remove board enable for Asus P5A.
by Luc Verhaegen Oct. 23, 2009

Oct. 23, 2009

A first: removal of what might be a working board enable still. Long story short; it's horrible and i do not want to spend any time on cleaning it up. We have better things to do. Luc Verhaegen.

2 2

ASUS A8V support
by Aaron Smith Oct. 22, 2009

Oct. 22, 2009

I'd like to report that flashrom worked great in upgrading the BIOS on my ASUS A8V motherboard. The product page is here: http://www.asus.com/product.aspx?P_ID=Yw0JOuUibSPSWxMo I see other A8V models listed on the wiki, but don't see this one listed. Let me know if you need any other info. Thanks, @@ron

2 2

[PATCH] Silence ICH preop debug message
by Carl-Daniel Hailfinger Oct. 22, 2009

Oct. 22, 2009

Since we don't have any debug level printing infrastructure yet, I propose to kill the obnoxious debug message in ichspi.c which was added to check for correct PREOP handling. We know the code works fine (after getting a few reports over 100 MB long) and there's no point in keeping it around anymore. If there is any desire, we can reinstate it as print_spew or whatever once the debug level infrastructure is merged, but at that point we probably just are happy that the debug output isn't there anymore. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ich_preop_silence/ichspi.c =================================================================== --- flashrom-ich_preop_silence/ichspi.c (Revision 752) +++ flashrom-ich_preop_silence/ichspi.c (Arbeitskopie) @@ -756,11 +756,8 @@ * opcode of the next command? */ if ((oppos != -1) && (preoppos != -1) && - (curopcodes->opcode[oppos].atomic - 1 == preoppos)) { - printf_debug("opcode 0x%02x will be run as PREOP\n", - cmds->writearr[0]); + (curopcodes->opcode[oppos].atomic - 1 == preoppos)) continue; - } } ret = ich_spi_send_command(cmds->writecnt, cmds->readcnt, -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

3 3

[commit] r753 - trunk
by svn＠flashrom.org Oct. 22, 2009

Oct. 22, 2009

Author: hailfinger Date: 2009-10-22 17:07:30 +0200 (Thu, 22 Oct 2009) New Revision: 753 Modified: trunk/ichspi.c Log: Since we don't have any debug level printing infrastructure yet, I propose to kill the obnoxious debug message in ichspi.c which was added to check for correct PREOP handling. We know the code works fine (after getting a few reports over 100 MB long) and there's no point in keeping it around anymore. If there is any desire, we can reinstate it as print_spew or whatever once the debug level infrastructure is merged, but at that point we probably just are happy that the debug output isn't there anymore. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Luc Verhaegen <libv(a)skynet.be> Modified: trunk/ichspi.c =================================================================== --- trunk/ichspi.c 2009-10-21 12:05:50 UTC (rev 752) +++ trunk/ichspi.c 2009-10-22 15:07:30 UTC (rev 753) @@ -756,11 +756,8 @@ * opcode of the next command? */ if ((oppos != -1) && (preoppos != -1) && - (curopcodes->opcode[oppos].atomic - 1 == preoppos)) { - printf_debug("opcode 0x%02x will be run as PREOP\n", - cmds->writearr[0]); + ((curopcodes->opcode[oppos].atomic - 1) == preoppos)) continue; - } } ret = ich_spi_send_command(cmds->writecnt, cmds->readcnt,

1 0

bios flash succeeded on ASUS P5L-MX (untested flash part)
by Linda Oct. 21, 2009

Oct. 21, 2009

Dear coreboot team, I just succesfully flashed my bios on a ASUS P5L-MX motherboard. flashrom detects two flash chips, SST25VF040B and SST25VF040B.REMS with the -c option I chose the first, without the -c option flashrom would not perform any action. I'd be happy to give more information if needed. Thanks for making this very nice tool :-) Kind regards Linda Polman 1. writing: 2. ======================================================================================== 3. 4. linda@tuxbox:~/LMX1103$ sudo flashrom -c SST25VF040B -wV LMX1103.ROM 5. flashrom v0.9.1-r706 6. No coreboot table found. 7. Found chipset "Intel ICH7/ICH7R", enabling flash write... 8. 0xfff80000/0xffb80000 FWH IDSEL: 0x0 9. 0xfff00000/0xffb00000 FWH IDSEL: 0x0 10. 0xffe80000/0xffa80000 FWH IDSEL: 0x1 11. 0xffe00000/0xffa00000 FWH IDSEL: 0x1 12. 0xffd80000/0xff980000 FWH IDSEL: 0x2 13. 0xffd00000/0xff900000 FWH IDSEL: 0x2 14. 0xffc80000/0xff880000 FWH IDSEL: 0x3 15. 0xffc00000/0xff800000 FWH IDSEL: 0x3 16. 0xff700000/0xff300000 FWH IDSEL: 0x4 17. 0xff600000/0xff200000 FWH IDSEL: 0x5 18. 0xff500000/0xff100000 FWH IDSEL: 0x6 19. 0xff400000/0xff000000 FWH IDSEL: 0x7 20. 0xfff80000/0xffb80000 FWH decode enabled 21. 0xfff00000/0xffb00000 FWH decode disabled 22. 0xffe80000/0xffa80000 FWH decode disabled 23. 0xffe00000/0xffa00000 FWH decode disabled 24. 0xffd80000/0xff980000 FWH decode disabled 25. 0xffd00000/0xff900000 FWH decode disabled 26. 0xffc80000/0xff880000 FWH decode disabled 27. 0xffc00000/0xff800000 FWH decode disabled 28. 0xff700000/0xff300000 FWH decode disabled 29. 0xff600000/0xff200000 FWH decode disabled 30. 0xff500000/0xff100000 FWH decode disabled 31. 0xff400000/0xff000000 FWH decode disabled 32. BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1 33. 34. Root Complex Register Block address = 0xfed1c000 35. GCS = 0x464: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) 36. Top Swap : not enabled 37. SPIBAR = 0xfed1c000 + 0x3020 38. 0x00: 0x0004 (SPIS) 39. 0x02: 0x4260 (SPIC) 40. 0x04: 0x00000000 (SPIA) 41. 0x08: 0xbf8d25bf (SPID0) 42. 0x0c: 0x00000000 (SPID0+4) 43. 0x10: 0x00000000 (SPID1) 44. 0x14: 0x0000471d (SPID1+4) 45. 0x18: 0x50120000 (SPID2) 46. 0x1c: 0x00495100 (SPID2+4) 47. 0x20: 0x00000100 (SPID3) 48. 0x24: 0x00000040 (SPID3+4) 49. 0x28: 0x30363041 (SPID4) 50. 0x2c: 0x30303035 (SPID4+4) 51. 0x30: 0x00000000 (SPID5) 52. 0x34: 0x00000000 (SPID5+4) 53. 0x38: 0x00ffaaea (SPID6) 54. 0x3c: 0x2f3830f0 (SPID6+4) 55. 0x40: 0x302f3532 (SPID7) 56. 0x44: 0x00fc0036 (SPID7+4) 57. 0x50: 0x00000000 (BBAR) 58. 0x54: 0x0006 (PREOP) 59. 0x56: 0x463b (OPTYPE) 60. 0x58: 0x05d80302 (OPMENU) 61. 0x5c: 0xc79f0190 (OPMENU+4) 62. 0x60: 0x00000000 (PBR0) 63. 0x64: 0x00000000 (PBR1) 64. 0x68: 0x00000000 (PBR2) 65. 0x6c: 0x00000000 (PBR3) 66. 67. Programming OPCODES... 68. program_opcodes: preop=0006 optype=463b opmenu=05d80302c79f0190 69. done 70. SPI Read Configuration: prefetching disabled, caching enabled, OK. 71. This chipset supports the following protocols: SPI. 72. Calibrating delay loop... 626M loops per second, 100 myus = 157 us. OK. 73. Probing for SST SST25VF040B, 512 KB: RDID returned 0xbf 0x25 0x8d. probe_spi_rdid_generic: id1 0xbf, id2 0x258d 74. Chip status register is 00 75. Chip status register: Block Protect Write Disable (BPL) is not set 76. Chip status register: Auto Address Increment Programming (AAI) is not set 77. Chip status register: Bit 5 / Block Protect 3 (BP3) is not set 78. Chip status register: Bit 4 / Block Protect 2 (BP2) is not set 79. Chip status register: Bit 3 / Block Protect 1 (BP1) is not set 80. Chip status register: Bit 2 / Block Protect 0 (BP0) is not set 81. Chip status register: Write Enable Latch (WEL) is not set 82. Chip status register: Write In Progress (WIP/BUSY) is not set 83. Resulting block protection : none 84. Found chip "SST SST25VF040B" (512 KB, SPI) at physical address 0xfff80000. 85. === 86. This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE 87. Please email a report to flashrom(a)flashrom.org if any of the above operations 88. work correctly for you with this flash part. Please include the flashrom 89. output with the additional -V option for all operations you tested (-V, -rV, 90. -wV, -EV), and mention which mainboard you tested. Thanks for your help! 91. === 92. Flash image seems to be a legacy BIOS. Disabling checks. 93. Writing flash chip... Erasing flash before programming... Invalid OPCODE 0x06 94. due to SPI master limitation, ignoring and hoping it will be run as PREOP 95. done. 96. Invalid OPCODE 0x06 97. due to SPI master limitation, ignoring and hoping it will be run as PREOP 98. Invalid OPCODE 0x06 99. due to SPI master limitation, ignoring and hoping it will be run as PREOP 100. Invalid OPCODE 0x06 101. due to SPI master limitation, ignoring and hoping it will be run as PREOP 102. Invalid OPCODE 0x06 103. due to SPI master limitation, ignoring and hoping it will be run as PREOP 104. Invalid OPCODE 0x06 105. due to SPI master limitation, ignoring and hoping it will be run as PREOP 106. Invalid OPCODE 0x06 107. due to SPI master limitation, ignoring and hoping it will be run as PREOP 108. Invalid OPCODE 0x06 109. due to SPI master limitation, ignoring and hoping it will be run as PREOP 110. Invalid OPCODE 0x06 111. due to SPI master limitation, ignoring and hoping it will be run as PREOP 112. Invalid OPCODE 0x06 113. due to SPI master limitation, ignoring and hoping it will be run as PREOP 114. 115. <few hundred times more the same error line> 116. 117. Invalid OPCODE 0x06 118. due to SPI master limitation, ignoring and hoping it will be run as PREOP 119. Invalid OPCODE 0x06 120. due to SPI master limitation, ignoring and hoping it will be run as PREOP 121. Invalid OPCODE 0x06 122. due to SPI master limitation, ignoring and hoping it will be run as PREOP 123. COMPLETE. 124. Verifying flash... VERIFIED. 125. 126. 127. 128. ====================================================================================== 129. Checking: 130. 131. linda@tuxbox:~/LMX1103$ sudo flashrom -c SST25VF040B -vV LMX1103.ROM 132. flashrom v0.9.1-r706 133. No coreboot table found. 134. Found chipset "Intel ICH7/ICH7R", enabling flash write... 135. 0xfff80000/0xffb80000 FWH IDSEL: 0x0 136. 0xfff00000/0xffb00000 FWH IDSEL: 0x0 137. 0xffe80000/0xffa80000 FWH IDSEL: 0x1 138. 0xffe00000/0xffa00000 FWH IDSEL: 0x1 139. 0xffd80000/0xff980000 FWH IDSEL: 0x2 140. 0xffd00000/0xff900000 FWH IDSEL: 0x2 141. 0xffc80000/0xff880000 FWH IDSEL: 0x3 142. 0xffc00000/0xff800000 FWH IDSEL: 0x3 143. 0xff700000/0xff300000 FWH IDSEL: 0x4 144. 0xff600000/0xff200000 FWH IDSEL: 0x5 145. 0xff500000/0xff100000 FWH IDSEL: 0x6 146. 0xff400000/0xff000000 FWH IDSEL: 0x7 147. 0xfff80000/0xffb80000 FWH decode enabled 148. 0xfff00000/0xffb00000 FWH decode disabled 149. 0xffe80000/0xffa80000 FWH decode disabled 150. 0xffe00000/0xffa00000 FWH decode disabled 151. 0xffd80000/0xff980000 FWH decode disabled 152. 0xffd00000/0xff900000 FWH decode disabled 153. 0xffc80000/0xff880000 FWH decode disabled 154. 0xffc00000/0xff800000 FWH decode disabled 155. 0xff700000/0xff300000 FWH decode disabled 156. 0xff600000/0xff200000 FWH decode disabled 157. 0xff500000/0xff100000 FWH decode disabled 158. 0xff400000/0xff000000 FWH decode disabled 159. BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1 160. 161. Root Complex Register Block address = 0xfed1c000 162. GCS = 0x464: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) 163. Top Swap : not enabled 164. SPIBAR = 0xfed1c000 + 0x3020 165. 0x00: 0x0004 (SPIS) 166. 0x02: 0x7f10 (SPIC) 167. 0x04: 0x0007ffc0 (SPIA) 168. 0x08: 0x0000004d (SPID0) 169. 0x0c: 0x00000000 (SPID0+4) 170. 0x10: 0x00000000 (SPID1) 171. 0x14: 0x0000471d (SPID1+4) 172. 0x18: 0x50120000 (SPID2) 173. 0x1c: 0x00495100 (SPID2+4) 174. 0x20: 0x00000100 (SPID3) 175. 0x24: 0x00000040 (SPID3+4) 176. 0x28: 0x30363041 (SPID4) 177. 0x2c: 0x30303035 (SPID4+4) 178. 0x30: 0x00000000 (SPID5) 179. 0x34: 0x00000000 (SPID5+4) 180. 0x38: 0x00ffaaea (SPID6) 181. 0x3c: 0x2f3231f0 (SPID6+4) 182. 0x40: 0x302f3231 (SPID7) 183. 0x44: 0x00fc0037 (SPID7+4) 184. 0x50: 0x00000000 (BBAR) 185. 0x54: 0x0006 (PREOP) 186. 0x56: 0x463b (OPTYPE) 187. 0x58: 0x05d80302 (OPMENU) 188. 0x5c: 0xc79f0190 (OPMENU+4) 189. 0x60: 0x00000000 (PBR0) 190. 0x64: 0x00000000 (PBR1) 191. 0x68: 0x00000000 (PBR2) 192. 0x6c: 0x00000000 (PBR3) 193. 194. Programming OPCODES... 195. program_opcodes: preop=0006 optype=463b opmenu=05d80302c79f0190 196. done 197. SPI Read Configuration: prefetching disabled, caching enabled, OK. 198. This chipset supports the following protocols: SPI. 199. Calibrating delay loop... 784M loops per second, 100 myus = 197 us. OK. 200. Probing for SST SST25VF040B, 512 KB: RDID returned 0xbf 0x25 0x8d. probe_spi_rdid_generic: id1 0xbf, id2 0x258d 201. Chip status register is 00 202. Chip status register: Block Protect Write Disable (BPL) is not set 203. Chip status register: Auto Address Increment Programming (AAI) is not set 204. Chip status register: Bit 5 / Block Protect 3 (BP3) is not set 205. Chip status register: Bit 4 / Block Protect 2 (BP2) is not set 206. Chip status register: Bit 3 / Block Protect 1 (BP1) is not set 207. Chip status register: Bit 2 / Block Protect 0 (BP0) is not set 208. Chip status register: Write Enable Latch (WEL) is not set 209. Chip status register: Write In Progress (WIP/BUSY) is not set 210. Resulting block protection : none 211. Found chip "SST SST25VF040B" (512 KB, SPI) at physical address 0xfff80000. 212. === 213. This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE 214. Please email a report to flashrom(a)flashrom.org if any of the above operations 215. work correctly for you with this flash part. Please include the flashrom 216. output with the additional -V option for all operations you tested (-V, -rV, 217. -wV, -EV), and mention which mainboard you tested. Thanks for your help! 218. === 219. Flash image seems to be a legacy BIOS. Disabling checks. 220. Verifying flash... VERIFIED.

2 1

lspci -vvnnxxx for Asrock P4i65GV
by Idwer Vollering Oct. 21, 2009

Oct. 21, 2009

This pretty much is an attempt to save the board from this thread: http://www.coreboot.org/pipermail/flashrom/2009-October/thread.html#775 --- Sending a lspci -vvnnxxx, as requested by libv on irc. Board: http://www.asrock.com/MB/overview.asp?Model=P4i65GV lspci -vvnnxxx: 00:00.0 Host bridge [0600]: Intel Corporation 82865G/PE/P DRAM Controller/Host-Hub Interface [8086:2570] (rev 02) Subsystem: ASRock Incorporation Device [1849:2570] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- Latency: 0 Region 0: Memory at fe800000 (32-bit, prefetchable) [size=4M] Capabilities: [e4] Vendor Specific Information <?> Kernel driver in use: agpgart-intel Kernel modules: intel-agp 00: 86 80 70 25 06 00 90 20 02 00 00 06 00 00 00 00 10: 08 00 80 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 70 25 30: 00 00 00 00 e4 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 34 00 40 80 1c 00 00 00 00 00 00 00 00 00 60: 00 05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 10 11 01 00 00 33 33 00 00 00 00 00 00 0a 38 00 a0: 02 00 30 00 17 42 00 1f 00 00 00 00 00 00 00 00 b0: 00 00 00 00 3f 00 00 00 00 00 00 00 20 10 00 00 c0: 00 00 00 00 80 1f 0e 20 00 01 00 00 00 00 00 00 d0: 02 28 04 0e 0b 0d 00 00 00 00 00 00 00 00 40 01 e0: 00 00 00 00 09 00 06 11 00 02 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 68 0f 03 00 00 00 00 00 00:02.0 VGA compatible controller [0300]: Intel Corporation 82865G Integrated Graphics Controller [8086:2572] (rev 02) Subsystem: ASRock Incorporation Device [1849:2572] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 16 Region 0: Memory at f0000000 (32-bit, prefetchable) [size=128M] Region 1: Memory at fe780000 (32-bit, non-prefetchable) [size=512K] Region 2: I/O ports at ec00 [size=8] Capabilities: [d0] Power Management version 1 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel modules: intelfb 00: 86 80 72 25 07 00 90 00 02 00 00 03 00 00 00 00 10: 08 00 00 f0 00 00 78 fe 01 ec 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 72 25 30: 00 00 00 00 d0 00 00 00 00 00 00 00 0a 01 00 00 40: 00 00 00 00 e0 23 e0 11 00 00 00 00 00 00 00 00 50: 00 00 34 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 01 00 00 00 00 00 01 02 ff 00 00 00 71 02 10 20 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 51 ff ff 51 ff ff 00 00 b0: 02 04 00 00 44 00 00 00 d5 1b ff 9f 7b 40 59 00 c0: 00 00 00 00 80 1f 0e 20 00 00 00 00 00 00 00 00 d0: 01 00 21 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 01 00 00 00 09 00 06 11 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 68 0f 03 00 00 00 00 00 00:1d.0 USB Controller [0c03]: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #1 [8086:24d2] (rev 02) Subsystem: ASRock Incorporation Device [1849:24d0] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 16 Region 4: I/O ports at dc00 [size=32] Kernel driver in use: uhci_hcd 00: 86 80 d2 24 05 00 80 02 02 00 03 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 dc 00 00 00 00 00 00 00 00 00 00 49 18 d0 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 66 0f 05 00 00 00 00 00 00:1d.1 USB Controller [0c03]: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #2 [8086:24d4] (rev 02) Subsystem: ASRock Incorporation Device [1849:24d0] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 19 Region 4: I/O ports at e000 [size=32] Kernel driver in use: uhci_hcd 00: 86 80 d4 24 05 00 80 02 02 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 e0 00 00 00 00 00 00 00 00 00 00 49 18 d0 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 06 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 66 0f 05 00 00 00 00 00 00:1d.2 USB Controller [0c03]: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #3 [8086:24d7] (rev 02) Subsystem: ASRock Incorporation Device [1849:24d0] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin C routed to IRQ 18 Region 4: I/O ports at e400 [size=32] Kernel driver in use: uhci_hcd 00: 86 80 d7 24 05 00 80 02 02 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 e4 00 00 00 00 00 00 00 00 00 00 49 18 d0 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 05 03 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 66 0f 05 00 00 00 00 00 00:1d.3 USB Controller [0c03]: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #4 [8086:24de] (rev 02) Subsystem: ASRock Incorporation Device [1849:24d0] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 16 Region 4: I/O ports at e800 [size=32] Kernel driver in use: uhci_hcd 00: 86 80 de 24 05 00 80 02 02 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 e8 00 00 00 00 00 00 00 00 00 00 49 18 d0 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 66 0f 05 00 00 00 00 00 00:1d.7 USB Controller [0c03]: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller [8086:24dd] (rev 02) (prog-if 20) Subsystem: ASRock Incorporation Device [1849:24d0] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin D routed to IRQ 23 Region 0: Memory at fe77bc00 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Debug port: BAR=1 offset=00a0 Kernel driver in use: ehci_hcd 00: 86 80 dd 24 06 01 90 02 02 20 03 0c 00 00 00 00 10: 00 bc 77 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 d0 24 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 04 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 c2 c9 00 00 00 00 0a 00 a0 20 00 00 00 00 60: 20 20 ff 01 00 00 00 00 01 00 00 00 00 00 08 c0 70: 00 00 dd 3f 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 55 55 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 80 00 00 88 83 40 00 66 0f 05 00 06 14 00 00 00:1e.0 PCI bridge [0604]: Intel Corporation 82801 PCI Bridge [8086:244e] (rev c2) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=32 I/O behind bridge: 0000b000-0000bfff Memory behind bridge: fe500000-fe5fffff Prefetchable memory behind bridge: 20000000-200fffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Kernel modules: shpchp 00: 86 80 4e 24 07 01 80 00 c2 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 20 b0 b0 80 02 20: 50 fe 50 fe 00 20 00 20 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 06 00 40: 02 28 30 76 00 00 00 00 00 00 00 00 00 00 00 00 50: 02 64 73 00 00 00 00 00 50 01 34 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 01 00 02 00 00 00 c0 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 66 0f 05 00 00 00 53 31 00:1f.0 ISA bridge [0601]: Intel Corporation 82801EB/ER (ICH5/ICH5R) LPC Interface Bridge [8086:24d0] (rev 02) Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Kernel modules: iTCO_wdt, intel-rng 00: 86 80 d0 24 0f 00 80 02 02 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 08 00 00 10 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 81 04 00 00 10 00 00 00 60: 8a 8a 85 86 d0 00 00 00 8a 80 8a 8b 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: ff fc 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 20 02 00 00 39 00 00 00 0d 00 00 00 00 03 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 86 21 02 00 02 00 00 00 04 00 00 00 00 00 00 00 e0: 00 00 00 80 00 00 08 14 33 22 11 00 00 00 67 45 f0: 00 00 44 00 04 00 00 00 66 0f 05 3e 00 00 00 00 00:1f.1 IDE interface [0101]: Intel Corporation 82801EB/ER (ICH5/ICH5R) IDE Controller [8086:24db] (rev 02) (prog-if 8a [Master SecP PriP]) Subsystem: ASRock Incorporation Device [1849:24d0] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 18 Region 0: I/O ports at 01f0 [size=8] Region 1: I/O ports at 03f4 [size=1] Region 2: I/O ports at 0170 [size=8] Region 3: I/O ports at 0374 [size=1] Region 4: I/O ports at fc00 [size=16] Region 5: Memory at 20100000 (32-bit, non-prefetchable) [size=1K] Kernel driver in use: ata_piix 00: 86 80 db 24 07 00 80 02 02 8a 01 01 00 00 00 00 10: 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 20: 01 fc 00 00 00 00 10 20 00 00 00 00 49 18 d0 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40: 07 e3 37 e3 b0 00 00 00 0d 00 01 22 00 00 00 00 50: 00 00 00 00 30 10 00 00 00 00 00 00 00 00 00 00 60: 08 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 66 0f 05 00 00 00 00 00 00:1f.3 SMBus [0c05]: Intel Corporation 82801EB/ER (ICH5/ICH5R) SMBus Controller [8086:24d3] (rev 02) Subsystem: ASRock Incorporation Device [1849:24d0] Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin B routed to IRQ 10 Region 4: I/O ports at 0400 [size=32] Kernel modules: i2c-i801 00: 86 80 d3 24 01 00 80 02 02 00 05 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 04 00 00 00 00 00 00 00 00 00 00 49 18 d0 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 02 00 00 40: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 66 0f 05 00 00 00 00 00 00:1f.5 Multimedia audio controller [0401]: Intel Corporation 82801EB/ER (ICH5/ICH5R) AC'97 Audio Controller [8086:24d5] (rev 02) Subsystem: ASRock Incorporation Device [1849:9739] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 17 Region 0: I/O ports at d800 [size=256] Region 1: I/O ports at d400 [size=64] Region 2: Memory at fe77b800 (32-bit, non-prefetchable) [size=512] Region 3: Memory at fe77b400 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: Intel ICH Kernel modules: snd-intel8x0 00: 86 80 d5 24 07 00 90 02 02 00 01 04 00 00 00 00 10: 01 d8 00 00 01 d4 00 00 00 b8 77 fe 00 b4 77 fe 20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 39 97 30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 02 00 00 40: 09 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 c2 c9 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 66 0f 05 00 00 00 00 00 01:03.0 Ethernet controller [0200]: Intel Corporation 82541PI Gigabit Ethernet Controller [8086:107c] (rev 05) Subsystem: Intel Corporation Device [8086:1376] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (63750ns min), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 20 Region 0: Memory at fe5e0000 (32-bit, non-prefetchable) [size=128K] Region 1: Memory at fe5c0000 (32-bit, non-prefetchable) [size=128K] Region 2: I/O ports at bc00 [size=64] Expansion ROM at 20000000 [disabled] [size=128K] Capabilities: [dc] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=1 PME- Capabilities: [e4] PCI-X non-bridge device Command: DPERE- ERO+ RBC=512 OST=1 Status: Dev=00:00.0 64bit- 133MHz- SCD- USC- DC=simple DMMRBC=2048 DMOST=1 DMCRS=8 RSCEM- 266MHz- 533MHz- Kernel driver in use: e1000 Kernel modules: e1000 00: 86 80 7c 10 17 00 30 02 05 00 00 02 08 20 00 00 10: 00 00 5e fe 00 00 5c fe 01 bc 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 76 13 30: 00 00 fe ff dc 00 00 00 00 00 00 00 0a 01 ff 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 e4 22 c8 e0: 00 20 00 28 07 00 02 00 00 00 40 00 00 00 00 00 f0: 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 01:05.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ [10ec:8139] (rev 10) Subsystem: ASRock Incorporation Device [1849:8139] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (8000ns min, 16000ns max) Interrupt: pin A routed to IRQ 22 Region 0: I/O ports at b800 [size=256] Region 1: Memory at fe5bfc00 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: 8139too Kernel modules: 8139too, 8139cp 00: ec 10 39 81 07 00 90 02 10 00 00 02 00 20 00 00 10: 01 b8 00 00 00 fc 5b fe 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 39 81 30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 01 20 40 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

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Re: [flashrom] [Patch] Board enable for Shuttle FN25 (SN25P).
by Luc Verhaegen Oct. 21, 2009

Oct. 21, 2009

On Sat, Oct 10, 2009 at 09:31:17PM -0300, Ulf Mehlig wrote: > Acked-by: Ulf Mehlig <ulf(a)ufpa.br> > > rebooting worked, also after re-flashing with the latest BIOS from > Shuttles Website; the ethernet address was preserved on reboot. > > Seems to be everything ok, then. > > Thanks again! Ulf > > On Wed, 2009-09-23 at 10:26 -0300, Luc Verhaegen wrote: > > On Wed, Sep 23, 2009 at 10:14:47AM -0300, Ulf Mehlig wrote: > > > Thanks for the patch, and many thanks again for helping me out > > > yesterday! > > > > > > All the best, Ulf > > > > > > > Does it work? If so, reply with: Acked-by: Ulf Mehlig <ulf(a)ufpa.br> > > so that it can be committed. > > > > Also, carldani is about to send in a patch for your bios chip, i am not > > sure how to test this, but he can explain this. > > > > Luc Verhaegen. Thanks: -> r752. Luc Verhaegen.

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[commit] r752 - trunk
by svn＠flashrom.org Oct. 21, 2009

Oct. 21, 2009

Author: libv Date: 2009-10-21 14:05:50 +0200 (Wed, 21 Oct 2009) New Revision: 752 Modified: trunk/board_enable.c Log: Board enable for Shuttle FN25 (SN25P). Shuttle SFF PC is SN25P, board FN25, AMD socket 939 with an nForce4 chipset. Config register 0x92 on the ISA bridge needs to be cleared for TBL# to be raised. No information about individual bits of this register is currently available. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Ulf Mehlig <ulf(a)ufpa.br> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-10-19 18:15:36 UTC (rev 751) +++ trunk/board_enable.c 2009-10-21 12:05:50 UTC (rev 752) @@ -400,6 +400,26 @@ } /** + * Suited for Shuttle FN25 (SN25P): AMD S939 + Nvidia CK804 (nForce4). + */ +static int board_shuttle_fn25(const char *name) +{ + struct pci_dev *dev; + + dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA Bridge. */ + if (!dev) { + fprintf(stderr, + "\nERROR: NVIDIA nForce4 ISA bridge not found.\n"); + return -1; + } + + /* one of those bits seems to be connected to TBL#, but -ENOINFO. */ + pci_write_byte(dev, 0x92, 0); + + return 0; +} + +/** * No docs, so we are just guessing that these might be individual gpio lines. */ static void nvidia_mcp_gpio_raise(struct pci_dev *dev, uint8_t offset) @@ -1086,6 +1106,7 @@ {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", ich6_gpio19_raise}, {0x10de, 0x005e, 0, 0, 0, 0, 0, 0, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", it8705f_write_enable_2e}, + {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, "Soyo", "SY-7VCA", board_soyo_sy_7vca}, {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", board_asus_a7v8x_mx}, {0x1106, 0x0314, 0x1106, 0xaa08, 0x1106, 0x3227, 0x1106, 0xAA08, NULL, NULL, "VIA", "EPIA-CN", board_via_epia_sp},

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[commit] r751 - trunk
by svn＠flashrom.org Oct. 19, 2009

Oct. 19, 2009

Author: hailfinger Date: 2009-10-19 20:15:36 +0200 (Mon, 19 Oct 2009) New Revision: 751 Modified: trunk/jedec.c Log: Remove confusing out-of-date comment. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/jedec.c =================================================================== --- trunk/jedec.c 2009-10-06 20:25:48 UTC (rev 750) +++ trunk/jedec.c 2009-10-19 18:15:36 UTC (rev 751) @@ -114,9 +114,6 @@ chip_writeb(0x55, bios + 0x2AAA); programmer_delay(10); chip_writeb(0x90, bios + 0x5555); - /* Older chips may need up to 100 us to respond. The ATMEL 29C020 - * needs 10 ms according to the data sheet. - */ programmer_delay(probe_timing_enter); /* Read product ID */

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Re: [flashrom] Winbond W25X16 successful programming
by Maurizio Cavalli Oct. 19, 2009

Oct. 19, 2009

Hi. I downloaded the latest snapshot of flashrom as you suggested, and you will find the new log in the attached file. There is yet a lot of "opcode 0x06 will be run as PREOP" lines: I deleted all of them but the first sequences. If you need them, let me known. I can rerun the program anytime, and if this little job can help you, I will do it. About the code for the PentiumM/82855GME: I'm sorry, but I have nothing to submit. Is was a my personal attempt to port linuxbios, but the activity was (too soon ?) stopped. The development tree was moved into the "old things limbo", from where it was deleted by a mistyped answer during disk maintenance. Anyway, thanks. Regards Maurizio Cavalli Sviluppo Software CONTROL SYSTEMS S.r.l. Via del Brolo, 14 26100 CREMONA (Italy) tel +39 0372 471806 fax +39 0372 471823 www.controlsystems-srl.it -----Original Message----- From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006@gmx.net] Sent: Fri 10/16/2009 12:45 PM To: Maurizio Cavalli Cc: flashrom(a)flashrom.org Subject: Re: [flashrom] Winbond W25X16 successful programming Hi Maurizio, thank you for your report. I will add your chip to the supported list. On 16.10.2009 10:03, Maurizio Cavalli wrote: > I had successfully programmed a Winbond W25X16(BVSSIG) chip with flashrom. > > Board: ROE RIVER Evaluation Board from Intel > (Reference: Intel® AtomTM Processor N270 and Mobile Intel® 945GSE Express Chipset Development Kit User's Manual - Document number: 320436-002) > BIOS: Phoenix Embedded BIOS(R) w/StrongFrame(R) Technology. > Kernel: Linux 2.6.30.2 SMP, compiled from source tree > Host system: Debian 5.0 > The log of your flashrom version had thousands of lines like this: Invalid OPCODE 0x06 due to SPI master limitation, ignoring and hoping it will be run as PREOP I have removed them from your log to make the mail smaller. It would be great if you could test erase and write with the latest flashrom from svn as well. The invalid opcode messages should have disappeared. > (I apologize we cannot use coreboot because lack of chipsets documentation from Intel. We already tried to port linuxBios onto a PentiumM/82855GME platform, but we failed in setting up the integrated graphic controller) > Oh, that is interesting. So you do already have some code, but it is not working yet? Could you please send that code to the coreboot mailing list <coreboot(a)coreboot.org> so other developers can have a look. Maybe someone has good docs for that platform. Regards, Carl-Daniel -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

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Flashrom MSI KT4V support.
by Luc Verhaegen Oct. 17, 2009

Oct. 17, 2009

Hi Sean, I have some questions about your kt4v/kt4ultra board enable: 1) I am about to move some code from many vt823x based board enables to the chipset enable. Your board enable has some "similar" code, but not quite, and it now forms the only anomaly. Can you send me the output of: dd if=/dev/mem of=/tmp/kt4v_system.rom bs=64k count=1 skip=15 so i can have a dig through the top segment of your AMI BIOS to verify this code? 2) I am about to tighten up the board enable matching table. * both the coreboot ids will disappear. * we need a second set for the kt4v. Can you send in lspci -vvnnxxx on both boards? Thanks, Luc Verhaegen.

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Re: [flashrom] Winbond W25X16 successful programming
by Carl-Daniel Hailfinger Oct. 16, 2009

Oct. 16, 2009

Hi Maurizio, thank you for your report. I will add your chip to the supported list. On 16.10.2009 10:03, Maurizio Cavalli wrote: > I had successfully programmed a Winbond W25X16(BVSSIG) chip with flashrom. > > Board: ROE RIVER Evaluation Board from Intel > (Reference: Intel® AtomTM Processor N270 and Mobile Intel® 945GSE Express Chipset Development Kit User’s Manual - Document number: 320436-002) > BIOS: Phoenix Embedded BIOS(R) w/StrongFrame(R) Technology. > Kernel: Linux 2.6.30.2 SMP, compiled from source tree > Host system: Debian 5.0 > The log of your flashrom version had thousands of lines like this: Invalid OPCODE 0x06 due to SPI master limitation, ignoring and hoping it will be run as PREOP I have removed them from your log to make the mail smaller. It would be great if you could test erase and write with the latest flashrom from svn as well. The invalid opcode messages should have disappeared. > (I apologize we cannot use coreboot because lack of chipsets documentation from Intel. We already tried to port linuxBios onto a PentiumM/82855GME platform, but we failed in setting up the integrated graphic controller) > Oh, that is interesting. So you do already have some code, but it is not working yet? Could you please send that code to the coreboot mailing list <coreboot(a)coreboot.org> so other developers can have a look. Maybe someone has good docs for that platform. Regards, Carl-Daniel -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

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