October 2009 - flashrom - mail.coreboot.org

[PATCH] Factor out lock functions (print, unlock, lock)
by Carl-Daniel Hailfinger Nov. 23, 2009

Nov. 23, 2009

Chip locking has three actions you can do with it: - Print/read the current locking status - Lock the chip - Unlock the chip. Currently, the code usually does lock printing inside the probe function, and unlocking somewhere in the erase or write function. Only very few chips reactivate the lock after write/erase. Since many chips have identical probe/write/erase functions, but totally different locking, many such functions have been duplicated needlessly. With this patch, it is possible to call the chip-specific locking functions from probe/write/erase functions and unify lots of code. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-lock_refactor/flash.h =================================================================== --- flashrom-lock_refactor/flash.h (Revision 750) +++ flashrom-lock_refactor/flash.h (Arbeitskopie) @@ -175,6 +175,12 @@ CHIP_BUSTYPE_UNKNOWN = CHIP_BUSTYPE_PARALLEL | CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI, }; +enum lockaction { + lock_print, + lock_disable, + lock_enable, +}; + /* * How many different contiguous runs of erase blocks with one size each do * we have for a given erase function? @@ -229,6 +235,7 @@ int (*write) (struct flashchip *flash, uint8_t *buf); int (*read) (struct flashchip *flash, uint8_t *buf, int start, int len); + int (*lock) (struct flashchip *flash, enum lockaction action); /* Some flash devices have an additional register space. */ chipaddr virtual_memory; @@ -551,6 +558,7 @@ int spi_send_multicommand(struct spi_command *cmds); int spi_write_enable(void); int spi_write_disable(void); +int spi_lock(struct flashchip *flash, enum lockaction action); int spi_chip_erase_60(struct flashchip *flash); int spi_chip_erase_c7(struct flashchip *flash); int spi_chip_erase_60_c7(struct flashchip *flash); Index: flashrom-lock_refactor/flashchips.c =================================================================== --- flashrom-lock_refactor/flashchips.c (Revision 750) +++ flashrom-lock_refactor/flashchips.c (Arbeitskopie) @@ -211,6 +211,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -227,6 +228,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -243,6 +245,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -259,6 +262,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -275,6 +279,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -291,6 +296,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -307,6 +313,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -323,6 +330,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -339,6 +347,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -355,6 +364,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -371,6 +381,7 @@ .erase = NULL, .write = NULL /* Incompatible Page write */, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -387,6 +398,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -403,6 +415,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -419,6 +432,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, /*The AT26DF321 has the same ID as the AT25DF321. */ @@ -436,6 +450,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, },*/ { @@ -452,6 +467,7 @@ .erase = spi_chip_erase_60_c7, .write = NULL /* Incompatible Page write */, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -468,7 +484,6 @@ .erase = erase_chip_jedec, .write = write_jedec, .read = read_memmapped, - }, { @@ -533,6 +548,7 @@ .erase = NULL, .write = NULL /* Incompatible Page write */, .read = NULL /* Incompatible read */, + .lock = spi_lock, }, { @@ -549,6 +565,7 @@ .erase = NULL, .write = NULL, .read = NULL, + .lock = spi_lock, }, { @@ -565,6 +582,7 @@ .erase = NULL, .write = NULL, .read = NULL, + .lock = spi_lock, }, { @@ -581,6 +599,7 @@ .erase = NULL, .write = NULL, .read = NULL, + .lock = spi_lock, }, { @@ -597,6 +616,7 @@ .erase = NULL, .write = NULL, .read = NULL, + .lock = spi_lock, }, { @@ -613,6 +633,7 @@ .erase = NULL, .write = NULL, .read = NULL, + .lock = spi_lock, }, { @@ -629,6 +650,7 @@ .erase = NULL, .write = NULL, .read = NULL /* Incompatible read */, + .lock = spi_lock, }, { @@ -645,6 +667,7 @@ .erase = NULL, .write = NULL, .read = NULL, + .lock = spi_lock, }, { @@ -661,6 +684,7 @@ .erase = NULL, .write = NULL, .read = NULL, + .lock = spi_lock, }, { @@ -725,6 +749,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -821,6 +846,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -837,6 +863,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -853,6 +880,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -869,6 +897,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -885,6 +914,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -901,6 +931,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -917,6 +948,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -933,6 +965,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -949,6 +982,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -965,6 +999,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -981,6 +1016,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -997,6 +1033,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1013,6 +1050,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1029,6 +1067,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1045,6 +1084,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1061,6 +1101,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1256,6 +1297,7 @@ }, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1288,6 +1330,7 @@ }, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1323,6 +1366,7 @@ }, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1358,6 +1402,7 @@ }, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1393,6 +1438,7 @@ }, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1428,6 +1474,7 @@ }, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1444,6 +1491,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1460,6 +1508,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1476,6 +1525,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1492,6 +1542,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1508,6 +1559,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1604,6 +1656,7 @@ .erase = spi_chip_erase_d8, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1620,6 +1673,7 @@ .erase = spi_chip_erase_d8, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1636,6 +1690,7 @@ .erase = spi_chip_erase_d8, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1652,6 +1707,7 @@ .erase = spi_chip_erase_d8, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1668,6 +1724,7 @@ .erase = spi_chip_erase_d8, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1684,6 +1741,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1700,6 +1758,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1716,6 +1775,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1732,6 +1792,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1748,6 +1809,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1764,6 +1826,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1876,6 +1939,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1892,6 +1956,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_1, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1908,6 +1973,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_1, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1924,6 +1990,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_1, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1940,6 +2007,7 @@ .erase = spi_chip_erase_60, .write = spi_chip_write_1, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1956,6 +2024,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_1, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -1972,6 +2041,7 @@ .erase = spi_chip_erase_60_c7, .write = spi_chip_write_1, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -2420,6 +2490,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, /* The ST M25P05 is a bit of a problem. It has the same ID as the @@ -2441,6 +2512,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_1, /* 128 */ .read = spi_chip_read, + .lock = spi_lock, }, { @@ -2457,6 +2529,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, /* The ST M25P10 has the same problem as the M25P05. */ @@ -2474,6 +2547,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_1, /* 128 */ .read = spi_chip_read, + .lock = spi_lock, }, { @@ -2490,6 +2564,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -2506,6 +2581,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -2522,6 +2598,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -2538,6 +2615,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -2554,6 +2632,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -2570,6 +2649,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -2586,6 +2666,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -2602,6 +2683,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -2954,6 +3036,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -2970,6 +3053,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -2986,6 +3070,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -3002,6 +3087,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -3018,6 +3104,7 @@ .erase = spi_chip_erase_c7, .write = spi_chip_write_256, .read = spi_chip_read, + .lock = spi_lock, }, { @@ -3258,6 +3345,7 @@ .erase = NULL, .write = NULL, .read = NULL, + .lock = NULL, }, { @@ -3274,6 +3362,7 @@ .erase = NULL, .write = NULL, .read = NULL, + .lock = NULL, }, { @@ -3290,6 +3379,7 @@ .erase = NULL, .write = NULL, .read = NULL, + .lock = NULL, }, { @@ -3306,6 +3396,7 @@ .erase = NULL, .write = NULL, .read = NULL, + .lock = NULL, }, { @@ -3322,6 +3413,7 @@ .erase = NULL, .write = NULL, .read = NULL, + .lock = NULL, }, { @@ -3338,6 +3430,7 @@ .erase = NULL, .write = NULL, .read = NULL, + .lock = NULL, }, { NULL } Index: flashrom-lock_refactor/spi.c =================================================================== --- flashrom-lock_refactor/spi.c (Revision 750) +++ flashrom-lock_refactor/spi.c (Arbeitskopie) @@ -30,8 +30,6 @@ enum spi_controller spi_controller = SPI_CONTROLLER_NONE; void *spibar = NULL; -void spi_prettyprint_status_register(struct flashchip *flash); - const struct spi_programmer spi_programmer[] = { { /* SPI_CONTROLLER_NONE */ .command = NULL, @@ -268,11 +266,6 @@ printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2); if (id1 == flash->manufacture_id && id2 == flash->model_id) { - /* Print the status register to tell the - * user about possible write protection. - */ - spi_prettyprint_status_register(flash); - return 1; } @@ -327,11 +320,6 @@ printf_debug("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2); if (id1 == flash->manufacture_id && id2 == flash->model_id) { - /* Print the status register to tell the - * user about possible write protection. - */ - spi_prettyprint_status_register(flash); - return 1; } @@ -363,10 +351,6 @@ if (id2 != flash->model_id) return 0; - /* Print the status register to tell the - * user about possible write protection. - */ - spi_prettyprint_status_register(flash); return 1; } @@ -490,6 +474,25 @@ } } +int spi_lock(struct flashchip *flash, enum lockaction action) +{ + switch (action) { + case lock_print: + spi_prettyprint_status_register(flash); + return 0; + break; + case lock_disable: + return spi_disable_blockprotect(); + break; + case lock_enable: + fprintf(stderr, "lock enable not supported.\n"); + return 1; + break; + default: /* Work around gcc. It can't see we enumerated all values. */ + return 1; + } +} + int spi_chip_erase_60(struct flashchip *flash) { int result; Index: flashrom-lock_refactor/flashrom.c =================================================================== --- flashrom-lock_refactor/flashrom.c (Revision 750) +++ flashrom-lock_refactor/flashrom.c (Arbeitskopie) @@ -448,6 +448,9 @@ printf("Found chip \"%s %s\" (%d KB, %s) at physical address 0x%lx.\n", flash->vendor, flash->name, flash->total_size, flashbuses_to_text(flash->bustype), base); + /* Print the locking status. */ + if (flash->lock) + flash->lock(flash, lock_print); return flash; } -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

3 7

[PATCH] Totally generic SPI chip match
by Carl-Daniel Hailfinger Nov. 19, 2009

Nov. 19, 2009

If a chip is not on the RDID generic vendor list nor on the REMS specific ID list, flashrom will claim that no chip is there. Handle these cases gracefully. flashrom will ignore generic matches if a specific chip was found, so this will have no impact on supported chips, but help a lot for a first quick analysis by the user or developer. The only drawback is that unknown chips may be recognized multiple times until they are added to flashchips.[ch]. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_totally_generic_probe/flashchips.c =================================================================== --- flashrom-spi_totally_generic_probe/flashchips.c (Revision 664) +++ flashrom-spi_totally_generic_probe/flashchips.c (Arbeitskopie) @@ -3167,5 +3167,32 @@ .read = NULL, }, + { + .vendor = "Generic", + .name = "unknown SPI chip (RDID)", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = GENERIC_MANUF_ID, + .model_id = GENERIC_DEVICE_ID, + .total_size = 0, + .page_size = 256, + .tested = TEST_BAD_PREW, + .probe = probe_spi_rdid, + .erase = NULL, + .write = NULL, + }, + { + .vendor = "Generic", + .name = "unknown SPI chip (REMS)", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = GENERIC_MANUF_ID, + .model_id = GENERIC_DEVICE_ID, + .total_size = 0, + .page_size = 256, + .tested = TEST_BAD_PREW, + .probe = probe_spi_rems, + .erase = NULL, + .write = NULL, + }, + { NULL } }; Index: flashrom-spi_totally_generic_probe/flashchips.h =================================================================== --- flashrom-spi_totally_generic_probe/flashchips.h (Revision 664) +++ flashrom-spi_totally_generic_probe/flashchips.h (Arbeitskopie) @@ -34,6 +34,7 @@ * SPI parts have 16-bit device IDs if they support RDID. */ +#define GENERIC_MANUF_ID 0xffff /* Check if there is a vendor ID */ #define GENERIC_DEVICE_ID 0xffff /* Only match the vendor ID */ #define ALLIANCE_ID 0x52 /* Alliance Semiconductor */ Index: flashrom-spi_totally_generic_probe/spi.c =================================================================== --- flashrom-spi_totally_generic_probe/spi.c (Revision 664) +++ flashrom-spi_totally_generic_probe/spi.c (Arbeitskopie) @@ -274,6 +274,11 @@ GENERIC_DEVICE_ID == flash->model_id) return 1; + /* Test if there is any vendor ID. */ + if (GENERIC_MANUF_ID == flash->manufacture_id && + id1 != 0xff) + return 1; + return 0; } @@ -329,6 +334,11 @@ GENERIC_DEVICE_ID == flash->model_id) return 1; + /* Test if there is any vendor ID. */ + if (GENERIC_MANUF_ID == flash->manufacture_id && + id1 != 0xff) + return 1; + return 0; } -- http://www.hailfinger.org/

2 4

[PATCH] Clean up main loop
by Carl-Daniel Hailfinger Nov. 17, 2009

Nov. 17, 2009

To prepare for libflashrom I wanted to make the main loop more readable and more correct and factor out stuff which can be useful in libflashrom. - Factor out printing of supported devices to print.c. - Adjust name of wiki printing function to fit the pattern. - Abort if the user specified --verify and --noverify at the same time. - Check for extra parameters which don't fit commandline syntax. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-mainloop_cleanup/flash.h =================================================================== --- flashrom-mainloop_cleanup/flash.h (Revision 755) +++ flashrom-mainloop_cleanup/flash.h (Arbeitskopie) @@ -338,11 +338,9 @@ /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); -void print_supported_chips(void); -void print_supported_chipsets(void); -void print_supported_boards(void); +void print_supported(void); void print_supported_pcidevs(struct pcidev_status *devs); -void print_wiki_tables(void); +void print_supported_wiki(void); /* board_enable.c */ void w836xx_ext_enter(uint16_t port); Index: flashrom-mainloop_cleanup/flashrom.c =================================================================== --- flashrom-mainloop_cleanup/flashrom.c (Revision 755) +++ flashrom-mainloop_cleanup/flashrom.c (Arbeitskopie) @@ -801,14 +801,25 @@ write_it = 1; break; case 'v': + //FIXME: gracefully handle superfluous -v if (++operation_specified > 1) { fprintf(stderr, "More than one operation " "specified. Aborting.\n"); exit(1); } + if (dont_verify_it) { + fprintf(stderr, "--verify and --noverify are" + "mutually exclusive. Aborting.\n"); + exit(1); + } verify_it = 1; break; case 'n': + if (verify_it) { + fprintf(stderr, "--verify and --noverify are" + "mutually exclusive. Aborting.\n"); + exit(1); + } dont_verify_it = 1; break; case 'c': @@ -896,29 +907,13 @@ } if (list_supported) { - print_supported_chips(); - print_supported_chipsets(); - print_supported_boards(); - printf("\nSupported PCI devices flashrom can use " - "as programmer:\n\n"); -#if NIC3COM_SUPPORT == 1 - print_supported_pcidevs(nics_3com); -#endif -#if GFXNVIDIA_SUPPORT == 1 - print_supported_pcidevs(gfx_nvidia); -#endif -#if DRKAISER_SUPPORT == 1 - print_supported_pcidevs(drkaiser_pcidev); -#endif -#if SATASII_SUPPORT == 1 - print_supported_pcidevs(satas_sii); -#endif + print_supported(); exit(0); } #if PRINT_WIKI_SUPPORT == 1 if (list_supported_wiki) { - print_wiki_tables(); + print_supported_wiki(); exit(0); } #endif @@ -930,6 +925,11 @@ if (optind < argc) filename = argv[optind++]; + + if (optind < argc) { + printf("Error: Extra parameter found.\n"); + usage(argv[0]); + } if (programmer_init()) { fprintf(stderr, "Error: Programmer initialization failed.\n"); @@ -1146,7 +1146,7 @@ if (write_it) programmer_delay(1000*1000); ret = verify_flash(flash, buf); - /* If we tried to write, and now we don't properly verify, we + /* If we tried to write, and verification now fails, we * might have an emergency situation. */ if (ret && write_it) Index: flashrom-mainloop_cleanup/print_wiki.c =================================================================== --- flashrom-mainloop_cleanup/print_wiki.c (Revision 755) +++ flashrom-mainloop_cleanup/print_wiki.c (Arbeitskopie) @@ -535,7 +535,7 @@ } } -void print_wiki_tables(void) +void print_supported_wiki(void) { time_t t = time(NULL); Index: flashrom-mainloop_cleanup/print.c =================================================================== --- flashrom-mainloop_cleanup/print.c (Revision 755) +++ flashrom-mainloop_cleanup/print.c (Arbeitskopie) @@ -222,7 +222,28 @@ "Laptops which have been verified to NOT work yet"); } +void print_supported(void) +{ + print_supported_chips(); + print_supported_chipsets(); + print_supported_boards(); + printf("\nSupported PCI devices flashrom can use " + "as programmer:\n\n"); +#if NIC3COM_SUPPORT == 1 + print_supported_pcidevs(nics_3com); +#endif +#if GFXNVIDIA_SUPPORT == 1 + print_supported_pcidevs(gfx_nvidia); +#endif +#if DRKAISER_SUPPORT == 1 + print_supported_pcidevs(drkaiser_pcidev); +#endif +#if SATASII_SUPPORT == 1 + print_supported_pcidevs(satas_sii); +#endif +} + /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info boards_ok[] = { /* Verified working boards that don't need write-enables. */ -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

2 3

Fix feature detection when fdti requires libusb for linking
by Joerg Mayer Nov. 16, 2009

Nov. 16, 2009

see attached patch. patch is too small to be copyrightable... ciao Joerg -- Joerg Mayer <jmayer(a)loplof.de> We are stuck with technology when what we really want is just stuff that works. Some say that should read Microsoft instead of technology.

3 5

Re: [flashrom] Trial of ARIMA:HDAMA Motherboard
by Spangler, Mike T Oct. 31, 2009

Oct. 31, 2009

Carl-Daniel - I can tell everyone's very busy. Just wanted to make sure that I haven't been forgotten. The system is still up and ready for testing. Mike -----Original Message----- From: Spangler, Mike T Sent: Friday, September 18, 2009 4:48 PM To: 'Carl-Daniel Hailfinger' Cc: flashrom(a)flashrom.org Subject: RE: [flashrom] Trial of ARIMA:HDAMA Motherboard Carl-Daniel - Yes, we are stuck with factory bios for now and a lot of it's due to our reliance on HP hardware and their maintenance requirements. We do have legacy Linux Networx gear that I could run coreboot on with gPXE. I'll have to investigate that solution at a later date. Also, the good thing about my method of reading the bios and flashing what I read is that it moves my bios settings with the flash. If you pull the flash off of the factory distribution, you have to redo the bios settings for every node one at a time. Below is the lspci output per your request: 0000:00:18.0 Class 0600: 1022:1100 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Capabilities: [80] #08 [2101] Capabilities: [a0] #08 [2101] Capabilities: [c0] #08 [2101] 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 01 01 05 00 04 04 01 00 01 01 01 00 01 01 01 00 50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 60: 10 00 01 00 e4 00 00 00 00 c8 00 0f 74 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 a0 01 21 20 00 11 11 22 04 75 80 02 00 00 00 90: 56 04 51 02 00 01 04 00 07 00 00 00 00 00 00 00 a0: 08 c0 01 21 20 00 11 11 22 05 75 80 02 00 00 00 b0: 13 56 13 04 00 00 00 00 03 00 00 00 00 00 00 00 c0: 08 00 01 21 d0 00 11 77 22 00 75 80 02 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:00:18.1 Class 0600: 1022:1101 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 ff 00 03 00 00 01 01 00 ff 01 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 03 00 f8 00 00 1f fb 00 c0: 03 10 00 00 00 20 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 03 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:00:18.2 Class 0600: 1022:1102 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 00 00 00 01 10 00 00 01 20 00 00 01 30 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 ce e0 0f 00 ce e0 0f 00 ce e0 0f 00 ce e0 0f 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 44 00 00 00 00 00 00 00 35 33 72 13 20 0a 10 00 90: 00 8c 33 08 08 0b 5b 0e 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: fd 2f 13 bf d0 00 00 00 d7 ff 5e 81 d0 87 9f 90 c0: 00 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 05 12 57 44 8d 44 e0 76 fe 8e 08 60 6d c8 54 69 e0: 14 44 63 6b e5 42 f3 db 33 8e 62 1c f4 4c b9 3a f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:00:18.3 Class 0600: 1022:1103 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: ff 3b 00 00 40 00 c0 02 00 00 00 00 00 00 00 00 50: 08 86 bb c0 60 00 00 00 16 16 16 00 40 d7 be 22 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 11 01 02 51 11 80 00 50 00 38 00 08 1b 22 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 03 00 00 00 7a 00 00 00 00 dd ef 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 3c 00 00 80 db e5 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 07 07 e2 04 00 00 00 00 00 25 00 00 e0: 00 00 00 00 20 0c 57 00 1b 01 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:00:19.0 Class 0600: 1022:1100 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Capabilities: [80] #08 [2101] Capabilities: [a0] #08 [2101] Capabilities: [c0] #08 [2101] 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 04 04 01 00 01 01 05 00 01 01 01 00 01 01 01 00 50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 60: 11 00 01 00 e4 00 00 00 00 c8 00 0f 7c 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 a0 01 21 d0 00 11 77 22 00 75 80 02 00 00 00 90: 56 04 51 02 00 00 00 00 00 00 00 00 00 00 00 00 a0: 08 c0 01 21 20 00 11 11 22 05 75 80 02 00 00 00 b0: 13 56 13 04 00 00 00 00 03 00 00 00 00 00 00 00 c0: 08 00 01 21 d0 00 11 77 22 00 75 80 02 00 00 00 d0: 0c 34 01 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:00:19.1 Class 0600: 1022:1101 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 ff 00 03 00 00 01 01 00 ff 01 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 03 00 f8 00 00 1f fb 00 c0: 03 10 00 00 00 20 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 03 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:00:19.2 Class 0600: 1022:1102 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 00 00 00 01 10 00 00 01 20 00 00 01 30 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 ce e0 0f 00 ce e0 0f 00 ce e0 0f 00 ce e0 0f 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 44 00 00 00 00 00 00 00 35 33 72 13 20 0a 10 00 90: 00 8c 33 08 08 0b 5b 0e 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 6f 68 15 bf d0 00 00 00 50 3e 50 02 c0 a1 42 d4 c0: 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 58 6f ff 13 b4 43 27 ba b5 7f 19 9f 74 7f eb bb e0: f9 f6 cf bb 95 cd f3 bc 7d dc 8d af fd 99 ce a3 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:00:19.3 Class 0600: 1022:1103 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: ff 3b 00 00 40 00 c0 02 00 00 00 00 00 00 00 00 50: 88 71 e6 db 21 00 00 00 16 16 16 00 c0 d3 be 22 60: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 11 01 02 51 11 80 00 50 00 38 00 08 1b 22 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 03 00 00 00 7a 00 00 00 00 dd ef 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 36 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 07 07 e2 04 00 00 00 00 00 25 00 00 e0: 00 00 00 00 20 10 55 00 1b 01 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:01.0 Class 0604: 1022:7450 (rev 12) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 Bus: primary=01, secondary=02, subordinate=02, sec-latency=64 I/O behind bridge: 00002000-00001fff Memory behind bridge: fb000000-fb0fffff Prefetchable memory behind bridge: 00000000fb100000-00000000fb000000 BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- Capabilities: [a0] Capabilities: [b8] #08 [8000] Capabilities: [c0] #08 [0041] 00: 22 10 50 74 57 01 30 02 12 00 04 06 00 40 81 00 10: 00 00 00 00 00 00 00 00 01 02 02 40 21 11 20 22 20: 00 fb 00 fb 11 fb 01 fb 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 ff 00 03 00 40: 07 00 1f 00 00 00 00 00 02 0c 00 00 01 2c 00 00 50: 00 00 03 00 00 00 05 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 07 b8 03 00 08 01 03 00 0e 00 0e 00 02 00 02 00 b0: 00 00 00 00 00 00 00 00 08 c0 00 80 00 00 00 03 c0: 08 00 41 00 22 00 11 11 22 00 00 00 22 04 35 00 d0: 02 00 35 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 04 04 10 00 04 04 0d 00 04 04 16 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:01.1 Class 0800: 1022:7451 (rev 01) (prog-if 10) Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Region 0: Memory at fb100000 (64-bit, non-prefetchable) 00: 22 10 51 74 02 00 00 02 01 10 00 08 00 00 00 00 10: 04 00 10 fb 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 03 00 00 00 04 00 10 fb 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:02.0 Class 0604: 1022:7450 (rev 12) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 Bus: primary=01, secondary=03, subordinate=03, sec-latency=64 I/O behind bridge: 00002000-00001fff Memory behind bridge: fb100000-fb0fffff Prefetchable memory behind bridge: 00000000fa000000-00000000faf00000 BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- Capabilities: [a0] Capabilities: [b8] #08 [8000] 00: 22 10 50 74 57 01 30 02 12 00 04 06 00 40 81 00 10: 00 00 00 00 00 00 00 00 01 03 03 40 21 11 20 a3 20: 10 fb 00 fb 01 fa f1 fa 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 ff 00 03 00 40: 05 00 1f 00 00 00 00 00 00 00 00 00 01 2c 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 07 b8 c3 00 10 01 03 00 0e 00 0e 00 02 00 02 00 b0: 00 00 00 00 00 00 00 00 08 00 00 80 00 00 00 04 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:02.1 Class 0800: 1022:7451 (rev 01) (prog-if 10) Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Region 0: Memory at fb101000 (64-bit, non-prefetchable) 00: 22 10 51 74 02 00 00 02 01 10 00 08 00 00 00 00 10: 04 10 10 fb 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 03 00 00 00 04 10 10 fb 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:03.0 Class 0604: 1022:7460 (rev 07) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 Bus: primary=01, secondary=04, subordinate=04, sec-latency=64 I/O behind bridge: 00001000-00001fff Memory behind bridge: f8000000-f90fffff Prefetchable memory behind bridge: fb100000-fb0fffff Expansion ROM at 00001000 [disabled] [size=4K] BridgeCtl: Parity+ SERR+ NoISA+ VGA+ MAbort- >Reset- FastB2B- Capabilities: [c0] #08 [0083] Capabilities: [f0] #08 [8000] 00: 22 10 60 74 47 01 30 02 07 00 04 06 00 40 01 00 10: 00 00 00 00 00 00 00 00 01 04 04 40 10 10 00 22 20: 00 f8 00 f9 10 fb 00 fb 00 00 00 00 00 00 00 00 30: 00 00 00 00 c0 00 00 00 00 00 00 00 ff 00 0f 08 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 04 06 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 08 f0 83 00 22 00 00 00 d0 00 00 00 22 00 01 00 d0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 08 00 0f 00 08 00 11 00 0f 00 17 00 00 00 00 00 f0: 08 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:04.0 Class 0601: 1022:7468 (rev 05) Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 00: 22 10 68 74 0f 00 20 02 05 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 30 07 c0 01 00 00 02 9f fd 00 01 00 00 00 c0 50: 00 00 00 00 85 01 00 00 44 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 de 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:04.1 Class 0101: 1022:7469 (rev 03) (prog-if 8a [Master SecP PriP]) Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 Region 4: I/O ports at 0f00 [size=16] 00: 22 10 69 74 05 00 00 02 03 8a 01 01 00 40 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 00 40: 43 f0 0f 00 00 00 00 00 5e 5e 5e 20 2a 00 ff 20 50: 03 03 03 c6 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:04.2 Class 0c05: 1022:746a (rev 02) Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin D routed to IRQ 0 Region 0: I/O ports at 2400 00: 22 10 6a 74 01 00 00 02 02 00 05 0c 00 40 00 00 10: 01 24 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 40: 02 00 05 0c 00 00 00 00 06 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:04.3 Class 0000: 1022:746b (rev 05) Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 6b 74 00 00 80 02 05 00 00 00 00 40 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 d1 00 04 00 00 00 00 20 14 10 00 00 00 00 00 50: 00 80 00 00 0f 00 00 00 01 20 00 00 00 00 00 00 60: 00 00 00 00 13 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 54 ac 76 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:02:03.0 Class 0200: 14e4:16a6 (rev 02) Subsystem: 14e4:000c Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 (16000ns min), cache line size 10 Interrupt: pin A routed to IRQ 19 Region 0: Memory at fb000000 (64-bit, non-prefetchable) [size=1026M] Expansion ROM at 00010000 [disabled] Capabilities: [40] PCI-X non-bridge device. Command: DPERE- ERO- RBC=0 OST=0 Status: Bus=255 Dev=31 Func=1 64bit+ 133MHz+ SCD- USC-, DC=simple, DMMRBC=2, DMOST=0, DMCRS=1, RSCEM- Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=1 PME- Capabilities: [50] Vital Product Data Capabilities: [58] Message Signalled Interrupts: 64bit+ Queue=0/3 Enable- Address: fcfb626b00cc0528 Data: 0109 00: e4 14 a6 16 46 01 b0 02 02 00 00 02 10 40 00 00 10: 04 00 00 fb 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 e4 14 0c 00 30: 00 00 20 40 40 00 00 00 00 00 00 00 00 01 40 00 40: 07 48 00 00 f9 ff 43 04 01 50 02 c0 00 20 00 64 50: 03 58 00 00 0a 80 a0 22 05 00 86 00 28 05 cc 00 60: 6b 62 fb fc 09 01 00 00 98 02 02 10 00 00 3f 76 70: fe 10 00 00 df 00 00 80 4c 5b 03 00 00 00 00 00 80: 00 00 00 00 9f 13 88 f6 34 00 13 04 82 10 08 00 90: 09 92 00 01 83 01 00 00 00 00 00 00 83 01 00 00 a0: 00 00 00 00 bb 00 00 00 00 00 00 00 cd 01 00 00 b0: 00 00 00 00 00 00 00 f6 00 00 00 00 00 00 00 f6 c0: 00 00 00 00 00 00 00 f6 00 00 00 00 00 00 00 f6 d0: 00 00 00 00 00 00 00 f6 00 00 00 00 00 00 00 f6 e0: 00 00 00 00 00 00 00 f6 00 00 00 00 00 00 00 f6 f0: 00 00 00 00 00 00 00 f6 00 00 00 00 00 00 00 f6 0000:02:04.0 Class 0200: 14e4:16a6 (rev 02) Subsystem: 14e4:000c Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 (16000ns min), cache line size 10 Interrupt: pin A routed to IRQ 19 Region 0: Memory at fb010000 (64-bit, non-prefetchable) [size=106M] Expansion ROM at 00010000 [disabled] Capabilities: [40] PCI-X non-bridge device. Command: DPERE- ERO+ RBC=0 OST=0 Status: Bus=255 Dev=31 Func=1 64bit+ 133MHz+ SCD- USC-, DC=simple, DMMRBC=2, DMOST=0, DMCRS=1, RSCEM- Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=1 PME- Capabilities: [50] Vital Product Data Capabilities: [58] Message Signalled Interrupts: 64bit+ Queue=0/3 Enable- Address: fcfd56ebfbf37f4c Data: eff5 00: e4 14 a6 16 46 01 b0 02 02 00 00 02 10 40 00 00 10: 04 00 01 fb 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 e4 14 0c 00 30: 00 00 ad 06 40 00 00 00 00 00 00 00 00 01 40 00 40: 07 48 02 00 f9 ff 43 04 01 50 02 c0 00 20 00 64 50: 03 58 b8 00 f7 e5 fe 79 05 00 86 00 4c 7f f3 fb 60: eb 56 fd fc f5 ef 00 00 9a 02 02 10 00 00 3f 76 70: be 12 00 00 df 00 00 00 50 00 00 00 00 00 00 00 80: 03 58 b8 00 5f bf f5 eb 34 00 00 00 fe 10 08 00 90: 01 02 00 01 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:03:01.0 Class 0280: 14c1:8043 (rev 04) Subsystem: 14c1:8043 Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR+ Interrupt: pin A routed to IRQ 17 Region 0: Memory at fa000000 (64-bit, prefetchable) Capabilities: [44] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [54] PCI-X non-bridge device. Command: DPERE- ERO- RBC=0 OST=0 Status: Bus=3 Dev=1 Func=0 64bit+ 133MHz+ SCD- USC-, DC=simple, DMMRBC=3, DMOST=0, DMCRS=2, RSCEM-00: c1 14 43 80 42 00 30 80 04 00 80 02 10 40 00 00 10: 0c 00 00 fa 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 c1 14 43 80 30: 00 00 00 00 44 00 00 00 00 00 00 00 00 01 00 00 40: 00 00 00 55 05 54 80 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 07 00 00 00 08 03 63 08 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 ac 00 60 dd 48 b1 80 0000:04:00.0 Class 0c03: 1022:7464 (rev 0b) (prog-if 10) Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin D routed to IRQ 0 Region 0: Memory at f9000000 (32-bit, non-prefetchable) 00: 22 10 64 74 02 01 80 02 0b 10 03 0c 00 40 80 00 10: 00 00 00 f9 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 50 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:04:00.1 Class 0c03: 1022:7464 (rev 0b) (prog-if 10) Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin D routed to IRQ 0 Region 0: Memory at f9001000 (32-bit, non-prefetchable) 00: 22 10 64 74 02 01 80 02 0b 10 03 0c 00 40 00 00 10: 00 10 00 f9 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 50 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:04:00.2 Class 0c03: 1022:7463 (rev 02) (prog-if 20) Subsystem: 1022:7463 Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin D routed to IRQ 0 Region 0: Memory at f9003000 (32-bit, non-prefetchable) Region 1: Memory at f9004000 (32-bit, non-prefetchable) [size=32] Capabilities: [80] #0a [4000] Capabilities: [88] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=100mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 22 10 63 74 02 00 10 02 02 20 03 0c 00 40 00 00 10: 00 30 00 f9 00 40 00 f9 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 63 74 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 04 00 00 40: 01 00 00 00 00 00 00 c0 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 01 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 22 10 63 74 01 00 00 00 40 30 00 01 00 00 00 00 80: 0a 88 00 40 00 00 00 00 01 00 82 fe 00 00 00 00 90: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:04:06.0 Class 0300: 1002:4752 (rev 27) Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin A routed to IRQ 0 Region 0: Memory at f8000000 (32-bit, non-prefetchable) Region 1: I/O ports at 1000 [size=256] Region 2: Memory at f9002000 (32-bit, non-prefetchable) [size=4K] Capabilities: [5c] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 02 10 52 47 83 00 90 02 27 00 00 03 10 40 00 00 10: 00 00 00 f8 01 10 00 00 00 20 00 f9 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 5c 00 00 00 00 00 00 00 00 01 08 00 40: 0c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 02 5c 10 00 01 00 00 ff 00 00 00 00 01 00 02 06 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -----Original Message----- From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006@gmx.net] Sent: Friday, September 18, 2009 3:18 PM To: Spangler, Mike T Cc: flashrom(a)flashrom.org Subject: Re: [flashrom] Trial of ARIMA:HDAMA Motherboard Hi Mike, On 18.09.2009 18:55, Spangler, Mike T wrote: > I've corrected my email and am now sending to the group. > Thanks. >> Of course I'd prefer it if you tried to flash coreboot (new name of >> LinuxBIOS) to these boards, but that's your choice. Anyway, you said you >> have the factory BIOS around somewhere. Is it the one at >> http://flextronics.com/arima/Server/Download/Download/HDAMA189.zip ? >> > > I can't use flash coreboot (LinuxBIOS) because our cluster management tools require pxeboot. We've transitioned away from it. > That's unfortunate. Did you know that coreboot+SeaBIOS works fine with gPXE? We coreboot/flashrom developers are always interested in helping people update coreboot to the latest and greatest. So if you need PXE booting, there's no need to move back to the factory BIOS, a simple coreboot update should suffice. > So, the bios zip file above is correct, but I'm not using it. It will not work for flashing a chip with LinuxBios. The way I do this is to do a "flashrom -r" on a system with factory bios and then take that newly created flashrom file and do a "flashrom -w" with it on a board with LinuxBios. That's one option. The other option would be to extract the BIOS from the .ROM file. That looks reasonably easy. No guarantees, though. dd if=something.ROM of=bios.bin bs=1k count=512 > This is the method we used with the old bios_copy software from Linux Networx, but that was extremely unreliable. > flashrom strives to be the most reliable flashing tool out there. The current version has builtin verification for every step it does. >> Hmm ok. I think we have enough docs to iterate through all possible >> board enables. How many of these boards do you have (in case we trash >> the ROM of one of them)? >> > > The ROM is removeable, so we only potentially trash a PLCC chip. I have a half dozen or so spares. > Great. And with hotplugging/hotflashing it should be possible to reflash a trashed chip in another board. Can you supply the output of "lspci -nnvvvxxx" as root? That will allow me to dig further. I'd like to limit the search to a reasonable subset of options. Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

[commit] r755 - trunk
by svn＠flashrom.org Oct. 30, 2009

Oct. 30, 2009

Author: hailfinger Date: 2009-10-31 02:53:09 +0100 (Sat, 31 Oct 2009) New Revision: 755 Modified: trunk/chipset_enable.c trunk/flash.h trunk/flashrom.c Log: Add infrastructure to check and report to the user the maximum supported decode size for chipsets and tested mainboards. The rationale is to warn users when they, for example, try to flash a 512KB parallel flash chip but their chipset only supports 256KB, or they try to flash 512KB and the chipset _does_ theoretically support 512KB but their special board doesn't wire all address lines and thus supports only 256 KB ROM chips at maximum. This has cost Uwe hours of debugging on some board already, until he figured out what was going on. We should try warn our users where possible about this. The chipset and the chip may have more than one bus in common (e.g. SB600 and Pm49* can both speak LPC+FWH) and on SB600/SB7x0/SB8x0 there are different limits for LPC and FWH. The only way to tell the user about the exact circumstances is to spew error messages per bus. The code will issue a warning during probe (which does fail for some chips if the size is too big) and abort before the first real read/write/erase action. If no action is specified, the warning is printed anyway. That way, a user can find out why probe might not have worked, and will be stopped before he/she gets incorrect results. Add a bitcount function to the infrastructure. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-10-30 21:12:39 UTC (rev 754) +++ trunk/chipset_enable.c 2009-10-31 01:53:09 UTC (rev 755) @@ -42,6 +42,17 @@ enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI; +/** + * Programmers supporting multiple buses can have differing size limits on + * each bus. Store the limits for each bus in a common struct. + */ +struct decode_sizes max_rom_decode = { + .parallel = 0xffffffff, + .lpc = 0xffffffff, + .fwh = 0xffffffff, + .spi = 0xffffffff +}; + extern int ichspi_lock; static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-10-30 21:12:39 UTC (rev 754) +++ trunk/flash.h 2009-10-31 01:53:09 UTC (rev 755) @@ -352,9 +352,17 @@ void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask); int board_flash_enable(const char *vendor, const char *part); +struct decode_sizes { + uint32_t parallel; + uint32_t lpc; + uint32_t fwh; + uint32_t spi; +}; + /* chipset_enable.c */ extern enum chipbustype buses_supported; int chipset_flash_enable(void); +extern struct decode_sizes max_rom_decode; extern unsigned long flashbase; Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-10-30 21:12:39 UTC (rev 754) +++ trunk/flashrom.c 2009-10-31 01:53:09 UTC (rev 755) @@ -299,6 +299,15 @@ return (a > b) ? a : b; } +int bitcount(unsigned long a) +{ + int i = 0; + for (; a != 0; a >>= 1) + if (a & 1) + i++; + return i; +} + char *strcat_realloc(char *dest, const char *src) { dest = realloc(dest, strlen(dest) + strlen(src) + 1); @@ -398,10 +407,60 @@ return ret; } +int check_max_decode(enum chipbustype buses, uint32_t size) +{ + int limitexceeded = 0; + if ((buses & CHIP_BUSTYPE_PARALLEL) && + (max_rom_decode.parallel < size)) { + limitexceeded++; + printf_debug("Chip size %u kB is bigger than supported " + "size %u kB of chipset/board/programmer " + "for %s interface, " + "probe/read/erase/write may fail. ", size / 1024, + max_rom_decode.parallel / 1024, "Parallel"); + } + if ((buses & CHIP_BUSTYPE_LPC) && (max_rom_decode.lpc < size)) { + limitexceeded++; + printf_debug("Chip size %u kB is bigger than supported " + "size %u kB of chipset/board/programmer " + "for %s interface, " + "probe/read/erase/write may fail. ", size / 1024, + max_rom_decode.lpc / 1024, "LPC"); + } + if ((buses & CHIP_BUSTYPE_FWH) && (max_rom_decode.fwh < size)) { + limitexceeded++; + printf_debug("Chip size %u kB is bigger than supported " + "size %u kB of chipset/board/programmer " + "for %s interface, " + "probe/read/erase/write may fail. ", size / 1024, + max_rom_decode.fwh / 1024, "FWH"); + } + if ((buses & CHIP_BUSTYPE_SPI) && (max_rom_decode.spi < size)) { + limitexceeded++; + printf_debug("Chip size %u kB is bigger than supported " + "size %u kB of chipset/board/programmer " + "for %s interface, " + "probe/read/erase/write may fail. ", size / 1024, + max_rom_decode.spi / 1024, "SPI"); + } + if (!limitexceeded) + return 0; + /* Sometimes chip and programmer have more than one bus in common, + * and the limit is not exceeded on all buses. Tell the user. + */ + if (bitcount(buses) > limitexceeded) + printf_debug("There is at least one common chip/programmer " + "interface which can support a chip of this size. " + "You can try --force at your own risk.\n"); + return 1; +} + struct flashchip *probe_flash(struct flashchip *first_flash, int force) { struct flashchip *flash; - unsigned long base = 0, size; + unsigned long base = 0; + uint32_t size; + enum chipbustype buses_common; char *tmp; for (flash = first_flash; flash && flash->name; flash++) { @@ -413,7 +472,8 @@ printf_debug("failed! flashrom has no probe function for this flash chip.\n"); continue; } - if (!(buses_supported & flash->bustype)) { + buses_common = buses_supported & flash->bustype; + if (!buses_common) { tmp = flashbuses_to_text(buses_supported); printf_debug("skipped. Host bus type %s ", tmp); free(tmp); @@ -424,6 +484,7 @@ } size = flash->total_size * 1024; + check_max_decode(buses_common, size); base = flashbase ? flashbase : (0xffffffff - size + 1); flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); @@ -956,6 +1017,15 @@ "mainboard you tested. Thanks for your help!\n===\n"); } + size = flash->total_size * 1024; + if (check_max_decode((buses_supported & flash->bustype), size) && + (!force)) { + fprintf(stderr, "Chip is too big for this programmer " + "(-V gives details). Use --force to override.\n"); + programmer_shutdown(); + return 1; + } + if (!(read_it | write_it | verify_it | erase_it)) { printf("No operations were specified.\n"); // FIXME: flash writes stay enabled! @@ -974,7 +1044,6 @@ if (write_it && !dont_verify_it) verify_it = 1; - size = flash->total_size * 1024; buf = (uint8_t *) calloc(size, sizeof(char)); if (erase_it) {

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[commit] r754 - trunk
by svn＠flashrom.org Oct. 30, 2009

Oct. 30, 2009

Author: hailfinger Date: 2009-10-30 22:12:39 +0100 (Fri, 30 Oct 2009) New Revision: 754 Modified: trunk/pcidev.c Log: Adjust a help text for external PCI programmers to the new parameter scheme. Pointed out by Maciej Pijanka. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/pcidev.c =================================================================== --- trunk/pcidev.c 2009-10-22 15:07:30 UTC (rev 753) +++ trunk/pcidev.c 2009-10-30 21:12:39 UTC (rev 754) @@ -100,7 +100,7 @@ exit(1); } else if (found > 1) { fprintf(stderr, "Error: Multiple supported PCI devices found. " - "Use 'flashrom -p xxxx=bb:dd.f' \n" + "Use 'flashrom -p xxxx:bb:dd.f' \n" "to explicitly select the card with the given BDF " "(PCI bus, device, function).\n"); exit(1);

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Need help to flash bios HP Omnibook 4150B
by guillaumeg Oct. 29, 2009

Oct. 29, 2009

Good evening i installed fedora 11 in my laptop Intel pentium III coppermine i'd like to flash the bios using flashrom the objectif is ( i hope) to fix a display problem - stripes on the screen, especially when i move the mouse. i tried to fix the problem with Xorg.conf and system-config-display withoot any success. Some people drived me in the french fedora forum. They invite my to join the flashrom IRC chat. for your information here a report when i launch flashrom with a terminal. flashrom v0.9.1-r710 No coreboot table found. Found chipset "Intel PIIX4/4E/4M", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically. i will stay connect on #flashrom as much as I can. Thank you for your help hope to hear from you soon regards guillaume de bamako

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[PATCH] Error out when chipset/board doesn't decode full ROM
by Uwe Hermann Oct. 29, 2009

Oct. 29, 2009

See patch. I'm thankful for better suggestions to track which chipsets and especially boards can decode how much. For boards we need to autodetect them (not possible for all boards unfortunately). For those with board-enables we could reuse that table and enhance/add board-enables, whether that's a good idea is another issue. For boards that cannot be autodetected we should at least have a table of the max. supported ROM chip size, which can be printed in "flashrom -L" and in the wiki. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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Board: Acorp 6A815EPD autodetectable.
by Luc Verhaegen Oct. 27, 2009

Oct. 27, 2009

3 4