Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43500 ) Change subject: ichspi.c: Make ich_set_bbar() parameteric on ich_generation ...................................................................... ichspi.c: Make ich_set_bbar() parameteric on ich_generation Work towards dropping ich_generation global usage and make the ich_set_bbar() function pure. Change-Id: I6da6dccb413cbafa2fbaca213574f22c7a258139 Signed-off-by: Edward O'Callaghan <quasisec@google.com> --- M ichspi.c 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/00/43500/1 diff --git a/ichspi.c b/ichspi.c index 82bbf9f..306b778 100644 --- a/ichspi.c +++ b/ichspi.c @@ -714,10 +714,10 @@ * Try to set BBAR (BIOS Base Address Register), but read back the value in case * it didn't stick. */ -static void ich_set_bbar(uint32_t min_addr) +static void ich_set_bbar(uint32_t min_addr, enum ich_chipset ich_gen) { int bbar_off; - switch (ich_generation) { + switch (ich_gen) { case CHIPSET_ICH7: case CHIPSET_TUNNEL_CREEK: case CHIPSET_CENTERTON: @@ -1811,7 +1811,7 @@ ichspi_lock = 1; } ich_init_opcodes(ich_gen); - ich_set_bbar(0); + ich_set_bbar(0, ich_gen); register_spi_master(&spi_master_ich7); break; case CHIPSET_ICH8: @@ -1946,7 +1946,7 @@ default: ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); msg_pdbg("0x%x: 0x%08x (BBAR)\n", ICH9_REG_BBAR, ichspi_bbar); - ich_set_bbar(0); + ich_set_bbar(0, ich_gen); break; } @@ -2099,7 +2099,7 @@ ichspi_lock = 1; } - ich_set_bbar(0); + ich_set_bbar(0, ich_generation); ich_init_opcodes(ich_generation); return 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/43500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6da6dccb413cbafa2fbaca213574f22c7a258139 Gerrit-Change-Number: 43500 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec@chromium.org> Gerrit-MessageType: newchange