Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/46140 ) Change subject: WIP: s25f.c: import file from cros flashrom ...................................................................... Patch Set 4: (11 comments) https://review.coreboot.org/c/flashrom/+/46140/2/chipdrivers.h File chipdrivers.h: https://review.coreboot.org/c/flashrom/+/46140/2/chipdrivers.h@24 PS2, Line 24: #include "writeprotect.h" /* for modifier_bits */
I don't think this is needed in this commit for adding the chip initial support. It provides the modifier_bits struct, used by the s25f_{set,get}_modifier_bits() prototypes. We could leave them out, but I think it's worth adding them now.
https://review.coreboot.org/c/flashrom/+/46140/2/s25f.c File s25f.c: https://review.coreboot.org/c/flashrom/+/46140/2/s25f.c@34 PS2, Line 34: * s25f.c - Helper functions for Spansion S25FL and S25FS SPI flash chips. : * Uses 24 bit addressing for the FS chips and 32 bit addressing for the FL : * chips (which is required by the overlayed sector size devices). : * TODO: Implement fancy hybrid sector architecture helpers.
separate out comment from license header. Done
https://review.coreboot.org/c/flashrom/+/46140/2/s25f.c@43 PS2, Line 43: #include "hwaccess.h"
is this needed? It was needed for the `be_to_cpu32` macro, but I have changed the code that used it now.
https://review.coreboot.org/c/flashrom/+/46140/2/s25f.c@45 PS2, Line 45: #include "writeprotect.h"
ditto. It provides the `struct modifier_bits` type.
https://review.coreboot.org/c/flashrom/+/46140/2/s25f.c@192 PS2, Line 192: unsigned char read_cr_cmd[] = { : CMD_RDAR, : (addr >> 16) & 0xff, : (addr >> 8) & 0xff, : (addr & 0xff), : 0x00, 0x00, 0x00, 0x00, : 0x00, 0x00, 0x00, 0x00, : };
looks like these various cmd blocks though the file are badly formatted. […] I've updated this one. I'm not sure what the indent levels should be for the others (e.g. in s25fs_write_cr), I can't find a comparable example in spi25.c. It seems like a weird mix of tabulation and regular indentation rules.
https://review.coreboot.org/c/flashrom/+/46140/2/s25f.c@489 PS2, Line 489: et;
= 0; This was never really used to store a return value, only to store the return code from spi_send_command(). I've changed it accordingly.
https://review.coreboot.org/c/flashrom/+/46140/2/s25f.c@494 PS2, Line 494: if (!ret) {
invert the ret check logic to avoid such a big block under a if branch. […] Done
https://review.coreboot.org/c/flashrom/+/46140/2/s25f.c@531 PS2, Line 531: return
ret = Restructured, no longer have ret variable.
https://review.coreboot.org/c/flashrom/+/46140/2/s25f.c@531 PS2, Line 531: return
ret = ditto
https://review.coreboot.org/c/flashrom/+/46140/2/s25f.c@534 PS2, Line 534: 0;
ret ditto
https://review.coreboot.org/c/flashrom/+/46140/4/s25f.c File s25f.c: https://review.coreboot.org/c/flashrom/+/46140/4/s25f.c@487 PS4, Line 487: int probe_spi_big_spansion(struct flashctx *flash) n.b. I have changed this function quite a bit: - Added context to msg_gdbg() debugging calls - Replaced type punned union + memcpy + endianness conversion with bitshift + bitwise or - Flattened control flow - Changed unsigned char -> uint8_t Compare at patchset 2 to patchset 4 to see the changes. -- To view, visit https://review.coreboot.org/c/flashrom/+/46140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2d23f9c36ce8b2959807fbeee7f60e02444e3763 Gerrit-Change-Number: 46140 Gerrit-PatchSet: 4 Gerrit-Owner: Nikolai Artemiev <nartemiev@google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec@chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Comment-Date: Fri, 06 Nov 2020 08:16:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Edward O'Callaghan <quasisec@chromium.org> Gerrit-MessageType: comment