August 2025 - flashrom-gerrit - mail.coreboot.org

Change in ...flashrom[master]: Add support for security register and SBULK command on Macronix chips
by vl_sk (Code Review) Jan. 13, 2026

Jan. 13, 2026

vl_sk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/32034 Change subject: Add support for security register and SBULK command on Macronix chips ...................................................................... Add support for security register and SBULK command on Macronix chips Signed-off-by: Vladimir Skokov <vl_sk(a)mail.ru> Change-Id: I6b3d7bd2625dec5fda7b85f421d40c49bbc528a6 --- M chipdrivers.h M flashchips.c M spi.h M spi25_statusreg.c 4 files changed, 78 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/32034/1 diff --git a/chipdrivers.h b/chipdrivers.h index 134ed26..54288cd 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -102,7 +102,9 @@ int spi_prettyprint_status_register_sst25(struct flashctx *flash); int spi_prettyprint_status_register_sst25vf016(struct flashctx *flash); int spi_prettyprint_status_register_sst25vf040b(struct flashctx *flash); +int spi_prettyprint_security_register_mx25(struct flashctx *flash); int spi_disable_blockprotect_sst26_global_unprotect(struct flashctx *flash); +int spi_disable_blockprotect_mx25_global_unprotect(struct flashctx *flash); /* sfdp.c */ int probe_spi_sfdp(struct flashctx *flash); diff --git a/flashchips.c b/flashchips.c index d85ea74..2c662e9 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8555,9 +8555,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register and SBLK/SBULK; MX25L12835F: configuration register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) supported */ .voltage = {2700, 3600}, @@ -8604,9 +8603,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register and SBLK/SBULK; MX25L12835F: configuration register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) supported */ .voltage = {2700, 3600}, @@ -8693,9 +8691,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8734,9 +8731,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8776,9 +8772,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8818,9 +8813,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8858,9 +8852,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, /* Multi I/O supported */ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8907,9 +8900,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, /* Multi I/O supported */ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, diff --git a/spi.h b/spi.h index 422e6a0..456d894 100644 --- a/spi.h +++ b/spi.h @@ -170,6 +170,15 @@ From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ #define JEDEC_BYTE_PROGRAM_4BA 0x12 +/* Read Security Register */ +#define JEDEC_RDSCUR 0x2B +#define JEDEC_RDSCUR_OUTSIZE 0x01 +#define JEDEC_RDSCUR_INSIZE 0x01 + +/* Do GBULK (gang block unlock) */ +#define JEDEC_GBULK 0x98 +#define JEDEC_GBULK_OUTSIZE 0x01 + /* Error codes */ #define SPI_GENERIC_ERROR -1 #define SPI_INVALID_OPCODE -2 diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 4cf7023..4cdf800 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -237,6 +237,28 @@ return spi_disable_blockprotect_generic(flash, 0x7C, 1 << 7, 0, 0xFF); } +int spi_disable_blockprotect_mx25_global_unprotect(struct flashctx *flash) +{ + static const unsigned char cmd[JEDEC_GBULK_OUTSIZE] = { JEDEC_GBULK }; + int ret; + + ret = spi_write_enable(flash); + if (ret) { + msg_cerr("Set WREN failed!\n"); + return -1; + } + + /* Send GBULK cmd to device. */ + ret = spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); + if (ret) { + msg_cerr("GBULK failed!\n"); + return -1; + } + + /* Disable standard blockprotect */ + return spi_disable_blockprotect_bp3_srwd(flash); +} + static void spi_prettyprint_status_register_hex(uint8_t status) { msg_cdbg("Chip status register is 0x%02x.\n", status); @@ -751,3 +773,32 @@ msg_cdbg("Resulting block protection : %s\n", bpt[(status & 0x1c) >> 2]); return 0; } + +/* === Macronix chips with Security Register === */ + +int spi_read_security_register(struct flashctx *flash) +{ + static const unsigned char cmd[JEDEC_RDSCUR_OUTSIZE] = { JEDEC_RDSCUR }; + unsigned char readarr[JEDEC_RDSCUR_INSIZE]; + int ret; + + ret = spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr); + if (ret) { + msg_cerr("RDSCUR failed!\n"); + return 0; + } + + return readarr[0]; +} + +int spi_prettyprint_security_register_mx25(struct flashctx *flash) +{ + int security_register = spi_read_security_register(flash); + int wpsel = !!(security_register & (1 << 7)); + + msg_cdbg("Chip security register: 0x%02X\n", security_register); + msg_cdbg("\tWPSEL is %s\n", wpsel ? "ON" : "OFF"); + + /* Print standard blockprotect info */ + return spi_prettyprint_status_register_bp3_srwd(flash); +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/flashrom/+/32034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6b3d7bd2625dec5fda7b85f421d40c49bbc528a6 Gerrit-Change-Number: 32034 Gerrit-PatchSet: 1 Gerrit-Owner: vl_sk Gerrit-MessageType: newchange

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Change in flashrom[master]: pcidev: On arm64 we are not getting a valid BAR0 address
by Martijn Berger (Code Review) Sept. 13, 2025

Sept. 13, 2025

Martijn Berger has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39965 ) Change subject: pcidev: On arm64 we are not getting a valid BAR0 address ...................................................................... pcidev: On arm64 we are not getting a valid BAR0 address It seems that there is some code to work around a possible bug in old versions of libpci. This trusts libpci if it is new enough Change-Id: I8bd32c6344b0831a949c3853abeb84905420922a Signed-off-by: Martijn Berger <martijn.berger(a)gmail.com> --- M pcidev.c M programmer.h 2 files changed, 30 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/65/39965/1 diff --git a/pcidev.c b/pcidev.c index 54c1fd3..973acde 100644 --- a/pcidev.c +++ b/pcidev.c @@ -30,20 +30,47 @@ TYPE_UNKNOWN }; +int pci_bar_nuber_from_offset(int offset) +{ + switch (offset) { + case PCI_BASE_ADDRESS_0: + return 0; + case PCI_BASE_ADDRESS_1: + return 1; + case PCI_BASE_ADDRESS_2: + return 2; + case PCI_BASE_ADDRESS_3: + return 3; + case PCI_BASE_ADDRESS_4: + return 4; + case PCI_BASE_ADDRESS_5: + return 5; + default: + return -1; + } + return -1; +} + uintptr_t pcidev_readbar(struct pci_dev *dev, int bar) { uint64_t addr; uint32_t upperaddr; uint8_t headertype; uint16_t supported_cycles; + int bar_number; enum pci_bartype bartype = TYPE_UNKNOWN; headertype = pci_read_byte(dev, PCI_HEADER_TYPE) & 0x7f; msg_pspew("PCI header type 0x%02x\n", headertype); + bar_number = pci_bar_nuber_from_offset(bar); - /* Don't use dev->base_addr[x] (as value for 'bar'), won't work on older libpci. */ - addr = pci_read_long(dev, bar); + if (PCI_LIB_VERSION >= 0x030500 && bar_number > -1) { + addr = dev->base_addr[bar_number]; + } else { + /* Don't use dev->base_addr[x] (as value for 'bar'), won't work on older libpci. */ + addr = pci_read_long(dev, bar); + } /* Sanity checks. */ switch (headertype) { diff --git a/programmer.h b/programmer.h index 9a41be1..5d4c1d7 100644 --- a/programmer.h +++ b/programmer.h @@ -190,6 +190,7 @@ // FIXME: This needs to be local, not global(?) extern struct pci_access *pacc; int pci_init_common(void); +int pci_bar_nuber_from_offset(int offset); uintptr_t pcidev_readbar(struct pci_dev *dev, int bar); struct pci_dev *pcidev_init(const struct dev_entry *devs, int bar); /* rpci_write_* are reversible writes. The original PCI config space register -- To view, visit https://review.coreboot.org/c/flashrom/+/39965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8bd32c6344b0831a949c3853abeb84905420922a Gerrit-Change-Number: 39965 Gerrit-PatchSet: 1 Gerrit-Owner: Martijn Berger Gerrit-MessageType: newchange

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[XS] Change in flashrom[main]: build: only add git describe for git checkouts
by Anastasia Klimchuk (Code Review) Aug. 31, 2025

Aug. 31, 2025

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/88967?usp=email ) Change subject: build: only add git describe for git checkouts ...................................................................... build: only add git describe for git checkouts Some tools, such as Buildroot, will use packed tarballs of cloned git repositories and trigger builds for the sources. This results in flashrom grabbing incorrect git information. The best option is to solely rely on the VERSION file. Change-Id: Iac60ae253263eab42361b0f73a9c9c95cd547eb5 Signed-off-by: Jacob Rothbauer <rothbauerj(a)hotmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/88967 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Vincent Fazio <vfazio(a)gmail.com> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M meson.build 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Vincent Fazio: Looks good to me, but someone else must approve Anastasia Klimchuk: Looks good to me, approved diff --git a/meson.build b/meson.build index 35feb33..dda636f 100644 --- a/meson.build +++ b/meson.build @@ -29,7 +29,7 @@ flashrom_version = meson.project_version() git = find_program('git', native : true, required : false) -if git.found() +if git.found() and fs.is_dir(meson.project_source_root()/'.git') version_git = run_command('git', 'describe', check : false) if version_git.returncode() == 0 flashrom_version += ' (git:@0@)'.format(version_git.stdout().strip()) -- To view, visit https://review.coreboot.org/c/flashrom/+/88967?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Iac60ae253263eab42361b0f73a9c9c95cd547eb5 Gerrit-Change-Number: 88967 Gerrit-PatchSet: 6 Gerrit-Owner: Jacob Rothbauer <rothbauerj(a)hotmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Vincent Fazio <vfazio(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in flashrom[main]: probe_spi_res1: Don't sent RDID opcode if the results are in cache
by Anastasia Klimchuk (Code Review) Aug. 30, 2025

Aug. 30, 2025

Anastasia Klimchuk has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/88101?usp=email ) Change subject: probe_spi_res1: Don't sent RDID opcode if the results are in cache ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: This probably needs a test for probe_spi_res1 too -- To view, visit https://review.coreboot.org/c/flashrom/+/88101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ifa087b66bac5a73db7b8ebaaed80665f2699e6b3 Gerrit-Change-Number: 88101 Gerrit-PatchSet: 7 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 30 Aug 2025 13:47:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in flashrom[main]: probe_spi_res1: Don't sent RDID opcode if the results are in cache
by Anastasia Klimchuk (Code Review) Aug. 30, 2025

Aug. 30, 2025

Attention is currently required from: Anastasia Klimchuk. Hello Peter Marheine, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/88101?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: probe_spi_res1: Don't sent RDID opcode if the results are in cache ...................................................................... probe_spi_res1: Don't sent RDID opcode if the results are in cache Probing function probe_spi_rdid implements a cache which stores a response on RDID opcode from the chip. This way RDID opcode is sent to chip once and then, if response is successful, it is reused. probe_spi_res1 is another probing function which also sends RDID opcode to the chip. However it was not checking the cache, and as a result RDID was additionally requested 4 more times (for each flashchip with registered probe_spi_res1 function). Note that the 4 extra RDID requests were happening for any probing, not only for chips with probe_spi_res1. This is because the probing goes through all the flashchips and tries each one. This patch changes probe_spi_res1 to check RDID results in the cache, and use the cached results if they are present. Otherwise RDID is sent to the chip. This patch starts the suit of tests which can go deep into probing operation. Initially the commit included the new tests only, but after writing new test the issue was discovered. Now the commit includes the fix and the test. The test is based on linux_spi emulation with all hw opcodes intercepted. Specifically for probe opcodes test can respond with given ID of chip vendor and model and keep the counter how many times probe opcode was sent. Change-Id: Ifa087b66bac5a73db7b8ebaaed80665f2699e6b3 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M spi25.c M tests/meson.build A tests/probe_spi.c M tests/tests.c M tests/tests.h 5 files changed, 274 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/01/88101/7 -- To view, visit https://review.coreboot.org/c/flashrom/+/88101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ifa087b66bac5a73db7b8ebaaed80665f2699e6b3 Gerrit-Change-Number: 88101 Gerrit-PatchSet: 7 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org>

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[L] Change in flashrom[main]: probe_spi_res1: Don't sent RDID opcode if the results are in cache
by Anastasia Klimchuk (Code Review) Aug. 30, 2025

Aug. 30, 2025

Attention is currently required from: Anastasia Klimchuk. Hello Peter Marheine, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/88101?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: probe_spi_res1: Don't sent RDID opcode if the results are in cache ...................................................................... probe_spi_res1: Don't sent RDID opcode if the results are in cache Probing function probe_spi_rdid implements a cache which stores a response on RDID opcode from the chip. This way RDID opcode is sent to chip once and then, if response is successful, it is reused. probe_spi_res1 is another probing function which also sends RDID opcode to the chip. However it was not checking the cache, and as a result RDID was additionally requested 4 more times (for each flashchip with registered probe_spi_res1 function). Note that the 4 extra RDID requests were happening for any probing, not only for chips with probe_spi_res1. This is because the probing goes through all the flashchips and tries each one. This patch changes probe_spi_res1 to check RDID results in the cache, and use the cached results if they are present. Otherwise RDID is sent to the chip. This patch starts the suit of tests which can go deep into probing operation. Initially the commit included the new tests only, but after writing new test the issue was discovered. Now the commit includes the fix and the test. The test is based on linux_spi emulation with all hw opcodes intercepted. Specifically for probe opcodes test can respond with given ID of chip vendor and model and keep the counter how many times probe opcode was sent. Change-Id: Ifa087b66bac5a73db7b8ebaaed80665f2699e6b3 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M spi25.c M tests/meson.build A tests/probe_spi.c M tests/tests.c M tests/tests.h 5 files changed, 274 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/01/88101/6 -- To view, visit https://review.coreboot.org/c/flashrom/+/88101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ifa087b66bac5a73db7b8ebaaed80665f2699e6b3 Gerrit-Change-Number: 88101 Gerrit-PatchSet: 6 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org>

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[L] Change in flashrom[main]: tests: Start adding more detailed tests for probing flow
by Anastasia Klimchuk (Code Review) Aug. 30, 2025

Aug. 30, 2025

Attention is currently required from: Anastasia Klimchuk. Hello Peter Marheine, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/88101?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: tests: Start adding more detailed tests for probing flow ...................................................................... tests: Start adding more detailed tests for probing flow This patch starts the suit of tests which can go deep into probing operation. The test is based on linux_spi emulation with all hw opcodes intercepted. Specifically for probe opcodes test can respond with given ID of chip vendor and model and keep the counter how many times probe opcode was sent. Change-Id: Ifa087b66bac5a73db7b8ebaaed80665f2699e6b3 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M tests/meson.build A tests/probe_spi.c M tests/tests.c M tests/tests.h 4 files changed, 264 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/01/88101/5 -- To view, visit https://review.coreboot.org/c/flashrom/+/88101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ifa087b66bac5a73db7b8ebaaed80665f2699e6b3 Gerrit-Change-Number: 88101 Gerrit-PatchSet: 5 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org>

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[L] Change in flashrom[main]: nv_sma_spi: Add Nvidia SMA Programmer
by Gilbert Chen (Code Review) Aug. 29, 2025

Aug. 29, 2025

Attention is currently required from: Anastasia Klimchuk, Peter Marheine, wthai(a)nvidia.com. Gilbert Chen has posted comments on this change by wthai(a)nvidia.com. ( https://review.coreboot.org/c/flashrom/+/88816?usp=email ) Change subject: nv_sma_spi: Add Nvidia SMA Programmer ...................................................................... Patch Set 3: (3 comments) File doc/classic_cli_manpage.rst: https://review.coreboot.org/c/flashrom/+/88816/comment/b48bc628_8e346de9?us… : PS2, Line 1468: . > You need to add `::` at the end of line, then command line below will be formatted as code. […] Acknowledged https://review.coreboot.org/c/flashrom/+/88816/comment/04e4f80c_a24ab091?us… : PS2, Line 1477: The optional ``spispeed`` parameter sets the target frequency in Hz. > Could you please add the list of valid values, and especially mention that if the spispeed value is […] Acknowledged Updated to mention that the device default setting if the spispeed value is not recognized. The default freq is retrieved from device. So, the default freq. cannot be hardcoded a value in doc file. https://review.coreboot.org/c/flashrom/+/88816/comment/111ecac9_b19bd08c?us… : PS2, Line 1480: value > Probably better use some real value (any of the valid ones) Acknowledged -- To view, visit https://review.coreboot.org/c/flashrom/+/88816?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I6b2522788db3dcee2b30faff29f605cede8c0eaf Gerrit-Change-Number: 88816 Gerrit-PatchSet: 3 Gerrit-Owner: wthai(a)nvidia.com Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Gilbert Chen Gerrit-CC: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: wthai(a)nvidia.com Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Fri, 29 Aug 2025 10:34:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[L] Change in flashrom[main]: nv_sma_spi: Add Nvidia SMA Programmer
by Gilbert Chen (Code Review) Aug. 29, 2025

Aug. 29, 2025

Attention is currently required from: Gilbert Chen, Peter Marheine, wthai(a)nvidia.com. Gilbert Chen has uploaded a new patch set (#3) to the change originally created by wthai(a)nvidia.com. ( https://review.coreboot.org/c/flashrom/+/88816?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: nv_sma_spi: Add Nvidia SMA Programmer ...................................................................... nv_sma_spi: Add Nvidia SMA Programmer Add initial support for System Management Agent (SMA) programmer. SMA is a SOC which is working as a side band management on Nvidia server board. One of its functionality is to flash firmware to other components. Test: 1. Build flashrom with this change. 2. Run operation: erase, write, read 3. All operations completed with expected performance. NV_SMA_SPI has been tested with the following SPI flash models: w25r128jw w25r64jv w25q16v Change-Id: I6b2522788db3dcee2b30faff29f605cede8c0eaf Co-Developed-by: Gilbert Chen <gilbertc(a)nvidia.com> Co-Developed-by: Willie Thai <wthai(a)nvidia.com> Signed-off-by: Willie Thai <wthai(a)nvidia.com> Signed-off-by: Gilbert Chen <gilbertc(a)nvidia.com> --- M doc/classic_cli_manpage.rst M doc/release_notes/devel.rst M include/programmer.h M meson.build M meson_options.txt A nv_sma_spi.c M programmer_table.c M test_build.sh 8 files changed, 798 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/16/88816/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/88816?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I6b2522788db3dcee2b30faff29f605cede8c0eaf Gerrit-Change-Number: 88816 Gerrit-PatchSet: 3 Gerrit-Owner: wthai(a)nvidia.com Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Gilbert Chen Gerrit-CC: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: wthai(a)nvidia.com Gerrit-Attention: Gilbert Chen Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org>

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[XS] Change in flashrom[main]: flashchips: Mark MT25QU02G as tested for PREW
by Anastasia Klimchuk (Code Review) Aug. 28, 2025

Aug. 28, 2025

Attention is currently required from: Nikolai Artemiev, Stefan Reinauer, Vincent Fazio. Anastasia Klimchuk has posted comments on this change by Vincent Fazio. ( https://review.coreboot.org/c/flashrom/+/88985?usp=email ) Change subject: flashchips: Mark MT25QU02G as tested for PREW ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/88985?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ida2ba300adf18280da325c1cf94a2df32f9163c6 Gerrit-Change-Number: 88985 Gerrit-PatchSet: 1 Gerrit-Owner: Vincent Fazio <vfazio(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Vincent Fazio <vfazio(a)gmail.com> Gerrit-Comment-Date: Fri, 29 Aug 2025 06:21:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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