May 2025 - flashrom-gerrit - mail.coreboot.org

Change in ...flashrom[master]: Add support for security register and SBULK command on Macronix chips
by vl_sk (Code Review) Jan. 13, 2026

Jan. 13, 2026

vl_sk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/32034 Change subject: Add support for security register and SBULK command on Macronix chips ...................................................................... Add support for security register and SBULK command on Macronix chips Signed-off-by: Vladimir Skokov <vl_sk(a)mail.ru> Change-Id: I6b3d7bd2625dec5fda7b85f421d40c49bbc528a6 --- M chipdrivers.h M flashchips.c M spi.h M spi25_statusreg.c 4 files changed, 78 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/32034/1 diff --git a/chipdrivers.h b/chipdrivers.h index 134ed26..54288cd 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -102,7 +102,9 @@ int spi_prettyprint_status_register_sst25(struct flashctx *flash); int spi_prettyprint_status_register_sst25vf016(struct flashctx *flash); int spi_prettyprint_status_register_sst25vf040b(struct flashctx *flash); +int spi_prettyprint_security_register_mx25(struct flashctx *flash); int spi_disable_blockprotect_sst26_global_unprotect(struct flashctx *flash); +int spi_disable_blockprotect_mx25_global_unprotect(struct flashctx *flash); /* sfdp.c */ int probe_spi_sfdp(struct flashctx *flash); diff --git a/flashchips.c b/flashchips.c index d85ea74..2c662e9 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8555,9 +8555,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register and SBLK/SBULK; MX25L12835F: configuration register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) supported */ .voltage = {2700, 3600}, @@ -8604,9 +8603,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register and SBLK/SBULK; MX25L12835F: configuration register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) supported */ .voltage = {2700, 3600}, @@ -8693,9 +8691,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8734,9 +8731,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8776,9 +8772,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8818,9 +8813,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8858,9 +8852,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, /* Multi I/O supported */ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8907,9 +8900,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, /* Multi I/O supported */ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, diff --git a/spi.h b/spi.h index 422e6a0..456d894 100644 --- a/spi.h +++ b/spi.h @@ -170,6 +170,15 @@ From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ #define JEDEC_BYTE_PROGRAM_4BA 0x12 +/* Read Security Register */ +#define JEDEC_RDSCUR 0x2B +#define JEDEC_RDSCUR_OUTSIZE 0x01 +#define JEDEC_RDSCUR_INSIZE 0x01 + +/* Do GBULK (gang block unlock) */ +#define JEDEC_GBULK 0x98 +#define JEDEC_GBULK_OUTSIZE 0x01 + /* Error codes */ #define SPI_GENERIC_ERROR -1 #define SPI_INVALID_OPCODE -2 diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 4cf7023..4cdf800 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -237,6 +237,28 @@ return spi_disable_blockprotect_generic(flash, 0x7C, 1 << 7, 0, 0xFF); } +int spi_disable_blockprotect_mx25_global_unprotect(struct flashctx *flash) +{ + static const unsigned char cmd[JEDEC_GBULK_OUTSIZE] = { JEDEC_GBULK }; + int ret; + + ret = spi_write_enable(flash); + if (ret) { + msg_cerr("Set WREN failed!\n"); + return -1; + } + + /* Send GBULK cmd to device. */ + ret = spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); + if (ret) { + msg_cerr("GBULK failed!\n"); + return -1; + } + + /* Disable standard blockprotect */ + return spi_disable_blockprotect_bp3_srwd(flash); +} + static void spi_prettyprint_status_register_hex(uint8_t status) { msg_cdbg("Chip status register is 0x%02x.\n", status); @@ -751,3 +773,32 @@ msg_cdbg("Resulting block protection : %s\n", bpt[(status & 0x1c) >> 2]); return 0; } + +/* === Macronix chips with Security Register === */ + +int spi_read_security_register(struct flashctx *flash) +{ + static const unsigned char cmd[JEDEC_RDSCUR_OUTSIZE] = { JEDEC_RDSCUR }; + unsigned char readarr[JEDEC_RDSCUR_INSIZE]; + int ret; + + ret = spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr); + if (ret) { + msg_cerr("RDSCUR failed!\n"); + return 0; + } + + return readarr[0]; +} + +int spi_prettyprint_security_register_mx25(struct flashctx *flash) +{ + int security_register = spi_read_security_register(flash); + int wpsel = !!(security_register & (1 << 7)); + + msg_cdbg("Chip security register: 0x%02X\n", security_register); + msg_cdbg("\tWPSEL is %s\n", wpsel ? "ON" : "OFF"); + + /* Print standard blockprotect info */ + return spi_prettyprint_status_register_bp3_srwd(flash); +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/flashrom/+/32034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6b3d7bd2625dec5fda7b85f421d40c49bbc528a6 Gerrit-Change-Number: 32034 Gerrit-PatchSet: 1 Gerrit-Owner: vl_sk Gerrit-MessageType: newchange

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Change in flashrom[master]: pcidev: On arm64 we are not getting a valid BAR0 address
by Martijn Berger (Code Review) Sept. 13, 2025

Sept. 13, 2025

Martijn Berger has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39965 ) Change subject: pcidev: On arm64 we are not getting a valid BAR0 address ...................................................................... pcidev: On arm64 we are not getting a valid BAR0 address It seems that there is some code to work around a possible bug in old versions of libpci. This trusts libpci if it is new enough Change-Id: I8bd32c6344b0831a949c3853abeb84905420922a Signed-off-by: Martijn Berger <martijn.berger(a)gmail.com> --- M pcidev.c M programmer.h 2 files changed, 30 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/65/39965/1 diff --git a/pcidev.c b/pcidev.c index 54c1fd3..973acde 100644 --- a/pcidev.c +++ b/pcidev.c @@ -30,20 +30,47 @@ TYPE_UNKNOWN }; +int pci_bar_nuber_from_offset(int offset) +{ + switch (offset) { + case PCI_BASE_ADDRESS_0: + return 0; + case PCI_BASE_ADDRESS_1: + return 1; + case PCI_BASE_ADDRESS_2: + return 2; + case PCI_BASE_ADDRESS_3: + return 3; + case PCI_BASE_ADDRESS_4: + return 4; + case PCI_BASE_ADDRESS_5: + return 5; + default: + return -1; + } + return -1; +} + uintptr_t pcidev_readbar(struct pci_dev *dev, int bar) { uint64_t addr; uint32_t upperaddr; uint8_t headertype; uint16_t supported_cycles; + int bar_number; enum pci_bartype bartype = TYPE_UNKNOWN; headertype = pci_read_byte(dev, PCI_HEADER_TYPE) & 0x7f; msg_pspew("PCI header type 0x%02x\n", headertype); + bar_number = pci_bar_nuber_from_offset(bar); - /* Don't use dev->base_addr[x] (as value for 'bar'), won't work on older libpci. */ - addr = pci_read_long(dev, bar); + if (PCI_LIB_VERSION >= 0x030500 && bar_number > -1) { + addr = dev->base_addr[bar_number]; + } else { + /* Don't use dev->base_addr[x] (as value for 'bar'), won't work on older libpci. */ + addr = pci_read_long(dev, bar); + } /* Sanity checks. */ switch (headertype) { diff --git a/programmer.h b/programmer.h index 9a41be1..5d4c1d7 100644 --- a/programmer.h +++ b/programmer.h @@ -190,6 +190,7 @@ // FIXME: This needs to be local, not global(?) extern struct pci_access *pacc; int pci_init_common(void); +int pci_bar_nuber_from_offset(int offset); uintptr_t pcidev_readbar(struct pci_dev *dev, int bar); struct pci_dev *pcidev_init(const struct dev_entry *devs, int bar); /* rpci_write_* are reversible writes. The original PCI config space register -- To view, visit https://review.coreboot.org/c/flashrom/+/39965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8bd32c6344b0831a949c3853abeb84905420922a Gerrit-Change-Number: 39965 Gerrit-PatchSet: 1 Gerrit-Owner: Martijn Berger Gerrit-MessageType: newchange

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Change in flashrom[master]: cli_classic.c: Add runtime measurement
by Simon Buhrow (Code Review) Aug. 19, 2025

Aug. 19, 2025

Simon Buhrow has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47805 ) Change subject: cli_classic.c: Add runtime measurement ...................................................................... cli_classic.c: Add runtime measurement To get an fast and easy feedback on how parameters effect runtime (e.g. clock setting, polling delays, ...). Signed-off-by: Simon Buhrow <simon.buhrow(a)posteo.de> Change-Id: I2238b3f3e6c2ab7745994662a88787fa2e86d480 --- M cli_classic.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/05/47805/1 diff --git a/cli_classic.c b/cli_classic.c index ae7f6ef..0d5381f 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -24,6 +24,7 @@ #include <string.h> #include <stdlib.h> #include <getopt.h> +#include <time.h> #include "flash.h" #include "flashchips.h" #include "fmap.h" @@ -142,6 +143,7 @@ /* Probe for up to eight flash chips. */ struct flashctx flashes[8] = {{0}}; struct flashctx *fill_flash; + struct timespec time_start, time_end; const char *name; int namelen, opt, i, j; int startchip = -1, chipcount = 0, option_index = 0, force = 0, ifd = 0, fmap = 0; @@ -528,6 +530,8 @@ /* FIXME: Delay calibration should happen in programmer code. */ myusec_calibrate_delay(); + timespec_get(&time_start, TIME_UTC); + if (programmer_init(prog, pparam)) { msg_perr("Error: Programmer initialization failed.\n"); ret = 1; @@ -806,6 +810,9 @@ for (i = 0; i < chipcount; i++) free(flashes[i].chip); + timespec_get(&time_end, TIME_UTC); + msg_gdbg("Runtime: %d:%2d min:s\n", (int)((time_end.tv_sec-time_start.tv_sec) / 60), (int)(time_end.tv_sec-time_start.tv_sec) % 60); + layout_cleanup(&include_args); free(filename); free(fmapfile); -- To view, visit https://review.coreboot.org/c/flashrom/+/47805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2238b3f3e6c2ab7745994662a88787fa2e86d480 Gerrit-Change-Number: 47805 Gerrit-PatchSet: 1 Gerrit-Owner: Simon Buhrow Gerrit-MessageType: newchange

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[XS] Change in flashrom[main]: Add more delay time for jlink power on feature to stabilize the LDO a...
by Anastasia Klimchuk (Code Review) May 25, 2025

May 25, 2025

Attention is currently required from: attila-v. Anastasia Klimchuk has posted comments on this change by attila-v. ( https://review.coreboot.org/c/flashrom/+/86085?usp=email ) Change subject: Add more delay time for jlink power on feature to stabilize the LDO and the decoupling capacitors ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/86085/comment/db3dda82_d241be66?us… : PS2, Line 7: Add more delay time for jlink power on feature to stabilize the LDO and the decoupling capacitors > For this, I can give a suggestion, you can use it or compose a different one (just make sure it wrap […] Attila, I wanted to check, are you planning to fix the commit message? If you are busy I can do that (if you agree with my wording) -- To view, visit https://review.coreboot.org/c/flashrom/+/86085?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ic2dd94e99ac6ffa17a009b8488ce027698ae2c28 Gerrit-Change-Number: 86085 Gerrit-PatchSet: 3 Gerrit-Owner: attila-v Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: attila-v Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: attila-v Gerrit-Comment-Date: Sun, 25 May 2025 11:48:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[S] Change in flashrom[main]: fmap: Skip unreadable regions when attempting to locate FMAP
by Anastasia Klimchuk (Code Review) May 22, 2025

May 22, 2025

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/87748?usp=email ) Change subject: fmap: Skip unreadable regions when attempting to locate FMAP ...................................................................... fmap: Skip unreadable regions when attempting to locate FMAP When using the on-chip FMAP to restrict flashrom operations to one or more regions (--fmap), flashrom must first locate the FMAP. This requires flashrom to read from multiple addresses, some of which may be located in regions which are not readable (such as the Intel ME region). In order to avoid a substantial amount of output from read_flash() when trying to locate the FMAP in these regions, set `the skip_unreadable_regions` flag before performing any reads to locate the FMAP, and restore the original flag value when finished. This resolves https://ticket.coreboot.org/issues/587 TEST=build flashrom, use cli to update COREBOOT and EC FMAP regions on an Intel Alderlake-N platform board (starlabs/starlite_adl). Change-Id: Ie78b977b4e6a5db02a25e69603f697834043ea99 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/87748 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M fmap.c 1 file changed, 11 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/fmap.c b/fmap.c index 50cb969..7081598 100644 --- a/fmap.c +++ b/fmap.c @@ -190,6 +190,7 @@ struct fmap *fmap; const unsigned int chip_size = flashctx->chip->total_size * 1024; const int sig_len = strlen(FMAP_SIGNATURE); + bool skip_unreadable_orig = flashctx->flags.skip_unreadable_regions; if (rom_offset + len > flashctx->chip->total_size * 1024) return 1; @@ -207,6 +208,13 @@ } /* + * Ignore unreadable regions when trying to locate the FMAP, in order + * to avoid a large amount of false-error prints to stderr. Unreadable + * regions have already reported so errors here are redundant. + */ + flashctx->flags.skip_unreadable_regions = true; + + /* * For efficient operation, we start with the largest stride possible * and then decrease the stride on each iteration. Also, check for a * remainder when modding the offset with the previous stride. This @@ -264,6 +272,9 @@ break; } + /* Restore original flag, since we're done searching */ + flashctx->flags.skip_unreadable_regions = skip_unreadable_orig; + if (!fmap_found) goto _free_ret; -- To view, visit https://review.coreboot.org/c/flashrom/+/87748?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ie78b977b4e6a5db02a25e69603f697834043ea99 Gerrit-Change-Number: 87748 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in flashrom[main]: fmap: Skip unreadable regions when attempting to locate FMAP
by Anastasia Klimchuk (Code Review) May 19, 2025

May 19, 2025

Attention is currently required from: Matt DeVillier. Anastasia Klimchuk has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/flashrom/+/87748?usp=email ) Change subject: fmap: Skip unreadable regions when attempting to locate FMAP ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/87748?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ie78b977b4e6a5db02a25e69603f697834043ea99 Gerrit-Change-Number: 87748 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Mon, 19 May 2025 22:26:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in flashrom[main]: fmap: Skip unreadable regions when attempting to locate FMAP
by Matt DeVillier (Code Review) May 19, 2025

May 19, 2025

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/87748?usp=email ) Change subject: fmap: Skip unreadable regions when attempting to locate FMAP ...................................................................... fmap: Skip unreadable regions when attempting to locate FMAP When using the on-chip FMAP to restrict flashrom operations to one or more regions (--fmap), flashrom must first locate the FMAP. This requires flashrom to read from multiple addresses, some of which may be located in regions which are not readable (such as the Intel ME region). In order to avoid a substantial amount of output from read_flash() when trying to locate the FMAP in these regions, set `the skip_unreadable_regions` flag before performing any reads to locate the FMAP, and restore the original flag value when finished. This resolves https://ticket.coreboot.org/issues/587 TEST=build flashrom, use cli to update COREBOOT and EC FMAP regions on an Intel Alderlake-N platform board (starlabs/starlite_adl). Change-Id: Ie78b977b4e6a5db02a25e69603f697834043ea99 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M fmap.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/48/87748/1 diff --git a/fmap.c b/fmap.c index 50cb969..7081598 100644 --- a/fmap.c +++ b/fmap.c @@ -190,6 +190,7 @@ struct fmap *fmap; const unsigned int chip_size = flashctx->chip->total_size * 1024; const int sig_len = strlen(FMAP_SIGNATURE); + bool skip_unreadable_orig = flashctx->flags.skip_unreadable_regions; if (rom_offset + len > flashctx->chip->total_size * 1024) return 1; @@ -207,6 +208,13 @@ } /* + * Ignore unreadable regions when trying to locate the FMAP, in order + * to avoid a large amount of false-error prints to stderr. Unreadable + * regions have already reported so errors here are redundant. + */ + flashctx->flags.skip_unreadable_regions = true; + + /* * For efficient operation, we start with the largest stride possible * and then decrease the stride on each iteration. Also, check for a * remainder when modding the offset with the previous stride. This @@ -264,6 +272,9 @@ break; } + /* Restore original flag, since we're done searching */ + flashctx->flags.skip_unreadable_regions = skip_unreadable_orig; + if (!fmap_found) goto _free_ret; -- To view, visit https://review.coreboot.org/c/flashrom/+/87748?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ie78b977b4e6a5db02a25e69603f697834043ea99 Gerrit-Change-Number: 87748 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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[S] Change in flashrom[main]: doc/devel: Add info about new libflashrom APIs
by Anastasia Klimchuk (Code Review) May 16, 2025

May 16, 2025

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/87644?usp=email ) Change subject: doc/devel: Add info about new libflashrom APIs ...................................................................... doc/devel: Add info about new libflashrom APIs Change-Id: I98524353b8bedff3364568636ed42a4bd6ce8b3d Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/87644 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Peter Marheine <pmarheine(a)chromium.org> --- M doc/release_notes/devel.rst 1 file changed, 39 insertions(+), 4 deletions(-) Approvals: Peter Marheine: Looks good to me, approved build bot (Jenkins): Verified diff --git a/doc/release_notes/devel.rst b/doc/release_notes/devel.rst index 2a2870d..ef8364d 100644 --- a/doc/release_notes/devel.rst +++ b/doc/release_notes/devel.rst @@ -52,7 +52,15 @@ to ``enabled`` in which case the build will fail if the requirements are not satisfied. -New libflashrom API for progress reporting +Programmer updates +------------------ + +* spidriver: Add support for the Excamera Labs SPIDriver + +libflashrom API updates +======================= + +New API for progress reporting ------------------------------------------ The old ``flashrom_set_progress_callback`` function for requesting progress updates @@ -65,7 +73,34 @@ define their own global state to track progress, and it was impossible to fix that issue while maintaining binary compatibility without adding a new API. -Programmer updates ------------------- +New API for logging and setting log level +----------------------------------------- -* spidriver: Add support for the Excamera Labs SPIDriver +New API ``flashrom_set_log_callback_v2`` is added which allows the users to provide +a pointer to user data, the latter is managed by the caller of the API. New API also +introduces a new signature for log callback function, ``flashrom_log_callback_v2``. + +New API supports setting the log level for messages from libflashrom, ``flashrom_set_log_level``. +The log callback is invoked only for the messages with log level less or equal than the one +requested (i.e. only for the messages at least as urgent as the level requested). + +Old API ``flashrom_set_log_callback`` without user data continues to work as before. + +New API for probing flashchips +------------------------------ + +New API for probing is added ``flashrom_flash_probe_v2`` which can (if requested) +go through all known flashchips and find all matches. v2 returns the number of matches +found (or 0 if none found) and the list of names of all matched entries. + +``flashrom_flash_probe_v2`` continues to support an optional parameter ``chip_name`` +if the caller want to probe for only one specific chip with given name. + +Old API ``flashrom_flash_probe`` which stops probing if more than one chip entry matches +continues to work as before. + +New API to get list of supported programmers +-------------------------------------------- + +New API ``flashrom_supported_programmers`` returns the list of all programmers that are +supported on a current run environment. -- To view, visit https://review.coreboot.org/c/flashrom/+/87644?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I98524353b8bedff3364568636ed42a4bd6ce8b3d Gerrit-Change-Number: 87644 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Dmitry Zhadinets <dzhadinets(a)gmail.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in flashrom[main]: doc/devel: Add info about new libflashrom APIs
by Peter Marheine (Code Review) May 12, 2025

May 12, 2025

Attention is currently required from: Anastasia Klimchuk, Dmitry Zhadinets. Peter Marheine has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/87644?usp=email ) Change subject: doc/devel: Add info about new libflashrom APIs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/87644?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I98524353b8bedff3364568636ed42a4bd6ce8b3d Gerrit-Change-Number: 87644 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Dmitry Zhadinets <dzhadinets(a)gmail.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Dmitry Zhadinets <dzhadinets(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Mon, 12 May 2025 23:50:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in flashrom[main]: cli: Use flashrom_supported_programmers API in cli
by Anastasia Klimchuk (Code Review) May 12, 2025

May 12, 2025

Attention is currently required from: Dmitry Zhadinets. Anastasia Klimchuk has posted comments on this change by Dmitry Zhadinets. ( https://review.coreboot.org/c/flashrom/+/87195?usp=email ) Change subject: cli: Use flashrom_supported_programmers API in cli ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > I just thought about something, it's for the separate commit. […] I made a patch and added all updated for libflashrom API in one patch CB:87644 (added you as reviewer) -- To view, visit https://review.coreboot.org/c/flashrom/+/87195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I86ac83ee0ef4e850e69aa4e7b607e28ebab9d3d5 Gerrit-Change-Number: 87195 Gerrit-PatchSet: 2 Gerrit-Owner: Dmitry Zhadinets <dzhadinets(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Dmitry Zhadinets <dzhadinets(a)gmail.com> Gerrit-Comment-Date: Mon, 12 May 2025 12:17:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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