December 2025 - flashrom-gerrit

Change in ...flashrom[master]: Add support for security register and SBULK command on Macronix chips
by vl_sk (Code Review) Jan. 13, 2026

Jan. 13, 2026

vl_sk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/32034 Change subject: Add support for security register and SBULK command on Macronix chips ...................................................................... Add support for security register and SBULK command on Macronix chips Signed-off-by: Vladimir Skokov <vl_sk(a)mail.ru> Change-Id: I6b3d7bd2625dec5fda7b85f421d40c49bbc528a6 --- M chipdrivers.h M flashchips.c M spi.h M spi25_statusreg.c 4 files changed, 78 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/32034/1 diff --git a/chipdrivers.h b/chipdrivers.h index 134ed26..54288cd 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -102,7 +102,9 @@ int spi_prettyprint_status_register_sst25(struct flashctx *flash); int spi_prettyprint_status_register_sst25vf016(struct flashctx *flash); int spi_prettyprint_status_register_sst25vf040b(struct flashctx *flash); +int spi_prettyprint_security_register_mx25(struct flashctx *flash); int spi_disable_blockprotect_sst26_global_unprotect(struct flashctx *flash); +int spi_disable_blockprotect_mx25_global_unprotect(struct flashctx *flash); /* sfdp.c */ int probe_spi_sfdp(struct flashctx *flash); diff --git a/flashchips.c b/flashchips.c index d85ea74..2c662e9 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8555,9 +8555,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register and SBLK/SBULK; MX25L12835F: configuration register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) supported */ .voltage = {2700, 3600}, @@ -8604,9 +8603,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register and SBLK/SBULK; MX25L12835F: configuration register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) supported */ .voltage = {2700, 3600}, @@ -8693,9 +8691,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8734,9 +8731,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8776,9 +8772,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8818,9 +8813,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8858,9 +8852,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, /* Multi I/O supported */ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8907,9 +8900,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, /* Multi I/O supported */ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, diff --git a/spi.h b/spi.h index 422e6a0..456d894 100644 --- a/spi.h +++ b/spi.h @@ -170,6 +170,15 @@ From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ #define JEDEC_BYTE_PROGRAM_4BA 0x12 +/* Read Security Register */ +#define JEDEC_RDSCUR 0x2B +#define JEDEC_RDSCUR_OUTSIZE 0x01 +#define JEDEC_RDSCUR_INSIZE 0x01 + +/* Do GBULK (gang block unlock) */ +#define JEDEC_GBULK 0x98 +#define JEDEC_GBULK_OUTSIZE 0x01 + /* Error codes */ #define SPI_GENERIC_ERROR -1 #define SPI_INVALID_OPCODE -2 diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 4cf7023..4cdf800 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -237,6 +237,28 @@ return spi_disable_blockprotect_generic(flash, 0x7C, 1 << 7, 0, 0xFF); } +int spi_disable_blockprotect_mx25_global_unprotect(struct flashctx *flash) +{ + static const unsigned char cmd[JEDEC_GBULK_OUTSIZE] = { JEDEC_GBULK }; + int ret; + + ret = spi_write_enable(flash); + if (ret) { + msg_cerr("Set WREN failed!\n"); + return -1; + } + + /* Send GBULK cmd to device. */ + ret = spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); + if (ret) { + msg_cerr("GBULK failed!\n"); + return -1; + } + + /* Disable standard blockprotect */ + return spi_disable_blockprotect_bp3_srwd(flash); +} + static void spi_prettyprint_status_register_hex(uint8_t status) { msg_cdbg("Chip status register is 0x%02x.\n", status); @@ -751,3 +773,32 @@ msg_cdbg("Resulting block protection : %s\n", bpt[(status & 0x1c) >> 2]); return 0; } + +/* === Macronix chips with Security Register === */ + +int spi_read_security_register(struct flashctx *flash) +{ + static const unsigned char cmd[JEDEC_RDSCUR_OUTSIZE] = { JEDEC_RDSCUR }; + unsigned char readarr[JEDEC_RDSCUR_INSIZE]; + int ret; + + ret = spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr); + if (ret) { + msg_cerr("RDSCUR failed!\n"); + return 0; + } + + return readarr[0]; +} + +int spi_prettyprint_security_register_mx25(struct flashctx *flash) +{ + int security_register = spi_read_security_register(flash); + int wpsel = !!(security_register & (1 << 7)); + + msg_cdbg("Chip security register: 0x%02X\n", security_register); + msg_cdbg("\tWPSEL is %s\n", wpsel ? "ON" : "OFF"); + + /* Print standard blockprotect info */ + return spi_prettyprint_status_register_bp3_srwd(flash); +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/flashrom/+/32034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6b3d7bd2625dec5fda7b85f421d40c49bbc528a6 Gerrit-Change-Number: 32034 Gerrit-PatchSet: 1 Gerrit-Owner: vl_sk Gerrit-MessageType: newchange

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[XS] Change in flashrom[main]: doc: Update Windows building instructions.
by Antonio Vázquez Blanco (Code Review) Dec. 31, 2025

Dec. 31, 2025

Antonio Vázquez Blanco has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/90665?usp=email ) Change subject: doc: Update Windows building instructions. ...................................................................... doc: Update Windows building instructions. The default MSYS environment is not UCRT64 instead of MINGW64 so use that instead. Also, libjaylink now is not available in unstable versioning and stable version should be used. Change-Id: Id0230e8477c1fb22efa87b7660d2ebd3aaa37f28 Signed-off-by: Antonio Vázquez Blanco <antoniovazquezblanco(a)gmail.com> --- M doc/dev_guide/building_from_source.rst 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/65/90665/1 diff --git a/doc/dev_guide/building_from_source.rst b/doc/dev_guide/building_from_source.rst index 2394767..9f0d566 100644 --- a/doc/dev_guide/building_from_source.rst +++ b/doc/dev_guide/building_from_source.rst @@ -111,17 +111,17 @@ from `ni.com <https://www.ni.com/en-us/support/downloads/drivers/download.ni-845x-driver-…>`_ and build flashrom for **32-bit**. Add ``-Dprogrammer=ni845x_spi`` to your meson configuration. - In the MINGW64 shell run:: + In the MSYS2 UCRT64 shell run:: pacman -Sy \ - mingw-w64-x86_64-gcc mingw-w64-x86_64-meson mingw-w64-x86_64-ninja mingw-w64-x86_64-pkg-config mingw-w64-x86_64-python-sphinx \ - mingw-w64-x86_64-cmocka mingw-w64-x86_64-libusb mingw-w64-x86_64-libftdi mingw-w64-x86_64-libjaylink-git + mingw-w64-ucrt-x86_64-gcc mingw-w64-ucrt-x86_64-meson mingw-w64-ucrt-x86_64-ninja mingw-w64-ucrt-x86_64-pkg-config mingw-w64-ucrt-x86_64-python-sphinx \ + mingw-w64-ucrt-x86_64-cmocka mingw-w64-ucrt-x86_64-libusb mingw-w64-ucrt-x86_64-libftdi mingw-w64-ucrt-x86_64-libjaylink For building flashrom as 32-bit application, use the MSYS2 MINGW32 shell and run:: pacman -Sy \ mingw-w64-i686-gcc mingw-w64-i686-meson mingw-w64-i686-ninja mingw-w64-i686-pkg-config mingw-w64-i686-python-sphinx \ - mingw-w64-i686-cmocka mingw-w64-i686-libusb mingw-w64-i686-libftdi mingw-w64-i686-libjaylink-git + mingw-w64-i686-cmocka mingw-w64-i686-libusb mingw-w64-i686-libftdi mingw-w64-i686-libjaylink MacOS """"" -- To view, visit https://review.coreboot.org/c/flashrom/+/90665?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Id0230e8477c1fb22efa87b7660d2ebd3aaa37f28 Gerrit-Change-Number: 90665 Gerrit-PatchSet: 1 Gerrit-Owner: Antonio Vázquez Blanco <antoniovazquezblanco(a)gmail.com>

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[XS] Change in flashrom[main]: nicintel_spi: fix truncated MMIO BAR on 64-bit systems
by Fabian Druschke (Code Review) Dec. 29, 2025

Dec. 29, 2025

Fabian Druschke has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/90638?usp=email ) Change subject: nicintel_spi: fix truncated MMIO BAR on 64-bit systems ...................................................................... nicintel_spi: fix truncated MMIO BAR on 64-bit systems nicintel_spi stored BAR0 into a 32-bit variable. On systems where the NIC gets a 64-bit MMIO BAR above 4G, this truncates the address and causes /dev/mem mmap failures (EPERM) and crashes. Use uintptr_t for the MMIO base address so 64-bit BARs are handled correctly. Tested by reading M25P40 (512 kB) on Intel 82599 (8086:10fb). Change-Id: I6eaf342a87c020b31a1e8ad3b9dd63f6519d8517 Signed-off-by: Fabian Druschke <fdruschke(a)outlook.com> --- M nicintel_spi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/38/90638/1 diff --git a/nicintel_spi.c b/nicintel_spi.c index fac6e54..5e7a7ab 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -285,7 +285,7 @@ if (!dev) return 1; - uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + uintptr_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); if (!io_base_addr) return 1; -- To view, visit https://review.coreboot.org/c/flashrom/+/90638?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I6eaf342a87c020b31a1e8ad3b9dd63f6519d8517 Gerrit-Change-Number: 90638 Gerrit-PatchSet: 1 Gerrit-Owner: Fabian Druschke <fdruschke(a)outlook.com>

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[M] Change in flashrom[main]: at45db: Add support for AT45DB641E flash chip
by Marco (Code Review) Dec. 29, 2025

Dec. 29, 2025

Attention is currently required from: Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer. Hello Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/90365?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: at45db: Add support for AT45DB641E flash chip ...................................................................... at45db: Add support for AT45DB641E flash chip The AT45DB641E (64-Mbit DataFlash) was incorrectly identified as AT45DB642D because both chips share the same JEDEC ID (0x1F2800). This caused read/write operations to fail due to fundamentally different memory architectures: - AT45DB642D: 1024/1056 byte pages, 8192 pages total - AT45DB641E: 256/264 byte pages, 32768 pages total This patch adds Extended Device Information (EDI) based detection to distinguish E-series chips. The AT45DB641E reports EDI = 0x0100 in bytes 3-4 of the RDID response. Datasheet: https://www.renesas.com/en/document/dst/at45db641e-datasheet?r=1608921 Changes: - Add probe_spi_at45db_e() function for E-series detection - Add at45db_read_edi() helper to read Extended Device Information - Add AT45DB_EDI_ESERIES macro for E-series EDI value - Add AT45DB641E chip definition with correct sector geometry - Add PROBE_SPI_AT45DB_E enum value TEST=Verified on real AT45DB641E hardware using pico-serprog (https://github.com/stacksmashing/pico-serprog) - Chip correctly identified as AT45DB641E (8448 kB) - Read operations: consistent checksums across multiple reads - Erase: full chip erase successful (~80 seconds) - Write: 8448 KB random data written and verified successfully - Verify: MD5 checksums match between written and read-back data Change-Id: I09547b857b74df7a5d1c7fe7c61e9474460870e2 Signed-off-by: Marco Müller <hello(a)annoyedmilk.ch> --- M at45db.c M flashchips/atmel.c M flashrom.c M include/chipdrivers.h M include/flash.h M include/flashchips.h 6 files changed, 97 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/65/90365/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/90365?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I09547b857b74df7a5d1c7fe7c61e9474460870e2 Gerrit-Change-Number: 90365 Gerrit-PatchSet: 3 Gerrit-Owner: Marco <hello(a)annoyedmilk.ch> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com>

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[M] Change in flashrom[main]: at45db: Add support for AT45DB641E flash chip
by Marco (Code Review) Dec. 29, 2025

Dec. 29, 2025

Attention is currently required from: Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer. Marco has posted comments on this change by Marco. ( https://review.coreboot.org/c/flashrom/+/90365?usp=email ) Change subject: at45db: Add support for AT45DB641E flash chip ...................................................................... Patch Set 2: (3 comments) File at45db.c: https://review.coreboot.org/c/flashrom/+/90365/comment/b7afa17b_d33b8c63?us… : PS1, Line 76: int probe_spi_at45db_e(struct flashctx *flash) > thanks! now there is no code duplication […] I'm currently on holiday without access to the hardware, so I can't verify the swapped order works correctly on the AT45DB641E right now. I'll test it when I'm back and update the patch if it does not works as expected. File at45db.c: https://review.coreboot.org/c/flashrom/+/90365/comment/a1c55657_553a2984?us… : PS2, Line 8: > You are adding a new feature here, if you want you can add your copyright line in this file? (below […] Yes, I'd love to! This is my first open source commit, so I really appreciate you guiding me through it with your patience and helpful suggestions :) File include/flashchips.h: https://review.coreboot.org/c/flashrom/+/90365/comment/93fa1ea4_4ce03ff9?us… : PS2, Line 189: #define ATMEL_AT45DB641E /* same as above but with EDI 0x0100 */ > I can see this is a pattern which started before you, but I am looking at this and don't understand […] Acknowledged -- To view, visit https://review.coreboot.org/c/flashrom/+/90365?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I09547b857b74df7a5d1c7fe7c61e9474460870e2 Gerrit-Change-Number: 90365 Gerrit-PatchSet: 2 Gerrit-Owner: Marco <hello(a)annoyedmilk.ch> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Mon, 29 Dec 2025 16:42:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marco <hello(a)annoyedmilk.ch> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[S] Change in flashrom[main]: dmi.h: Extract DMI declarations to a separate header
by Antonio Vázquez Blanco (Code Review) Dec. 29, 2025

Dec. 29, 2025

Antonio Vázquez Blanco has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/90632?usp=email ) Change subject: dmi.h: Extract DMI declarations to a separate header ...................................................................... dmi.h: Extract DMI declarations to a separate header This patch moves all the declarations relevant to dmi into their own header in include/dmi.h. The corresponding functions implementations are already in dmi.c, so the declarations naturally can be in dmi.h Currently, most of the declarations reside in programmer.h making it difficult to really understand file dependency. Change-Id: I5fcb14da0b7f478a4f6badc8929c8389a5fa3e3c Signed-off-by: Antonio Vázquez <antoniovazquezblanco(a)gmail.com> --- M board_enable.c M dmi.c A include/dmi.h M include/programmer.h M internal.c 5 files changed, 26 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/32/90632/1 diff --git a/board_enable.c b/board_enable.c index c0f6a51..6a86e57 100644 --- a/board_enable.c +++ b/board_enable.c @@ -19,6 +19,7 @@ #include "flash.h" #include "programmer.h" #include "pcidev.h" +#include "dmi.h" #if defined(__i386__) || defined(__x86_64__) diff --git a/dmi.c b/dmi.c index e19f596..488a908 100644 --- a/dmi.c +++ b/dmi.c @@ -8,6 +8,8 @@ * SPDX-FileCopyrightText: 2011-2013 Stefan Tauner */ +#include "dmi.h" + /* strnlen is in POSIX but was a GNU extension up to glibc 2.10 */ #if (__GLIBC__ == 2 && __GLIBC_MINOR__ < 10) || __GLIBC__ < 2 #define _GNU_SOURCE diff --git a/include/dmi.h b/include/dmi.h new file mode 100644 index 0000000..b5b629e --- /dev/null +++ b/include/dmi.h @@ -0,0 +1,22 @@ +/* + * This file is part of the flashrom project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef __DMI_H__ +#define __DMI_H__ + +#if defined(__i386__) || defined(__x86_64__) + +#include <stdbool.h> + +void dmi_init(int *is_laptop); + +bool dmi_is_supported(void); + +int dmi_match(const char *pattern); + +#endif // defined(__i386__) || defined(__x86_64__) + +#endif // __DMI_H__ diff --git a/include/programmer.h b/include/programmer.h index 116e81c..b2f13e2 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -212,13 +212,6 @@ int cb_parse_table(const char **vendor, const char **model); int cb_check_image(const uint8_t *bios, unsigned int size); -/* dmi.c */ -#if defined(__i386__) || defined(__x86_64__) -void dmi_init(int *is_laptop); -bool dmi_is_supported(void); -int dmi_match(const char *pattern); -#endif // defined(__i386__) || defined(__x86_64__) - /* internal.c */ struct superio { uint16_t vendor; diff --git a/internal.c b/internal.c index 3251f84..31c0349 100644 --- a/internal.c +++ b/internal.c @@ -13,6 +13,7 @@ #include "flash.h" #include "programmer.h" #include "pcidev.h" +#include "dmi.h" #if defined(__i386__) || defined(__x86_64__) #include "hwaccess_x86_io.h" -- To view, visit https://review.coreboot.org/c/flashrom/+/90632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I5fcb14da0b7f478a4f6badc8929c8389a5fa3e3c Gerrit-Change-Number: 90632 Gerrit-PatchSet: 1 Gerrit-Owner: Antonio Vázquez Blanco <antoniovazquezblanco(a)gmail.com>

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[M] Change in flashrom[main]: flashchips: Add W77Q{64,128}NW
by Eugene Goubine (Code Review) Dec. 21, 2025

Dec. 21, 2025

Eugene Goubine has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/90583?usp=email ) Change subject: flashchips: Add W77Q{64,128}NW ...................................................................... flashchips: Add W77Q{64,128}NW Tested:probe, read, write, erase via ch341a_spi http://paste.flashrom.org/view.php?id=3799 ds: https://www.winbond.com/hq/product/trustme/w77q-trustme-secure-flash-memory… Change-Id: I91a5a2a54888999c01af798dd1e47e99bbf8700d Signed-off-by: Evgeni Goubine Bricker <egoubine(a)winbond.com> --- M flashchips/winbond.c 1 file changed, 72 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/83/90583/1 diff --git a/flashchips/winbond.c b/flashchips/winbond.c index 7a29442..8d3e1cd 100644 --- a/flashchips/winbond.c +++ b/flashchips/winbond.c @@ -3595,3 +3595,75 @@ .read = SPI_CHIP_READ, .voltage = {1700, 1950}, }, + + { + .vendor = "Winbond", + .name = "W77Q64NW", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W77Q64_W, + .total_size = 8192, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_QPI | FEATURE_4BA, + .tested = {.probe = OK, .read = OK, .erase = OK, .write = OK, .wp = NA}, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {1700, 1950}, + }, + + { + .vendor = "Winbond", + .name = "W77Q128NW", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W77Q128_W, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_QPI | FEATURE_4BA, + .tested = TEST_UNTESTED, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, /*FIXME: opcode is supported but check for each die is required, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + }*/ + }, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {1700, 1950}, + }, -- To view, visit https://review.coreboot.org/c/flashrom/+/90583?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I91a5a2a54888999c01af798dd1e47e99bbf8700d Gerrit-Change-Number: 90583 Gerrit-PatchSet: 1 Gerrit-Owner: Eugene Goubine <egoubine(a)winbond.com>

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[M] Change in flashrom[main]: doc: Update Recent development doc
by Anastasia Klimchuk (Code Review) Dec. 20, 2025

Dec. 20, 2025

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/90545?usp=email ) Change subject: doc: Update Recent development doc ...................................................................... doc: Update Recent development doc End of year update Change-Id: I146a99302b4bf0900faf374b0d92cd30eaf10abc Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/90545 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M doc/release_notes/devel.rst 1 file changed, 63 insertions(+), 3 deletions(-) Approvals: Stefan Reinauer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/doc/release_notes/devel.rst b/doc/release_notes/devel.rst index 9e6f31d..20150b8 100644 --- a/doc/release_notes/devel.rst +++ b/doc/release_notes/devel.rst @@ -19,18 +19,53 @@ * Erasing generic SFDP chips was unreliable or could crash if the SFDP erase definitions were not in ascending order of sector sizes. + Eraseblocks definition detected from SFDP header are now sorted in ascending + order before proceeding further. + See https://review.coreboot.org/c/flashrom/+/90131 + To complete the bug fix, few more things are also added: + + * selfcheck function now runs over a chip definition that was constructed from the SFDP header. + This way we assert that definition is valid before starting any further operations with the chip. + + * Basic tests are added for sfdp probing flow. + + Added support ============= * Intel Wildcat Lake chipset * EN25QX128A + * MT25QU02G, MT25QL02G marked as tested * MT35XU02G + * MX25U12873F +* MX25R512F +* MX25R1035F +* MX25U12873F +* MX66U1G45G +* MX66L2G45G + * P25D80H + +* S25FL116K/S25FL216K marked as tested + * W35T02NW +* W35T02NW +* W25Q512JV_M +* W25Q80_V +* W25R256JW +* W77Q{16,32}JW +* W77Q{64,128}JW +* W77Q{64,128}JV +* W77Q{25,51,10}NW [#b1]_ +* W77T{25,51,10}NW [#b1]_ + +* XM25QU64C/XM25LU64C write-protect support + +.. [#b1] | Will also be updated later when multi-die support added New features ============ @@ -104,14 +139,20 @@ when ``--noverify`` is ignored, more details and disussion is here: https://ticket.coreboot.org/issues/605 -New programmers -=============== +Programmers updates +=================== -* Nvidia System Management Agent +* New programmer: Nvidia System Management Agent System Management Agent (SMA) programmer is a SoC which is working as a side band management on Nvidia server board. One of its functions is to flash firmware to other components. +* asm106x: Added device ID for IDE mode + + Some boards are configured as IDE controller (class 0x0101); others even + have a physical switch to select between IDE and AHCI. For IDE the + device ID is 0x0611. + libflashrom =========== @@ -142,3 +183,22 @@ Note that source files in directory ``subprojects/packagefiles/cmocka-1.1.5`` haven't been changed, and won't be. Those files are unpacked from cmocka wrap, so that's the exact copy from another project, and should stay as is. + +Misc updates +============ + +* tests: Add tests which run a chain of operations +* cli_classic.c: Print runtime measurement in seconds in debug +* Add guard for compare_region_with_dump() +* build: only add git describe for git checkouts +* pcidev.h: Extract pcidev declarations to a separate header +* doc: Add page to publish license info on the website +* sb600spi: Check if SPI BAR register has valid value +* spi.h: Move SPI declarations from chipdrivers.h to spi.h +* parallel.h: Extract parallel declarations to a separate header +* doc: Disable auto-conversion of -- to en-dash on html pages +* serial.h: Extract serial declarations to a separate header +* helpers_fileio.c: fix fsync() check (fix compilation issue for Android) +* flashchips: Add Spansion S25FL512S: pretty print status register 2 +* pcidev: support programmers that don't need the ROM BAR and use config space registers +* tests/spidriver.c: Fix Windows compilation (see also https://ticket.coreboot.org/issues/602) -- To view, visit https://review.coreboot.org/c/flashrom/+/90545?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I146a99302b4bf0900faf374b0d92cd30eaf10abc Gerrit-Change-Number: 90545 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in flashrom[main]: doc: Update Recent development doc
by Anastasia Klimchuk (Code Review) Dec. 20, 2025

Dec. 20, 2025

Attention is currently required from: Peter Marheine. Anastasia Klimchuk has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/90545?usp=email ) Change subject: doc: Update Recent development doc ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > This includes CB:90110 and CB:90524 so needs to be submitted after those two patches. Done -- To view, visit https://review.coreboot.org/c/flashrom/+/90545?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I146a99302b4bf0900faf374b0d92cd30eaf10abc Gerrit-Change-Number: 90545 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Sat, 20 Dec 2025 11:50:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[S] Change in flashrom[main]: flashchips: add support for W25Q01JV
by Jae Hyun Yoo (Code Review) Dec. 19, 2025

Dec. 19, 2025

Jae Hyun Yoo has abandoned this change. ( https://review.coreboot.org/c/flashrom/+/90543?usp=email ) Change subject: flashchips: add support for W25Q01JV ...................................................................... Abandoned Ah, I found that David has already submitted the same support via https://review.coreboot.org/c/flashrom/+/90106 I'm dropping this patch. Thank you! -- To view, visit https://review.coreboot.org/c/flashrom/+/90543?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Iac251e47969f16551803d5fede474f29d8120dcb Gerrit-Change-Number: 90543 Gerrit-PatchSet: 2 Gerrit-Owner: Jae Hyun Yoo <jae.yoo(a)oss.qualcomm.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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