November 2025 - flashrom-gerrit

Change in ...flashrom[master]: Add support for security register and SBULK command on Macronix chips
by vl_sk (Code Review) Jan. 13, 2026

Jan. 13, 2026

vl_sk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/32034 Change subject: Add support for security register and SBULK command on Macronix chips ...................................................................... Add support for security register and SBULK command on Macronix chips Signed-off-by: Vladimir Skokov <vl_sk(a)mail.ru> Change-Id: I6b3d7bd2625dec5fda7b85f421d40c49bbc528a6 --- M chipdrivers.h M flashchips.c M spi.h M spi25_statusreg.c 4 files changed, 78 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/32034/1 diff --git a/chipdrivers.h b/chipdrivers.h index 134ed26..54288cd 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -102,7 +102,9 @@ int spi_prettyprint_status_register_sst25(struct flashctx *flash); int spi_prettyprint_status_register_sst25vf016(struct flashctx *flash); int spi_prettyprint_status_register_sst25vf040b(struct flashctx *flash); +int spi_prettyprint_security_register_mx25(struct flashctx *flash); int spi_disable_blockprotect_sst26_global_unprotect(struct flashctx *flash); +int spi_disable_blockprotect_mx25_global_unprotect(struct flashctx *flash); /* sfdp.c */ int probe_spi_sfdp(struct flashctx *flash); diff --git a/flashchips.c b/flashchips.c index d85ea74..2c662e9 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8555,9 +8555,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register and SBLK/SBULK; MX25L12835F: configuration register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) supported */ .voltage = {2700, 3600}, @@ -8604,9 +8603,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register and SBLK/SBULK; MX25L12835F: configuration register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) supported */ .voltage = {2700, 3600}, @@ -8693,9 +8691,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8734,9 +8731,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8776,9 +8772,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8818,9 +8813,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8858,9 +8852,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, /* Multi I/O supported */ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8907,9 +8900,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, /* Multi I/O supported */ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, diff --git a/spi.h b/spi.h index 422e6a0..456d894 100644 --- a/spi.h +++ b/spi.h @@ -170,6 +170,15 @@ From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ #define JEDEC_BYTE_PROGRAM_4BA 0x12 +/* Read Security Register */ +#define JEDEC_RDSCUR 0x2B +#define JEDEC_RDSCUR_OUTSIZE 0x01 +#define JEDEC_RDSCUR_INSIZE 0x01 + +/* Do GBULK (gang block unlock) */ +#define JEDEC_GBULK 0x98 +#define JEDEC_GBULK_OUTSIZE 0x01 + /* Error codes */ #define SPI_GENERIC_ERROR -1 #define SPI_INVALID_OPCODE -2 diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 4cf7023..4cdf800 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -237,6 +237,28 @@ return spi_disable_blockprotect_generic(flash, 0x7C, 1 << 7, 0, 0xFF); } +int spi_disable_blockprotect_mx25_global_unprotect(struct flashctx *flash) +{ + static const unsigned char cmd[JEDEC_GBULK_OUTSIZE] = { JEDEC_GBULK }; + int ret; + + ret = spi_write_enable(flash); + if (ret) { + msg_cerr("Set WREN failed!\n"); + return -1; + } + + /* Send GBULK cmd to device. */ + ret = spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); + if (ret) { + msg_cerr("GBULK failed!\n"); + return -1; + } + + /* Disable standard blockprotect */ + return spi_disable_blockprotect_bp3_srwd(flash); +} + static void spi_prettyprint_status_register_hex(uint8_t status) { msg_cdbg("Chip status register is 0x%02x.\n", status); @@ -751,3 +773,32 @@ msg_cdbg("Resulting block protection : %s\n", bpt[(status & 0x1c) >> 2]); return 0; } + +/* === Macronix chips with Security Register === */ + +int spi_read_security_register(struct flashctx *flash) +{ + static const unsigned char cmd[JEDEC_RDSCUR_OUTSIZE] = { JEDEC_RDSCUR }; + unsigned char readarr[JEDEC_RDSCUR_INSIZE]; + int ret; + + ret = spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr); + if (ret) { + msg_cerr("RDSCUR failed!\n"); + return 0; + } + + return readarr[0]; +} + +int spi_prettyprint_security_register_mx25(struct flashctx *flash) +{ + int security_register = spi_read_security_register(flash); + int wpsel = !!(security_register & (1 << 7)); + + msg_cdbg("Chip security register: 0x%02X\n", security_register); + msg_cdbg("\tWPSEL is %s\n", wpsel ? "ON" : "OFF"); + + /* Print standard blockprotect info */ + return spi_prettyprint_status_register_bp3_srwd(flash); +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/flashrom/+/32034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6b3d7bd2625dec5fda7b85f421d40c49bbc528a6 Gerrit-Change-Number: 32034 Gerrit-PatchSet: 1 Gerrit-Owner: vl_sk Gerrit-MessageType: newchange

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[M] Change in flashrom[main]: flashchips: add Macronix MX66U1G45G
by Ting Kai Chen (Code Review) Nov. 29, 2025

Nov. 29, 2025

Ting Kai Chen has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/90271?usp=email ) Change subject: flashchips: add Macronix MX66U1G45G ...................................................................... flashchips: add Macronix MX66U1G45G Adds support for the Macronix MX66U1G45G flashchip [0]. Tested probe, read, write, and erase via nv_sma_spi [1]. [0]: https://www.macronix.com/Lists/Datasheet/Attachments/8742/MX66U1G45G,%201.8… [1]: https://paste.flashrom.org/view.php?id=3790 Co-Developed-by: Ting-Kai Chen <tingkaic(a)nvidia.com> Co-Developed-by: William Davy <wdavy(a)nvidia.com> Co-Developed-by: Harry Sung <harrys(a)nvidia.com> Change-Id: Id648da76148c7b091cbd1f39ba0c7f8983935f60 Signed-off-by: Ting-Kai Chen <tingkaic(a)nvidia.com> --- M flashchips/macronix.c M include/flashchips.h 2 files changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/71/90271/1 diff --git a/flashchips/macronix.c b/flashchips/macronix.c index fb16c7a..8d7b3c5 100644 --- a/flashchips/macronix.c +++ b/flashchips/macronix.c @@ -2817,6 +2817,55 @@ { .vendor = "Macronix", + .name = "MX66U1G45G", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX66U1G45G, + .total_size = 131072, + .page_size = 256, + /* OTP: 512B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = SPI_BLOCK_ERASE_21, + }, { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 4096} }, + .block_erase = SPI_BLOCK_ERASE_5C, + }, { + .eraseblocks = { {32 * 1024, 4096} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = SPI_BLOCK_ERASE_DC, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {128 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {128 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + /* TODO: security register and SBLK/SBULK, configuration register */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit6 is quad enable */ + .unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Macronix", .name = "MX77L25650F", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, diff --git a/include/flashchips.h b/include/flashchips.h index 8342138..353694a 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -528,6 +528,7 @@ #define MACRONIX_MX25L1635E 0x2515 /* MX25L1635{E} */ #define MACRONIX_MX66L51235F 0x201a /* MX66L51235F, MX25L51245G */ #define MACRONIX_MX66L1G45G 0x201b /* MX66L1G45G */ +#define MACRONIX_MX66U1G45G 0x253b /* MX66U1G45G */ #define MACRONIX_MX25V4035F 0x2313 #define MACRONIX_MX25V8035F 0x2314 #define MACRONIX_MX25V1635F 0x2315 /* MX25V1636E */ -- To view, visit https://review.coreboot.org/c/flashrom/+/90271?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Id648da76148c7b091cbd1f39ba0c7f8983935f60 Gerrit-Change-Number: 90271 Gerrit-PatchSet: 1 Gerrit-Owner: Ting Kai Chen <tingkaic(a)nvidia.com>

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[L] Change in flashrom[main]: flashchips: Add W77Q{16,32}JW, W77Q{64,128}JW, W77Q{64,128}JV, W77Q{6...
by Anastasia Klimchuk (Code Review) Nov. 29, 2025

Nov. 29, 2025

Attention is currently required from: Eugene Goubine, Nikolai Artemiev, Stefan Reinauer. Anastasia Klimchuk has posted comments on this change by Eugene Goubine. ( https://review.coreboot.org/c/flashrom/+/90080?usp=email ) Change subject: flashchips: Add W77Q{16,32}JW, W77Q{64,128}JW, W77Q{64,128}JV, W77Q{64,128}NW, W77{Q,T}{25,51,01}NW W77Q secure chips are drop and replace to W25Q series. Adding support + testing via ch341a_api: probe> flashrom -p ch341a_spi erase/write/verify> flashrom -p ch341a_spi -c W77Q51NWD -w test_pattern_full.bin Still untested are {W77Q16JW, W77Q128NW, W77Q01NWQ, W77T{25,51,01}NW https://paste.flashrom.org/view.php?id=3785 ...................................................................... Patch Set 1: (3 comments) Patchset: PS1: > Sure I will send them via mail ( is this one I get notifications from ?) or another one In many cases you can see an email when you hover over person's name in the top-left corner (for example I am in reviewers section). For me you can send to aklm at flashrom.org or aklm at chromium.org The notifications about the patch progress are sent from the Gerrit (which is our code review tool), usually you don't reply to those - you reply on the patch , here. For the datasheet, if they are available to public you can add link to commit message. If not then maybe you can send by email to reviewers of this patch, or at least to me. File flashchips/winbond.c: https://review.coreboot.org/c/flashrom/+/90080/comment/2cac6096_31b8aa3d?us… : PS1, Line 3221: {.probe = OK, .read = OK, .erase = OK, .write = OK, .wp = NA} > actually wp feature is not NOT TESTED as in TEST_OK_PREW , but NOT AVAILABLE. […] I see, yes you are right then - you can use unfolded value. I was confused because you added feature flags FEATURE_WRSR2, FEATURE_WRSR3, FEATURE_WRSR_EXT2, and these ones are usually used by flashrom to read write-protect register bits (from status2 and 3). But I haven't seen the datasheet, so that was my guess. But in any case, I think only one of FEATURE_WRSR2 or FEATURE_WRSR_EXT2 is needed, not both? Current implementation of `spi_write_register` treats FEATURE_WRSR2/3 as a priority and if it's set, the EXT one is not needed. https://review.coreboot.org/c/flashrom/+/90080/comment/98ad72d1_05f01984?us… : PS1, Line 3379: opcode is supported but check for each die is required, > I am not aware how this works in other chips so do not know if I should introduce specific winbond erase chip flow or make generic flow Hopefully I will be able to tell you when I read the datasheet! but in any case - multi-die support is a new feature which is being introduced right now, so what I can say: 1) when you split into multiple commits, keep the multi-die ones last - then maybe by that time CB:90105 will be submitted and you will be able to check if it works 2) I also understand that CB:90105 was tested for W25 series and you are adding W77, so it may need more support? 3) as for the other chip: multi-die support is a new feature and the that one is the first patch to add support, and for Winbond! :) before that, I saw multi-dies in the datasheet from other chips, but there was no special opcodes required to select dies, probably it was handled by the chip -- To view, visit https://review.coreboot.org/c/flashrom/+/90080?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Iaac6a44b95a0b2db45745cbf11ee448cd5590b27 Gerrit-Change-Number: 90080 Gerrit-PatchSet: 1 Gerrit-Owner: Eugene Goubine <egoubine(a)winbond.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Eugene Goubine <egoubine(a)winbond.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Sat, 29 Nov 2025 09:13:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eugene Goubine <egoubine(a)winbond.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[M] Change in flashrom[main]: spi25: add dual die support
by David Schneider (Code Review) Nov. 28, 2025

Nov. 28, 2025

Attention is currently required from: Anastasia Klimchuk, Peter Marheine. David Schneider has posted comments on this change by David Schneider. ( https://review.coreboot.org/c/flashrom/+/90105?usp=email ) Change subject: spi25: add dual die support ...................................................................... Patch Set 5: (1 comment) File spi25.c: https://review.coreboot.org/c/flashrom/+/90105/comment/5fbdbc49_9a0834b3?us… : PS5, Line 401: if (flash->chip->feature_bits & FEATURE_DUAL_DIE_C2) { > Duplicating the feature check between this and the previous function seems like a little bit of a sm […] I respectfully disagree. spi_select_die is purely policy: it establishes that the die needs to be selected and then issues the request. As more feature bits are added, these bits will be OR'd together into a single check -- it doesn't care how the die select command is executed, especially not implementation details like the opcode. spi_write_die_select on the other hand is purely executive -- it takes the request and determines the appropriate command to write given the feature set. Here and only here is where the opcode and command structure should determined. Moving opcode selection into spi_select_die splits the executive part of the code between two functions, and won't work in the rare case that two chips use the same opcode but with different data structures. -- To view, visit https://review.coreboot.org/c/flashrom/+/90105?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I60ee5ff12f67f4e941db3df109eb0f8d6c538dff Gerrit-Change-Number: 90105 Gerrit-PatchSet: 5 Gerrit-Owner: David Schneider <dnschneid(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Sat, 29 Nov 2025 00:56:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Peter Marheine <pmarheine(a)chromium.org>

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[M] Change in flashrom[main]: Enclustra Mercurial XU5: Add code to make SoC/FPGA dormant
by Anastasia Klimchuk (Code Review) Nov. 28, 2025

Nov. 28, 2025

Attention is currently required from: Andrew Lunn, Peter Marheine. Anastasia Klimchuk has posted comments on this change by Andrew Lunn. ( https://review.coreboot.org/c/flashrom/+/89896?usp=email ) Change subject: Enclustra Mercurial XU5: Add code to make SoC/FPGA dormant ...................................................................... Patch Set 3: (7 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/89896/comment/cf9aa7af_b6be9283?us… : PS1, Line 7: quiescent > How about "Add code to make the Soc/FPGA go dormant" Yes this is better, thank you! https://review.coreboot.org/c/flashrom/+/89896/comment/dd482348_98e23bf2?us… : PS1, Line 26: Add a little bit of infrastructure to allow more complex : initialization and shutdown. > I would say the ft2232_programmer_type and how it is handled is infrastructure. […] Alright, lets keep infra. I thought of servers and cables - but there is also a wider meaning for this word. If everyone understands the commit message, it's fine. Commit Message: https://review.coreboot.org/c/flashrom/+/89896/comment/644947fb_7c735fc6?us… : PS3, Line 20: enclustra This one left with the old name, I think here better use the param value (enclustra-xu5) File ft2232_spi.c: https://review.coreboot.org/c/flashrom/+/89896/comment/96183418_f4f2a33f?us… : PS1, Line 83: enum ft2232_programmer_type { : PROGRAMMER_TYPE_UNDEFINED = 0, : PROGRAMMER_TYPE_ENCLUSTRA : }; > Layering is an interesting idea, but i have problems seeing how it would work. […] I don't fully understand the idea of layering, I think I half-understand hooking the setup/teardown functions - but the names are too generic? are these just example names? But I want to understand Peter's idea - even that I am thinking maybe the large refactoring better be in a separate commit? this patch is adding support for new device, which is already a big thing by itself. File ft2232_spi.c: https://review.coreboot.org/c/flashrom/+/89896/comment/4b23298f_33d6038b?us… : PS3, Line 6: * You will need to rebase at some point, because we have just converted license and copyright info to spdx tags. And then, if you want you can add your copyright line here: you are adding a new feature to the programmer. I am saying "if you want" because sometimes people don't want, which is also fine. Up to you. https://review.coreboot.org/c/flashrom/+/89896/comment/c9e83351_2d4532e8?us… : PS3, Line 91: enum ft2232_programmer_type { : PROGRAMMER_TYPE_UNDEFINED = 0, : PROGRAMMER_TYPE_ENCLUSTRA_XU5 : }; I finally managed to formulate what was confusing to me with this enum: the naming (of enum and values), so with different naming it might be fine. Specifically: there is already a programmer param `type`, and this enum has suffix `_programmer_type`, so first natural thought is that this is the same type, same values. But it is not - the values are different. Moreover, the command line param has 18 values, one of them enclustra-xu5. And the enum has just two values - why all of the 17 param values correspond to undefined in the enum? I tried to come up with different names, but I don't know which one of them makes better sense (or maybe you have a better idea!) some of my ideas prog_subtype prog_custom_init_shutdown_subtype prog_extra_init_shutdown_subtype prog_extra_init_shutdown_required prog_board_interaction_type prog_board_communication_type Then the first value of enum can be something like NO_SUBTYPE, NO_CUSTOM_INIT_SHUTDOWN, NO_INTERACTION (just not to use "unknown" or "undefined") anything to avoid saying "programmer type" because this is what command line param already is what do you think? https://review.coreboot.org/c/flashrom/+/89896/comment/0eeecfdf_05107db9?us… : PS3, Line 776: Enclustra A small comment, but I think here the message can be specific and say "Enclustra XU5: ..." (and same in other messages here and on shutdown) -- To view, visit https://review.coreboot.org/c/flashrom/+/89896?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I0238387cff6eb581c0c5f28cda54544d9405deb2 Gerrit-Change-Number: 89896 Gerrit-PatchSet: 3 Gerrit-Owner: Andrew Lunn <andrew(a)lunn.ch> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andrew Lunn <andrew(a)lunn.ch> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Fri, 28 Nov 2025 09:01:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Andrew Lunn <andrew(a)lunn.ch> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Comment-In-Reply-To: Peter Marheine <pmarheine(a)chromium.org>

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[M] Change in flashrom[main]: spi25: add dual die support
by Peter Marheine (Code Review) Nov. 27, 2025

Nov. 27, 2025

Attention is currently required from: Anastasia Klimchuk, David Schneider. Peter Marheine has posted comments on this change by David Schneider. ( https://review.coreboot.org/c/flashrom/+/90105?usp=email ) Change subject: spi25: add dual die support ...................................................................... Patch Set 5: (1 comment) File spi25.c: https://review.coreboot.org/c/flashrom/+/90105/comment/941064d2_eb4f18f0?us… : PS5, Line 401: if (flash->chip->feature_bits & FEATURE_DUAL_DIE_C2) { Duplicating the feature check between this and the previous function seems like a little bit of a smell. The feature flag tells you how to compute the die to select, whereas `spi_write_die_select` needs to know how to format the command. I'd prefer to pass the opcode to `spi_write_die_select`, so then the feature clearly has a 1:1 mapping to an opcode and `spi_write_die_select` can use the opcode alone to format the command correctly. -- To view, visit https://review.coreboot.org/c/flashrom/+/90105?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I60ee5ff12f67f4e941db3df109eb0f8d6c538dff Gerrit-Change-Number: 90105 Gerrit-PatchSet: 5 Gerrit-Owner: David Schneider <dnschneid(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Schneider <dnschneid(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Fri, 28 Nov 2025 04:30:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in flashrom[main]: flashchips/xmc.c: Add reg_bits for XM25QU64C/XM25LU64C
by Anastasia Klimchuk (Code Review) Nov. 27, 2025

Nov. 27, 2025

Attention is currently required from: Hsuan-ting Chen, Nikolai Artemiev, Stefan Reinauer. Anastasia Klimchuk has posted comments on this change by Hsuan-ting Chen. ( https://review.coreboot.org/c/flashrom/+/90178?usp=email ) Change subject: flashchips/xmc.c: Add reg_bits for XM25QU64C/XM25LU64C ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/90178?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I0cb0de3521803662b1198fcbe3028cf06f03c5cb Gerrit-Change-Number: 90178 Gerrit-PatchSet: 2 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Fri, 28 Nov 2025 03:12:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in flashrom[main]: flashchips/xmc.c: Add reg_bits for XM25QU64C/XM25LU64C
by Hsuan-ting Chen (Code Review) Nov. 27, 2025

Nov. 27, 2025

Attention is currently required from: Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer. Hsuan-ting Chen has posted comments on this change by Hsuan-ting Chen. ( https://review.coreboot.org/c/flashrom/+/90178?usp=email ) Change subject: flashchips/xmc.c: Add reg_bits for XM25QU64C/XM25LU64C ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/90178/comment/c1d18e88_0f0c436f?us… : PS1, Line 9: The register : definitions are same as XM25QH128C. > Why are you mentioning XM25QH128C in this commit message? This is a different model which is not upd […] Just because I initially copied the bits from XM25QH128C. But I'll remove that if that causes the confusion. -- To view, visit https://review.coreboot.org/c/flashrom/+/90178?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I0cb0de3521803662b1198fcbe3028cf06f03c5cb Gerrit-Change-Number: 90178 Gerrit-PatchSet: 2 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Fri, 28 Nov 2025 02:54:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[S] Change in flashrom[main]: flashchips/xmc.c: Add reg_bits for XM25QU64C/XM25LU64C
by Hsuan-ting Chen (Code Review) Nov. 27, 2025

Nov. 27, 2025

Attention is currently required from: Hsuan-ting Chen, Nikolai Artemiev, Stefan Reinauer. Hello Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/90178?usp=email to look at the new patch set (#2). Change subject: flashchips/xmc.c: Add reg_bits for XM25QU64C/XM25LU64C ...................................................................... flashchips/xmc.c: Add reg_bits for XM25QU64C/XM25LU64C Add reg_bits for XM25QU64C/XM25LU64C as per the datasheet. Datasheet: https://www.xmcwh.com/uploads/231/XM25QU64C.pdf Datasheet: https://www.xmcwh.com/uploads/954/XM25LU64C_V1.5.pdf BUG=b:447014726 TEST=datasheet only Change-Id: I0cb0de3521803662b1198fcbe3028cf06f03c5cb Signed-off-by: Hsuan Ting Chen <roccochen(a)google.com> --- M flashchips/xmc.c 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/90178/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/90178?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I0cb0de3521803662b1198fcbe3028cf06f03c5cb Gerrit-Change-Number: 90178 Gerrit-PatchSet: 2 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com>

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[S] Change in flashrom[main]: flashchips/xmc.c: Add reg_bits for XM25QU64C/XM25LU64C
by Anastasia Klimchuk (Code Review) Nov. 27, 2025

Nov. 27, 2025

Attention is currently required from: Hsuan-ting Chen, Nikolai Artemiev, Stefan Reinauer. Anastasia Klimchuk has posted comments on this change by Hsuan-ting Chen. ( https://review.coreboot.org/c/flashrom/+/90178?usp=email ) Change subject: flashchips/xmc.c: Add reg_bits for XM25QU64C/XM25LU64C ...................................................................... Patch Set 1: (2 comments) Patchset: PS1: I checked the reg bits, all good, thanks for adding support! I have only one question, about commit message Commit Message: https://review.coreboot.org/c/flashrom/+/90178/comment/b18f49ec_ed560caf?us… : PS1, Line 9: The register : definitions are same as XM25QH128C. Why are you mentioning XM25QH128C in this commit message? This is a different model which is not updated in this commit? maybe remove this sentence -- To view, visit https://review.coreboot.org/c/flashrom/+/90178?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I0cb0de3521803662b1198fcbe3028cf06f03c5cb Gerrit-Change-Number: 90178 Gerrit-PatchSet: 1 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Fri, 28 Nov 2025 02:35:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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