October 2025 - flashrom-gerrit

Change in ...flashrom[master]: Add support for security register and SBULK command on Macronix chips
by vl_sk (Code Review) Jan. 14, 2026

Jan. 14, 2026

vl_sk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/32034 Change subject: Add support for security register and SBULK command on Macronix chips ...................................................................... Add support for security register and SBULK command on Macronix chips Signed-off-by: Vladimir Skokov <vl_sk(a)mail.ru> Change-Id: I6b3d7bd2625dec5fda7b85f421d40c49bbc528a6 --- M chipdrivers.h M flashchips.c M spi.h M spi25_statusreg.c 4 files changed, 78 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/32034/1 diff --git a/chipdrivers.h b/chipdrivers.h index 134ed26..54288cd 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -102,7 +102,9 @@ int spi_prettyprint_status_register_sst25(struct flashctx *flash); int spi_prettyprint_status_register_sst25vf016(struct flashctx *flash); int spi_prettyprint_status_register_sst25vf040b(struct flashctx *flash); +int spi_prettyprint_security_register_mx25(struct flashctx *flash); int spi_disable_blockprotect_sst26_global_unprotect(struct flashctx *flash); +int spi_disable_blockprotect_mx25_global_unprotect(struct flashctx *flash); /* sfdp.c */ int probe_spi_sfdp(struct flashctx *flash); diff --git a/flashchips.c b/flashchips.c index d85ea74..2c662e9 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8555,9 +8555,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register and SBLK/SBULK; MX25L12835F: configuration register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) supported */ .voltage = {2700, 3600}, @@ -8604,9 +8603,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register and SBLK/SBULK; MX25L12835F: configuration register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) supported */ .voltage = {2700, 3600}, @@ -8693,9 +8691,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8734,9 +8731,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8776,9 +8772,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8818,9 +8813,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8858,9 +8852,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, /* Multi I/O supported */ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8907,9 +8900,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, /* Multi I/O supported */ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, diff --git a/spi.h b/spi.h index 422e6a0..456d894 100644 --- a/spi.h +++ b/spi.h @@ -170,6 +170,15 @@ From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ #define JEDEC_BYTE_PROGRAM_4BA 0x12 +/* Read Security Register */ +#define JEDEC_RDSCUR 0x2B +#define JEDEC_RDSCUR_OUTSIZE 0x01 +#define JEDEC_RDSCUR_INSIZE 0x01 + +/* Do GBULK (gang block unlock) */ +#define JEDEC_GBULK 0x98 +#define JEDEC_GBULK_OUTSIZE 0x01 + /* Error codes */ #define SPI_GENERIC_ERROR -1 #define SPI_INVALID_OPCODE -2 diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 4cf7023..4cdf800 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -237,6 +237,28 @@ return spi_disable_blockprotect_generic(flash, 0x7C, 1 << 7, 0, 0xFF); } +int spi_disable_blockprotect_mx25_global_unprotect(struct flashctx *flash) +{ + static const unsigned char cmd[JEDEC_GBULK_OUTSIZE] = { JEDEC_GBULK }; + int ret; + + ret = spi_write_enable(flash); + if (ret) { + msg_cerr("Set WREN failed!\n"); + return -1; + } + + /* Send GBULK cmd to device. */ + ret = spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); + if (ret) { + msg_cerr("GBULK failed!\n"); + return -1; + } + + /* Disable standard blockprotect */ + return spi_disable_blockprotect_bp3_srwd(flash); +} + static void spi_prettyprint_status_register_hex(uint8_t status) { msg_cdbg("Chip status register is 0x%02x.\n", status); @@ -751,3 +773,32 @@ msg_cdbg("Resulting block protection : %s\n", bpt[(status & 0x1c) >> 2]); return 0; } + +/* === Macronix chips with Security Register === */ + +int spi_read_security_register(struct flashctx *flash) +{ + static const unsigned char cmd[JEDEC_RDSCUR_OUTSIZE] = { JEDEC_RDSCUR }; + unsigned char readarr[JEDEC_RDSCUR_INSIZE]; + int ret; + + ret = spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr); + if (ret) { + msg_cerr("RDSCUR failed!\n"); + return 0; + } + + return readarr[0]; +} + +int spi_prettyprint_security_register_mx25(struct flashctx *flash) +{ + int security_register = spi_read_security_register(flash); + int wpsel = !!(security_register & (1 << 7)); + + msg_cdbg("Chip security register: 0x%02X\n", security_register); + msg_cdbg("\tWPSEL is %s\n", wpsel ? "ON" : "OFF"); + + /* Print standard blockprotect info */ + return spi_prettyprint_status_register_bp3_srwd(flash); +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/flashrom/+/32034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6b3d7bd2625dec5fda7b85f421d40c49bbc528a6 Gerrit-Change-Number: 32034 Gerrit-PatchSet: 1 Gerrit-Owner: vl_sk Gerrit-MessageType: newchange

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[XS] Change in flashrom[main]: flashrom.c: use `finalize_flash_access` in case of failure
by Michał Iwanicki (Code Review) Oct. 31, 2025

Oct. 31, 2025

Attention is currently required from: Anastasia Klimchuk, Sergii Dmytruk. Michał Iwanicki has posted comments on this change by Michał Iwanicki. ( https://review.coreboot.org/c/flashrom/+/89684?usp=email ) Change subject: flashrom.c: use `finalize_flash_access` in case of failure ...................................................................... Patch Set 2: (1 comment) File flashrom.c: https://review.coreboot.org/c/flashrom/+/89684/comment/391079d3_60c85f07?us… : PS2, Line 1964: unmap_flash(flash); > Michal, what do you think of the plan? […] Not sure if I've done this correctly: https://review.coreboot.org/c/flashrom/+/89852 Also, I won't be available until around November 12th -- To view, visit https://review.coreboot.org/c/flashrom/+/89684?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I2e7be3f4f71447a1df532f02d1e45d20c253da5a Gerrit-Change-Number: 89684 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Iwanicki <michal.iwanicki(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Fri, 31 Oct 2025 12:42:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>

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[S] Change in flashrom[main]: flashrom.c: move `can_change_target_regions` check below wp unlock
by Michał Iwanicki (Code Review) Oct. 31, 2025

Oct. 31, 2025

Michał Iwanicki has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/89852?usp=email ) Change subject: flashrom.c: move `can_change_target_regions` check below wp unlock ...................................................................... flashrom.c: move `can_change_target_regions` check below wp unlock We should check if target regions are writable after trying to unlock them, not before. Tested on PC Engines APU4A: ``` $ ./flashrom -p internal -c W25Q64BV/W25Q64CV/W25Q64FV --wp-status (...) Protection range: start=0x00400000 length=0x00400000 (upper 1/2) Protection mode: hardware ``` Before this PR trying to write wp protected region: ``` $ ./flashrom -p internal -c W25Q64BV/W25Q64CV/W25Q64FV -l \ <(echo -e '00300000:00500000 wp\n') -i wp -w image.bin ``` Failed with: ``` cannot fully update wp region (0x300000..0x500000) due to chip's write-protection ``` With this change: ``` Using region: "wp". coreboot table found at 0x7ecc2000. Found chipset "AMD FCH". Enabling flash write... OK. Found Winbond flash chip "W25Q64BV/W25Q64CV/W25Q64FV" (8192 kB, SPI) mapped at physical address 0x00000000ff800000. Reading old flash chip contents... done. Updating flash chip contents... Region [0x00300000 - 0x00500000] is not sector aligned! Extending end boundaries by 0x00000fff bytes, from 0x00500000 -> 0x00500fff Erase/write done from 300000 to 500fff ``` Change-Id: I403d0a715d8efc03bb3f34ee73d718cc9e2aad59 Signed-off-by: Michał Iwanicki <michal.iwanicki(a)3mdeb.com> --- M flashrom.c 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/52/89852/1 diff --git a/flashrom.c b/flashrom.c index f6a5be8..3ee826d 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1900,13 +1900,6 @@ return 1; } - if ((write_it || erase_it) && !flash->flags.force) { - if (!can_change_target_regions(flash)) { - msg_cerr("At least one target region is not fully writable. Aborting.\n"); - return 1; - } - } - if (map_flash(flash) != 0) return 1; @@ -1930,6 +1923,13 @@ if (ret && bp_func) bp_func(flash); + if ((write_it || erase_it) && !flash->flags.force) { + if (!can_change_target_regions(flash)) { + msg_cerr("At least one target region is not fully writable. Aborting.\n"); + return 1; + } + } + flash->address_high_byte = -1; flash->in_4ba_mode = false; -- To view, visit https://review.coreboot.org/c/flashrom/+/89852?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I403d0a715d8efc03bb3f34ee73d718cc9e2aad59 Gerrit-Change-Number: 89852 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Iwanicki <michal.iwanicki(a)3mdeb.com>

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[XS] Change in flashrom[main]: flashrom.c: use `finalize_flash_access` in case of failure
by Anastasia Klimchuk (Code Review) Oct. 31, 2025

Oct. 31, 2025

Attention is currently required from: Michał Iwanicki. Anastasia Klimchuk has posted comments on this change by Michał Iwanicki. ( https://review.coreboot.org/c/flashrom/+/89684?usp=email ) Change subject: flashrom.c: use `finalize_flash_access` in case of failure ...................................................................... Patch Set 2: (1 comment) File flashrom.c: https://review.coreboot.org/c/flashrom/+/89684/comment/d77c4467_30a2d969?us… : PS2, Line 1964: unmap_flash(flash); > I made a chain locally, […] Michal, what do you think of the plan? If we chain the 3 patches together, at the end they all can be submitted in order. I am making progress with CB:89603 (or at least, I fixed all the comments so far). Would you be able to make a copy of CB:89689 and put on top of this? I am really sorry that you have to do it again :( I understand that CB:89689 was fixing a bug, and of course I want it to be fixed. Thank you! Just in case, if you are busy I can make a copy of CB:89689 ? I don't know because you haven't responded. -- To view, visit https://review.coreboot.org/c/flashrom/+/89684?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I2e7be3f4f71447a1df532f02d1e45d20c253da5a Gerrit-Change-Number: 89684 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Iwanicki <michal.iwanicki(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Iwanicki <michal.iwanicki(a)3mdeb.com> Gerrit-Comment-Date: Fri, 31 Oct 2025 11:52:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>

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[L] Change in flashrom[main]: libflashrom: Add flashrom_create_context to create and init context
by Anastasia Klimchuk (Code Review) Oct. 31, 2025

Oct. 31, 2025

Attention is currently required from: Peter Marheine, Sergii Dmytruk. Anastasia Klimchuk has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/89603?usp=email ) Change subject: libflashrom: Add flashrom_create_context to create and init context ...................................................................... Patch Set 12: (1 comment) File tests/external_client.c: https://review.coreboot.org/c/flashrom/+/89603/comment/4c76bf99_96175ba3?us… : PS11, Line 21: #if CONFIG_DUMMY == 1 > If we really want to enforce public API only, this is set by the flashrom build system and unavailab […] This was very silly of me, thank you so much for catching! I thought why not to check the supported programmers in official way - libflashrom has a api for this! :) I added the check. The test does not fail when dummy is not enabled. This is needed for Jenkins run, because it does different runs with various combinations of programmers enabled/disabled. That's why all tests check if their programmer is enabled, and if not then skip. -- To view, visit https://review.coreboot.org/c/flashrom/+/89603?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I483f6cabb2b4ed27e0ee10bf621ae1bddb1fc9f3 Gerrit-Change-Number: 89603 Gerrit-PatchSet: 12 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Fri, 31 Oct 2025 09:40:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Peter Marheine <pmarheine(a)chromium.org>

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[L] Change in flashrom[main]: libflashrom: Add flashrom_create_context to create and init context
by Anastasia Klimchuk (Code Review) Oct. 31, 2025

Oct. 31, 2025

Attention is currently required from: Anastasia Klimchuk, Sergii Dmytruk. Hello Peter Marheine, Sergii Dmytruk, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/89603?usp=email to look at the new patch set (#12). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: libflashrom: Add flashrom_create_context to create and init context ...................................................................... libflashrom: Add flashrom_create_context to create and init context flashrom_create_context does create and all initialisations needed for flash context. The real life usage of flashrom_flash_probe_v2 discovered the issue: error: variable 'flashctx' has initializer but incomplete type error: storage size of 'flashctx' isn't known flashrom_create_context fixes this, it would need to be called prior to any other api calls that require flash context. The patch also adds test which runs as external client for libflashrom. The test runs in a separate test executable, so that it does not use flashrom source code but instead uses libflashrom as a library. It is also an example how to use libflashrom api. Change-Id: I483f6cabb2b4ed27e0ee10bf621ae1bddb1fc9f3 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M cli_classic.c M doc/release_notes/devel.rst M include/libflashrom.h M libflashrom.c M libflashrom.map M meson.build A tests/client_tests.c A tests/client_tests.h M tests/dummyflasher.c A tests/external_client.c M tests/libflashrom.c M tests/lifecycle.c M tests/meson.build 13 files changed, 263 insertions(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/03/89603/12 -- To view, visit https://review.coreboot.org/c/flashrom/+/89603?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I483f6cabb2b4ed27e0ee10bf621ae1bddb1fc9f3 Gerrit-Change-Number: 89603 Gerrit-PatchSet: 12 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>

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[M] Change in flashrom[main]: flashchips: Add MT35XU02G
by Anastasia Klimchuk (Code Review) Oct. 31, 2025

Oct. 31, 2025

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/89686?usp=email ) Change subject: flashchips: Add MT35XU02G ...................................................................... flashchips: Add MT35XU02G Add initial support for Micron MT35XU02G. Tested probe, read, write, and erase via linux_spi [0]. [0]: https://paste.flashrom.org/view.php?id=3778 Change-Id: I28eb0ce202b6e45ab3a72dca07f2f8c3b4cfb1b2 Signed-off-by: Jacob Zarnstorff <jacobzarnstorff(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/89686 Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-by: Vincent Fazio <vfazio(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M flashchips/micron.c M include/flashchips.h 2 files changed, 55 insertions(+), 0 deletions(-) Approvals: Vincent Fazio: Looks good to me, but someone else must approve build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/flashchips/micron.c b/flashchips/micron.c index cee17ba..68cbff7 100644 --- a/flashchips/micron.c +++ b/flashchips/micron.c @@ -476,3 +476,55 @@ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1700, 2000}, }, + + { + .vendor = "Micron", + .name = "MT35XU02G", /* U = 1.8V, uniform 128KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = MICRON_ID, + .model_id = MICRON_MT35XU02GCBA, + .total_size = 256 * 1024, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 65536} }, + .block_erase = SPI_BLOCK_ERASE_21, + }, { + .eraseblocks = { {4 * 1024, 65536} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 8192} }, + .block_erase = SPI_BLOCK_ERASE_5C, + }, { + .eraseblocks = { {32 * 1024, 8192} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {128 * 1024, 2048} }, + .block_erase = SPI_BLOCK_ERASE_DC, + }, { + .eraseblocks = { {128 * 1024, 2048} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {65536 * 1024, 4} }, + .block_erase = SPI_BLOCK_ERASE_C4, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_N25Q, /* TODO: config, lock, flag regs */ + .unlock = SPI_DISABLE_BLOCKPROTECT_N25Q, /* TODO: per 128kB sector lock registers */ + .write = SPI_CHIP_WRITE256, /* Multi I/O supported */ + .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 6, RW}}, + .tb = {STATUS1, 5, RW}, + }, + }, diff --git a/include/flashchips.h b/include/flashchips.h index 2e5b07a..8380f87 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -604,6 +604,9 @@ #define MACRONIX_MX29SL800CB 0x6B /* Same as MX29SL802CB */ #define MACRONIX_MX29SL800CT 0xEA /* Same as MX29SL802CT */ +#define MICRON_ID 0x2C +#define MICRON_MT35XU02GCBA 0x5B1C + /* Nantronics Semiconductors is listed in JEP106AJ in bank 7, so it should have 6 continuation codes in front * of the manufacturer ID of 0xD5. http://www.nantronicssemi.com */ #define NANTRONICS_ID 0x7F7F7F7F7F7FD5 /* Nantronics */ -- To view, visit https://review.coreboot.org/c/flashrom/+/89686?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I28eb0ce202b6e45ab3a72dca07f2f8c3b4cfb1b2 Gerrit-Change-Number: 89686 Gerrit-PatchSet: 6 Gerrit-Owner: jacobzarnstorff(a)gmail.com Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Vincent Fazio <vfazio(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in flashrom[main]: libflashrom: Add flashrom_create_context to create and init context
by Peter Marheine (Code Review) Oct. 30, 2025

Oct. 30, 2025

Attention is currently required from: Anastasia Klimchuk, Sergii Dmytruk. Peter Marheine has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/89603?usp=email ) Change subject: libflashrom: Add flashrom_create_context to create and init context ...................................................................... Patch Set 11: (1 comment) File tests/external_client.c: https://review.coreboot.org/c/flashrom/+/89603/comment/dbd1b7a8_373101d1?us… : PS11, Line 21: #if CONFIG_DUMMY == 1 If we really want to enforce public API only, this is set by the flashrom build system and unavailable to library users. Is it possible to check the result of `flashrom_programmer_init` for programmer support? -- To view, visit https://review.coreboot.org/c/flashrom/+/89603?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I483f6cabb2b4ed27e0ee10bf621ae1bddb1fc9f3 Gerrit-Change-Number: 89603 Gerrit-PatchSet: 11 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Thu, 30 Oct 2025 23:53:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in flashrom[main]: libflashrom: Add flashrom_create_context to create and init context
by Anastasia Klimchuk (Code Review) Oct. 30, 2025

Oct. 30, 2025

Attention is currently required from: Peter Marheine, Sergii Dmytruk. Anastasia Klimchuk has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/89603?usp=email ) Change subject: libflashrom: Add flashrom_create_context to create and init context ...................................................................... Patch Set 11: (1 comment) File tests/external_client.c: https://review.coreboot.org/c/flashrom/+/89603/comment/01289b08_ffc3c8ce?us… : PS3, Line 11: #include "libflashrom.h" > Might want to add a comment (or even devise some kind of assertion?) that this test must not include […] I did the first part: added comments! I added comments everywhere (in both meson files and here in the c source), just in case. Also hopefully the name of the file gives a hint too. I don't want to use C++, but especially not C++ magic :( I thought maybe there is a way in meson to check whether executable contains a header, but I couldn't find. -- To view, visit https://review.coreboot.org/c/flashrom/+/89603?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I483f6cabb2b4ed27e0ee10bf621ae1bddb1fc9f3 Gerrit-Change-Number: 89603 Gerrit-PatchSet: 11 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Thu, 30 Oct 2025 04:15:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Peter Marheine <pmarheine(a)chromium.org>

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[L] Change in flashrom[main]: libflashrom: Add flashrom_create_context to create and init context
by Anastasia Klimchuk (Code Review) Oct. 30, 2025

Oct. 30, 2025

Attention is currently required from: Peter Marheine, Sergii Dmytruk. Hello Peter Marheine, Sergii Dmytruk, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/89603?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: libflashrom: Add flashrom_create_context to create and init context ...................................................................... libflashrom: Add flashrom_create_context to create and init context flashrom_create_context does create and all initialisations needed for flash context. The real life usage of flashrom_flash_probe_v2 discovered the issue: error: variable 'flashctx' has initializer but incomplete type error: storage size of 'flashctx' isn't known flashrom_create_context fixes this, it would need to be called prior to any other api calls that require flash context. The patch also adds test which runs as external client for libflashrom. The test runs in a separate test executable, so that it does not use flashrom source code but instead uses libflashrom as a library. It is also an example how to use libflashrom api. Change-Id: I483f6cabb2b4ed27e0ee10bf621ae1bddb1fc9f3 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M cli_classic.c M doc/release_notes/devel.rst M include/libflashrom.h M libflashrom.c M libflashrom.map M meson.build A tests/client_tests.c A tests/client_tests.h M tests/dummyflasher.c A tests/external_client.c M tests/libflashrom.c M tests/lifecycle.c M tests/meson.build 13 files changed, 246 insertions(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/03/89603/11 -- To view, visit https://review.coreboot.org/c/flashrom/+/89603?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I483f6cabb2b4ed27e0ee10bf621ae1bddb1fc9f3 Gerrit-Change-Number: 89603 Gerrit-PatchSet: 11 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org>

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