April 2020 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: dediprog: Fix SF600 4BA mode
by Patrick Rudolph (Code Review) Aug. 29, 2026

Aug. 29, 2026

Hello Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/flashrom/+/34629 to review the following change. Change subject: dediprog: Fix SF600 4BA mode ...................................................................... dediprog: Fix SF600 4BA mode Flash chips greater than 16MiB require 4BA mode support. Current master doesn't support such mode as the SF600 uses PROTOCOL_V3. Fix protocol version check to support 4BA on PROTOCOL_V3, too. Tested on SF600 V:7.2.45 Able to read and write "IS25WP256" (32768 kB, SPI). Change-Id: I2d3089693fbd2f8f7717a8f71be242be131ce707 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M dediprog.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/29/34629/1 diff --git a/dediprog.c b/dediprog.c index 3566109..add478d 100644 --- a/dediprog.c +++ b/dediprog.c @@ -1160,7 +1160,7 @@ if (dediprog_devicetype == DEV_SF100 && protocol() == PROTOCOL_V1) spi_master_dediprog.features &= ~SPI_MASTER_NO_4BA_MODES; - if (protocol() == PROTOCOL_V2) + if (protocol() >= PROTOCOL_V2) spi_master_dediprog.features |= SPI_MASTER_4BA; if (register_spi_master(&spi_master_dediprog) || dediprog_set_leds(LED_NONE)) -- To view, visit https://review.coreboot.org/c/flashrom/+/34629 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2d3089693fbd2f8f7717a8f71be242be131ce707 Gerrit-Change-Number: 34629 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 8

Change in flashrom[master]: Add support for continuous SPI reads
by Edward O'Callaghan (Code Review) Aug. 29, 2026

Aug. 29, 2026

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34584 ) Change subject: Add support for continuous SPI reads ...................................................................... Add support for continuous SPI reads Forward port the original patch from Duncan Laurie <dlaurie(a)chromium.org> in commit 06ffd5263892061c5ebf46e52b7878786cf2cece so that it fits for upstream consumption. This patch adds support for "unbounded reads" which are for continous reads to a SPI flash chip instead of reading in page size blocks. This speeds up the flash process over FTDI by quite a bit, testing the read of a 16MB part it goes from 2m11s to 0m15s. Change-Id: I804545aeb1b827ffdd41b21024fd618475e8263a Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M chipdrivers.h M flash.h M spi.c M spi25.c 4 files changed, 40 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/84/34584/1 diff --git a/chipdrivers.h b/chipdrivers.h index e380878..77e1943 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -55,6 +55,7 @@ int spi_chip_write_1(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int spi_nbyte_read(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); int spi_read_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize); +int spi_read_unbound(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize); int spi_write_chunked(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize); int spi_enter_4ba(struct flashctx *flash); int spi_exit_4ba(struct flashctx *flash); diff --git a/flash.h b/flash.h index b60a980..981f88b 100644 --- a/flash.h +++ b/flash.h @@ -143,6 +143,8 @@ #define ERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff) +#define FEATURE_UNBOUND_READ (1 << 19) + enum test_state { OK = 0, NT = 1, /* Not tested */ diff --git a/spi.c b/spi.c index 489baf3..23f4cfe 100644 --- a/spi.c +++ b/spi.c @@ -75,13 +75,18 @@ unsigned int len) { unsigned int max_data = flash->mst->spi.max_data_read; + int rc; if (max_data == MAX_DATA_UNSPECIFIED) { msg_perr("%s called, but SPI read chunk size not defined " "on this hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); return 1; } - return spi_read_chunked(flash, buf, start, len, max_data); + if (flash->feature_bits & FEATURE_UNBOUND_READ) + rc = spi_read_unbound(flash, buf, start, len, max_data); + else + rc = spi_read_chunked(flash, buf, start, len, max_data); + return rc; } int default_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len) diff --git a/spi25.c b/spi25.c index 2a1d492..3327110 100644 --- a/spi25.c +++ b/spi25.c @@ -659,6 +659,37 @@ } /* + * Read a part of the flash chip. + * Ignore pages and read the data continuously, the only bound is the chunksize. + */ +int spi_read_unbound(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize) +{ + int rc = 0; + unsigned int i; + + for (i = start; i < (start + len); i += chunksize) { + int chunk_status = 0; + unsigned int toread = min(chunksize, start + len - i); + + chunk_status = spi_nbyte_read(flash, i, buf + (i - start), toread); + if (chunk_status) { + if (ignore_error(chunk_status)) { + /* fill this chunk with 0xff bytes and + let caller know about the error */ + memset(buf + (i - start), 0xff, toread); + rc = chunk_status; + continue; + } else { + rc = chunk_status; + break; + } + } + } + + return rc; +} + +/* * Write a part of the flash chip. * FIXME: Use the chunk code from Michael Karcher instead. * Each page is written separately in chunks with a maximum size of chunksize. -- To view, visit https://review.coreboot.org/c/flashrom/+/34584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I804545aeb1b827ffdd41b21024fd618475e8263a Gerrit-Change-Number: 34584 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 5

Change in flashrom[master]: Automatic programmer driver writer
by Carl-Daniel Hailfinger (Code Review) Aug. 29, 2026

Aug. 29, 2026

Carl-Daniel Hailfinger has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/38488 ) Change subject: Automatic programmer driver writer ...................................................................... Automatic programmer driver writer Edit build_new_driver.sh and fill in the properties of the flashrom programmer driver you want to create. Then run ./build_new_driver.sh The driver skeleton will be created in $PROGRAMMERNAME.c.mine Modified versions of existing files will be created with extension .mine You can replace the original files with the modified versions by running for a in *; do test -f $a.mine && mv $a.mine $a; done If you want to use the newly generated skeleton $PROGRAMMERNAME.c.mine , run mv $PROGRAMMERNAME.c.mine $PROGRAMMERNAME.c WARNING: Please note that rerunning build_new_driver.sh will overwrite all *.mine files, but it won't touch $PROGRAMMERNAME.c . If something goes wrong, you can revert all files which look odd and run this script again. TODO: Stefan Tauner suggested to put the configuration into a separate file Change-Id: Icdcdcdcdcdcdcdcdcdcdcdcdcdcdcdcdcd000001 Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> --- M Makefile A build_new_driver.sh M flashrom.8.tmpl M flashrom.c M meson.build M meson_options.txt M programmer.h 7 files changed, 443 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/88/38488/1 diff --git a/Makefile b/Makefile index 7242b09..3149bb6 100644 --- a/Makefile +++ b/Makefile @@ -696,6 +696,8 @@ # Disable J-Link for now. CONFIG_JLINK_SPI ?= no +#PLACEHOLDER_NEWPROG_DEFAULTCONFIG + # Disable wiki printing by default. It is only useful if you have wiki access. CONFIG_PRINT_WIKI ?= no @@ -759,7 +761,9 @@ ifeq ($(CONFIG_OGP_SPI), yes) override CONFIG_BITBANG_SPI = yes else +#PLACEHOLDER_NEWPROG_BITBANGSPICONFIG1 CONFIG_BITBANG_SPI ?= no +#PLACEHOLDER_NEWPROG_BITBANGSPICONFIG2 endif endif endif @@ -996,6 +1000,8 @@ PROGRAMMER_OBJS += mstarddc_spi.o endif +#PLACEHOLDER_NEWPROG_COMPILERULE + ifeq ($(CONFIG_CH341A_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_CH341A_SPI=1' PROGRAMMER_OBJS += ch341a_spi.o diff --git a/build_new_driver.sh b/build_new_driver.sh new file mode 100644 index 0000000..d15e135 --- /dev/null +++ b/build_new_driver.sh @@ -0,0 +1,420 @@ +#!/bin/bash +# flashrom programmer driver skeleton builder. +# Copyright 2012,2020 Carl-Daniel Hailfinger +# Licensed under the GNU GPL v2 +# The license of the generated programmer driver is unrelated to the license +# of this script and can be specified below. + +# Fill in all info in the block below, and don't touch anything else. +# The data provided here is just an example. +# Name of the programmer. Needs to be an all-lowercase valid C identifier. +PROGRAMMERNAME=ezo +# Short description of the programmer. Please do not use / inside the name, it will break the sed expressions. +PROGRAMMERDESCR="EZo+Willem Programmer" +# Name of the programmer manufacturer. +PROGRAMMERMANUF="EZo and Willem" +# Website for the programmer. +PROGRAMMERURL="http://www.ezoflash.com/" +# Fill in your name here. +AUTHORNAME="Carl-Daniel Hailfinger" +# License version of the new programmer driver: 2 or 2+ (for 2+later) +LICENSE_GPL=2 +# Does the programmer need a map/unmap function? +HAVE_MAP=no +# Does the programmer have its own delay function? +HAVE_DELAY=no +# Does the programmer need some sort of direct hardware access? +NEED_PCI=yes +# Does the programmer need some sort of serial port access? +NEED_SERIAL=no +# Is the programmer a PCI device, USB device, or something else? +# You have to specify exactly one of PCI, USB, OTHER +DEVICETYPE=USB +# Note: Usually a programmer only has one of NEED_PARLPCFWH, NEED_SPI or NEED_SPI_BITBANG set to yes. +# Does the programmer use Parallel/LPC/FWH functionality? +NEED_PARLPCFWH=yes +# Which of PARALLEL/LPC/FWH buses does the programer use? FIXME: Explain how to handle multiple buses. +BUS_PARLPCFWH=LPC +# Does the programmer use SPI functionality without bitbanging? FIXME: Check if a SPI bitbanging driver with NEED_SPI=no generates useful code. +NEED_SPI=yes +# Does the programmer use the bitbanging SPI infrastructure? +NEED_SPI_BITBANG=yes + +# No user serviceable parts below. +unset LANG +unset LANGUAGE +unset LC_COLLATE +if test $LICENSE_GPL = 2; then + GPLV3EITHER= + GPLV3OR= +elif test $LICENSE_GPL = 2+; then + GPLV3EITHER="either" + GPLV3OR="\n * (at your option) any later version" +else + echo "Specified license can not be handled automatically" + exit 1 +fi +if test $HAVE_MAP = yes; then MAPNAME=$PROGRAMMERNAME; else MAPNAME=fallback; fi +if test $HAVE_DELAY = yes; then DELAYNAME=$PROGRAMMERNAME; else DELAYNAME=internal; fi +PROGRAMMERNAMECAPS=$(echo -n $PROGRAMMERNAME|tr "[[:lower:]]" "[[:upper:]]") +CONFIGNAME=CONFIG_$PROGRAMMERNAMECAPS +ENUMNAME=PROGRAMMER_$PROGRAMMERNAMECAPS +if test $NEED_PCI = yes; then NEEDS="NEED_PCI := yes\n"; fi +if test $NEED_SERIAL = yes; then NEEDS+="NEED_SERIAL := yes\n"; fi + +sed "s-^//PLACEHOLDER_NEWPROG_PROGRAMMER_ARRAY-\ +#if ${CONFIGNAME} == 1\n\ + {\n\ + .name = \"${PROGRAMMERNAME}\",\n\ +\0-" flashrom.c >flashrom.c.mine +if test $DEVICETYPE = OTHER; then +sed "s-^//PLACEHOLDER_NEWPROG_PROGRAMMER_ARRAY-\ + .type = OTHER,\n\ + .devs.note = \"Textual list of usable devices\\\\n\",\n\ +\0-" flashrom.c.mine >flashrom.c.mine1 +mv flashrom.c.mine1 flashrom.c.mine +else +sed "s-^//PLACEHOLDER_NEWPROG_PROGRAMMER_ARRAY-\ + .type = ${DEVICETYPE},\n\ + .devs.dev = devs_${PROGRAMMERNAME},\n\ +\0-" flashrom.c.mine >flashrom.c.mine1 +mv flashrom.c.mine1 flashrom.c.mine +fi +sed "s-^//PLACEHOLDER_NEWPROG_PROGRAMMER_ARRAY-\ + .init = ${PROGRAMMERNAME}_init,\n\ + .map_flash_region = ${MAPNAME}_map,\n\ + .unmap_flash_region = ${MAPNAME}_unmap,\n\ + .delay = ${DELAYNAME}_delay,\n\ + },\n\ +#endif\n\ +\n\0-" flashrom.c.mine >flashrom.c.mine1 +mv flashrom.c.mine1 flashrom.c.mine + +sed -e "s/^#PLACEHOLDER_NEWPROG_DEFAULTCONFIG/\ +# Enable ${PROGRAMMERDESCR} for now.\n\ +${CONFIGNAME} ?= yes\n\ +\n\0/" \ +-e "s/^#PLACEHOLDER_NEWPROG_COMPILERULE/\ +ifeq (\$(${CONFIGNAME}), yes)\n\ +FEATURE_CFLAGS += -D'${CONFIGNAME}=1'\n\ +PROGRAMMER_OBJS += ${PROGRAMMERNAME}.o\n\ +${NEEDS}\ +endif\n\ +\n\0/" Makefile >Makefile.mine + +if test $NEED_SPI_BITBANG = yes; then +sed -e "s/^#PLACEHOLDER_NEWPROG_BITBANGSPICONFIG1/\ +ifeq (\$(${CONFIGNAME}), yes)\n\ +override CONFIG_BITBANG_SPI = yes\n\ +else\n\ +\0/" \ +-e "s/^#PLACEHOLDER_NEWPROG_BITBANGSPICONFIG2/\ +\0\n\ +endif/;" Makefile.mine >Makefile.mine1 +mv Makefile.mine1 Makefile.mine +fi + +sed -e "s-^//PLACEHOLDER_NEWPROG_PROGRAMMER_ENUM-\ +#if ${CONFIGNAME} == 1\n\ + ${ENUMNAME},\n\ +#endif\n\ +\0-" \ +-e "s-^//PLACEHOLDER_NEWPROG_PUBLICFUNCTIONS-\ +/* ${PROGRAMMERNAME}.c */\n\ +#if ${CONFIGNAME} == 1\n\ +int ${PROGRAMMERNAME}_init(void);\n\ +\0-" programmer.h >programmer.h.mine + +if test $DEVICETYPE = PCI -o $DEVICETYPE = USB; then +sed -e "s-^//PLACEHOLDER_NEWPROG_PUBLICFUNCTIONS-\ +extern const struct dev_entry devs_${PROGRAMMERNAME}[];\n\ +\n\0-" programmer.h.mine >programmer.h.mine1 +mv programmer.h.mine1 programmer.h.mine +fi + +sed -e "s-^//PLACEHOLDER_NEWPROG_PUBLICFUNCTIONS-\ +#endif\n\ +\n\0-" programmer.h.mine >programmer.h.mine1 +mv programmer.h.mine1 programmer.h.mine + +if test $NEED_SPI_BITBANG = yes; then +sed -e "s-//PLACEHOLDER_NEWPROG_SELECT_SPI_BITBANG\$-\ +|| ${CONFIGNAME} == 1 \0-" programmer.h.mine >programmer.h.mine1 +mv programmer.h.mine1 programmer.h.mine +fi + +# No idea if roff supports hidden comments. Hook up to hopefully unchanged sequences. +sed -e "s/.*PLACEHOLDER_NEWPROG_MAN_SHORTDESCRIPTION/\ +.BR \"* ${PROGRAMMERNAME}\" \" (${PROGRAMMERDESCR})\"\n\ +.sp\n\ +\0/" \ +-e "s/.*PLACEHOLDER_NEWPROG_MAN_LONGDESCRIPTION/\ +.SS\n\ +.BR \"${PROGRAMMERNAME} \" programmer\n\ +Please describe the programmer parameters here.\n\ +\0/" \ +-e "s/.*PLACEHOLDER_NEWPROG_MAN_REQUIREMENTS/\ +.B ${PROGRAMMERNAME}\n\ +Please describe the programmer requirements here.\n\ +.sp\n\ +\0/" flashrom.8.tmpl > flashrom.8.tmpl.mine + +cat >$PROGRAMMERNAME.c.mine <<EOF +/* + * This file is part of the flashrom project. + * + * Copyright (C) $(date +%Y) ${AUTHORNAME} + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; ${GPLV3EITHER}version 2 of the License${GPLV3OR}. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Driver for the ${PROGRAMMERDESCR} hardware by ${PROGRAMMERMANUF}. + * See ${PROGRAMMERURL} for more info. + */ + +#include "flash.h" +#include "programmer.h" + +EOF + +if test $DEVICETYPE = PCI -o $DEVICETYPE = USB; then +cat >>$PROGRAMMERNAME.c.mine <<EOF +const struct dev_entry devs_${PROGRAMMERNAME}[] = { + {0xdead, 0xbeef, NT, "Vendor name", "Device name"}, + + {0}, +}; + +EOF +fi + +if test $NEED_PARLPCFWH = yes; then +cat >>$PROGRAMMERNAME.c.mine <<EOF +static void ${PROGRAMMERNAME}_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) +{ + /* Write a byte to the flash chip. */ +} + +static uint8_t ${PROGRAMMERNAME}_chip_readb(const struct flashctx *flash, const chipaddr addr) +{ + /* Read a byte from the flash chip and return it. */ + /* Set it to 0xff to get the template to compile. */ + uint8_t val = 0xff; + + return val; +} + +static const struct par_programmer par_programmer_${PROGRAMMERNAME} = { + .chip_readb = ${PROGRAMMERNAME}_chip_readb, + /* If your programmer supports word/long accesses, change the lines below. */ + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = ${PROGRAMMERNAME}_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + +EOF +fi + +if test $NEED_SPI_BITBANG = yes; then +cat >>$PROGRAMMERNAME.c.mine <<EOF +static void ${PROGRAMMERNAME}_bitbang_set_cs(int val) +{ + /* Set/clear the CS# line. */ +} + +static void ${PROGRAMMERNAME}_bitbang_set_sck(int val) +{ + /* Set/clear the SCLK line. */ +} + +static void ${PROGRAMMERNAME}_bitbang_set_mosi(int val) +{ + /* Set/clear the MOSI line. */ +} + +static int ${PROGRAMMERNAME}_bitbang_get_miso(void) +{ + /* Get the state of the MISO line and return it. */ + /* Set it to 1 to get the template to compile. */ + int misoval = 1; + + return misoval; +} + +/* If this programmer does not support requesting/releasing the SPI bus, remove + * the functions ${PROGRAMMERNAME}_request_spibus and ${PROGRAMMERNAME}_release_spibus + * and set bitbang_spi_master_${PROGRAMMERNAME} members .request_bus and .release_bus + * to NULL. + */ +static void ${PROGRAMMERNAME}_request_spibus(void) +{ +} + +static void ${PROGRAMMERNAME}_release_spibus(void) +{ +} + +static const struct bitbang_spi_master bitbang_spi_master_${PROGRAMMERNAME} = { + .set_cs = ${PROGRAMMERNAME}_bitbang_set_cs, + .set_sck = ${PROGRAMMERNAME}_bitbang_set_sck, + .set_mosi = ${PROGRAMMERNAME}_bitbang_set_mosi, + .get_miso = ${PROGRAMMERNAME}_bitbang_get_miso, + .request_bus = ${PROGRAMMERNAME}_request_spibus, + .release_bus = ${PROGRAMMERNAME}_release_spibus, + .half_period = 1, /* Delay in microseconds before each SCLK level change. */ +}; + +EOF +fi + +if test $NEED_SPI = yes; then +cat >>$PROGRAMMERNAME.c.mine <<EOF +/* Include string.h for memset to get the template to compile. Remove this. */ +#include <string.h> +static int ${PROGRAMMERNAME}_spi_send_command(struct flashctx *flash, + unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + /* Send a SPI command to the flash chip. */ + /* Set readarr to 0xff to get the template to compile and run without segfaults. */ + memset(readarr, 0xff, readcnt); + + return 0; +} + +static const struct spi_master spi_master_${PROGRAMMERNAME} = { + .max_data_read = 64 * 1024, /* Maximum data read size in one go (excluding opcode+address). */ + .max_data_write = 256, /* Maximum data write size in one go (excluding opcode+address). */ + .command = ${PROGRAMMERNAME}_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, +}; + +EOF +fi + +cat >>$PROGRAMMERNAME.c.mine <<EOF +static int ${PROGRAMMERNAME}_shutdown(void *data) +{ + /* Shutdown stuff. */ + return 0; +} + +int ${PROGRAMMERNAME}_init(void) +{ + /* Init stuff (i.e. parameter parsing) here which does not need to be + * undone. + */ + + /* If your shutdown function takes a parameter, replace NULL with it. */ + register_shutdown(${PROGRAMMERNAME}_shutdown, NULL); + + /* Init stuff which needs to be undone on shutdown. */ + +EOF + +if test $NEED_SPI_BITBANG = yes; then +cat >>$PROGRAMMERNAME.c.mine <<EOF + /* 1 usec halfperiod delay, change as needed. */ + if (bitbang_spi_init(&bitbang_spi_master_${PROGRAMMERNAME})) + return 1; + +EOF +fi + +if test $NEED_SPI = yes; then +cat >>$PROGRAMMERNAME.c.mine <<EOF + register_spi_master(&spi_master_${PROGRAMMERNAME}); + +EOF +fi + +if test $NEED_PARLPCFWH = yes; then +cat >>$PROGRAMMERNAME.c.mine <<EOF + register_par_programmer(&par_programmer_${PROGRAMMERNAME}, BUS_${BUS_PARLPCFWH}); + +EOF +fi + +cat >>$PROGRAMMERNAME.c.mine <<EOF + return 0; +} +EOF + +csplit -f .newmeson_options meson_options.txt "/#PLACEHOLDER_NEWPROG_MESON_OPTION_START/+1" "/#PLACEHOLDER_NEWPROG_MESON_OPTION_END/" +echo "option('config_${PROGRAMMERNAME}', type : 'boolean', value : true, description : '${PROGRAMMERDESCR}')" >>.newmeson_options01 +sort .newmeson_options01 >.newmeson_options03 +cat .newmeson_options00 .newmeson_options03 .newmeson_options02 >meson_options.txt.mine +rm .newmeson_options00 .newmeson_options01 .newmeson_options02 .newmeson_options03 + +csplit -f .newmeson meson.build "/#PLACEHOLDER_NEWPROG_MESON_CONFIGFETCH_START/+1" "/#PLACEHOLDER_NEWPROG_MESON_CONFIGFETCH_END/" +echo "config_${PROGRAMMERNAME} = get_option('config_${PROGRAMMERNAME}')" >>.newmeson01 +sort .newmeson01 >.newmeson03 +cat .newmeson00 .newmeson03 .newmeson02 >.newmeson.build.mine +rm .newmeson00 .newmeson01 .newmeson02 .newmeson03 + +if test $DEVICETYPE = PCI ; then + csplit -f .newmeson .newmeson.build.mine "/#PLACEHOLDER_NEWPROG_MESON_PCI_REQUIREMENT_MISSING_START/+1" "/#PLACEHOLDER_NEWPROG_MESON_PCI_REQUIREMENT_MISSING_END/" + echo " config_${PROGRAMMERNAME} = false" >>.newmeson01 + sort .newmeson01 >.newmeson03 + cat .newmeson00 .newmeson03 .newmeson02 >.newmeson.build.mine + rm .newmeson00 .newmeson01 .newmeson02 .newmeson03 +fi + +if test $DEVICETYPE = USB ; then + csplit -f .newmeson .newmeson.build.mine "/#PLACEHOLDER_NEWPROG_MESON_USB_REQUIREMENT_MISSING_START/+1" "/#PLACEHOLDER_NEWPROG_MESON_USB_REQUIREMENT_MISSING_END/" + echo " config_${PROGRAMMERNAME} = false" >>.newmeson01 + sort .newmeson01 >.newmeson03 + cat .newmeson00 .newmeson03 .newmeson02 >.newmeson.build.mine + rm .newmeson00 .newmeson01 .newmeson02 .newmeson03 +fi + +csplit -f .newmeson .newmeson.build.mine "/#PLACEHOLDER_NEWPROG_MESON_FILES_DEFINES_NEEDS_START/+1" "/#PLACEHOLDER_NEWPROG_MESON_FILES_DEFINES_NEEDS_END/" +# FIXME: The current meson.build always builds the PCI intrastructure unless explicitly disabled. +cat >>.newmeson01 <<EOF +if config_${PROGRAMMERNAME} + srcs += '${PROGRAMMERNAME}.c' + cargs += '-D${CONFIGNAME}=1' +EOF +if $NEED_SERIAL = yes; then + cat >>.newmeson01 <<EOF + need_serial = true +EOF +cat >>.newmeson01 <<EOF +endif +EOF +# FIXME: Sorting is a bit more complicated here. Skip it for now. +cat .newmeson00 .newmeson01 .newmeson02 >.newmeson.build.mine +rm .newmeson00 .newmeson01 .newmeson02 + +mv .newmeson.build.mine meson.build.mine + +echo "The driver skeleton has been created in $PROGRAMMERNAME.c.mine" +echo "Modified versions of existing files have been created with extension .mine" +echo "You can replace the original files with the modified versions by running" +echo "for a in *; do test -f \$a.mine && mv \$a.mine \$a; done" +echo "If you want to use the newly generated skeleton $PROGRAMMERNAME.c.mine , run" +echo "mv $PROGRAMMERNAME.c.mine $PROGRAMMERNAME.c" +echo +echo "WARNING: Please note that rerunning build_new_driver.sh will overwrite" +echo "all *.mine files, but it won't touch $PROGRAMMERNAME.c ." +echo "If something goes wrong, you can revert all files which look odd and" +echo "run this script again." diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index aa5bcd4..b28c86a 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -345,6 +345,7 @@ .sp .BR "* stlinkv3_spi" " (for SPI flash ROMs attached to STMicroelectronics STLINK V3 devices)" .sp +.\"PLACEHOLDER_NEWPROG_MAN_SHORTDESCRIPTION Some programmers have optional or mandatory parameters which are described in detail in the .B PROGRAMMER-SPECIFIC INFORMATION @@ -1287,7 +1288,7 @@ If the passed frequency is not supported by the adapter the nearest lower supported frequency will be used. .SS - +.\"PLACEHOLDER_NEWPROG_MAN_LONGDESCRIPTION .SH EXAMPLES To back up and update your BIOS, run .sp @@ -1365,6 +1366,7 @@ .B ogp needs PCI configuration space read access and raw memory access. .sp +.\"PLACEHOLDER_NEWPROG_MAN_REQUIREMENTS On OpenBSD, you can obtain raw access permission by setting .B "securelevel=-1" in diff --git a/flashrom.c b/flashrom.c index e540027..ad8b23e 100644 --- a/flashrom.c +++ b/flashrom.c @@ -473,6 +473,7 @@ }, #endif +//PLACEHOLDER_NEWPROG_PROGRAMMER_ARRAY {0}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; diff --git a/meson.build b/meson.build index 375089c..c602399 100644 --- a/meson.build +++ b/meson.build @@ -30,6 +30,7 @@ add_project_arguments('-DFLASHROM_VERSION="' + meson.project_version() + '"', language : 'c') # get defaults from configure +# PLACEHOLDER_NEWPROG_MESON_CONFIGFETCH_START config_atahpt = get_option('config_atahpt') config_atapromise = get_option('config_atapromise') config_atavia = get_option('config_atavia') @@ -62,6 +63,7 @@ config_serprog = get_option('config_serprog') config_usbblaster_spi = get_option('config_usbblaster_spi') config_stlinkv3_spi = get_option('config_stlinkv3_spi') +# PLACEHOLDER_NEWPROG_MESON_CONFIGFETCH_END cargs = [] deps = [] @@ -86,11 +88,13 @@ srcs += 'usbdev.c' deps += dependency('libusb-1.0') else +# PLACEHOLDER_NEWPROG_MESON_USB_REQUIREMENT_MISSING_START config_ch341a_spi = false config_dediprog = false config_digilent_spi = false config_developerbox_spi = false config_pickit2_spi = false +# PLACEHOLDER_NEWPROG_MESON_USB_REQUIREMENT_MISSING_END endif # some programmers require libpci @@ -99,6 +103,7 @@ deps += dependency('libpci') cargs += '-DNEED_PCI=1' else +# PLACEHOLDER_NEWPROG_MESON_PCI_REQUIREMENT_MISSING_START config_atahpt = false config_atapromise = false config_atavia = false @@ -116,9 +121,11 @@ config_rayer_spi = false config_satamv = false config_satasii = false +# PLACEHOLDER_NEWPROG_MESON_PCI_REQUIREMENT_MISSING_END endif # set defines for configured programmers +# PLACEHOLDER_NEWPROG_MESON_FILES_DEFINES_NEEDS_START if config_atahpt srcs += 'atahpt.c' cargs += '-DCONFIG_ATAHPT=1' @@ -276,6 +283,7 @@ srcs += 'stlinkv3_spi.c' cargs += '-DCONFIG_STLINKV3_SPI=1' endif +# PLACEHOLDER_NEWPROG_MESON_FILES_DEFINES_NEEDS_END # bitbanging SPI infrastructure if config_bitbang_spi diff --git a/meson_options.txt b/meson_options.txt index b7633d0..9e47272 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -1,6 +1,7 @@ option('pciutils', type : 'boolean', value : true, description : 'use pciutils') option('usb', type : 'boolean', value : true, description : 'use libusb1') +#PLACEHOLDER_NEWPROG_MESON_OPTION_START option('config_atahpt', type : 'boolean', value : false, description : 'Highpoint (HPT) ATA/RAID controllers') option('config_atapromise', type : 'boolean', value : false, description : 'Promise ATA controller') option('config_atavia', type : 'boolean', value : true, description : 'VIA VT6421A LPC memory') @@ -33,3 +34,4 @@ option('config_satasii', type : 'boolean', value : true, description : 'SiI SATA controllers') option('config_serprog', type : 'boolean', value : true, description : 'serprog') option('config_usbblaster_spi', type : 'boolean', value : true, description : 'Altera USB-Blaster dongles') +#PLACEHOLDER_NEWPROG_MESON_OPTION_END diff --git a/programmer.h b/programmer.h index 3cf53b9..90afc7b 100644 --- a/programmer.h +++ b/programmer.h @@ -127,6 +127,7 @@ #if CONFIG_STLINKV3_SPI == 1 PROGRAMMER_STLINKV3_SPI, #endif +//PLACEHOLDER_NEWPROG_PROGRAMMER_ENUM PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -573,6 +574,8 @@ int ni845x_spi_init(void); #endif +//PLACEHOLDER_NEWPROG_PUBLICFUNCTIONS + /* flashrom.c */ struct decode_sizes { uint32_t parallel; -- To view, visit https://review.coreboot.org/c/flashrom/+/38488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Icdcdcdcdcdcdcdcdcdcdcdcdcdcdcdcdcd000001 Gerrit-Change-Number: 38488 Gerrit-PatchSet: 1 Gerrit-Owner: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Gerrit-MessageType: newchange

5 13

Change in ...flashrom[master]: Add "--dangerous-bruteforce" mode for the unreliable ISP environments
by mikeb mikeb (Code Review) Aug. 29, 2026

Aug. 29, 2026

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/flashrom/+/31830 to review the following change. Change subject: Add "--dangerous-bruteforce" mode for the unreliable ISP environments ...................................................................... Add "--dangerous-bruteforce" mode for the unreliable ISP environments Some in-system-programming environments are very unreliable, e.g. when you connect a SOIC8 test clip to the flash chip of WR841ND v9 wireless router: because the low power SOC of this router becomes powered and is constantly trying to boot, the router's flash chip is correctly detected only 30% of times, and when it is detected just 30% of the read operations are successful - the rest result in zeroes or garbage data being read from a flash chip. While in this new "--dangerous-bruteforce" mode, flashrom will be constantly probing for a flash chip until it is correctly detected - and then, depending on the operation selected by a user, at the moments of chip availability it will be reading or writing by the small chunks of 256 bytes maximum size, verifying each small chunk and retrying the operation until the success or timeout (~ 60 sec). Constant probing between the small chunk operations is also being done - to avoid a possible situation where we have got two identical blocks of zeroes while reading a chunk and erroneously accepted it. Currently this mode is active only for those SPI25 chips which are ".write = spi_chip_write_256" and ".read = spi_chip_read", but later could be expanded to more functions to become useful for more chips. NOTE: this mode is experimental! Also, some targets like WR841ND v9 could block the ISP chip access completely if there is no bootable firmware inside (e.g. after you've tried to erase the chip contents). In such a situation it could be hard to recover the firmware without desoldering a flash chip and flashing it separately. Please do not erase or write to a flash chip using this mode if you are not sure. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: If47476793721a0061fd65bc6d1f98d48b03dc6c1 --- M cli_classic.c M flash.h M flashrom.c M libflashrom.c M libflashrom.h M spi25.c 6 files changed, 148 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/30/31830/1 diff --git a/cli_classic.c b/cli_classic.c index ced08c6..454df2b 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -51,6 +51,7 @@ " -V | --verbose more verbose output\n" " -c | --chip <chipname> probe only for specified flash chip\n" " -f | --force force specific operations (see man page)\n" + " --dangerous-bruteforce verify each small chunk and probe constantly\n" " -n | --noverify don't auto-verify\n" " -N | --noverify-all verify included regions only (cf. -i)\n" " -l | --layout <layoutfile> read ROM layout from <layoutfile>\n" @@ -104,7 +105,7 @@ #if CONFIG_PRINT_WIKI == 1 int list_supported_wiki = 0; #endif - int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; + int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0, bruteforce = 0, timeout = 30000; int dont_verify_it = 0, dont_verify_all = 0, list_supported = 0, operation_specified = 0; struct flashrom_layout *layout = NULL; enum programmer prog = PROGRAMMER_INVALID; @@ -113,6 +114,7 @@ OPTION_FMAP, OPTION_FMAP_FILE, OPTION_FLASH_CONTENTS, + OPTION_BRUTEFORCE, }; int ret = 0; @@ -127,6 +129,7 @@ {"chip", 1, NULL, 'c'}, {"verbose", 0, NULL, 'V'}, {"force", 0, NULL, 'f'}, + {"dangerous-bruteforce", 0, NULL, OPTION_BRUTEFORCE}, {"layout", 1, NULL, 'l'}, {"ifd", 0, NULL, OPTION_IFD}, {"fmap", 0, NULL, OPTION_FMAP}, @@ -228,6 +231,9 @@ case 'f': force = 1; break; + case OPTION_BRUTEFORCE: + bruteforce = 1; + break; case 'l': if (layoutfile) { fprintf(stderr, "Error: --layout specified " @@ -503,16 +509,27 @@ msg_pdbg("The following protocols are supported: %s.\n", tempstr); free(tempstr); - for (j = 0; j < registered_master_count; j++) { - startchip = 0; - while (chipcount < ARRAY_SIZE(flashes)) { - startchip = probe_flash(&registered_masters[j], startchip, &flashes[chipcount], 0); - if (startchip == -1) - break; - chipcount++; - startchip++; + do { + chipcount = 0; + for (j = 0; j < registered_master_count; j++) { + startchip = 0; + while (chipcount < ARRAY_SIZE(flashes)) { + startchip = probe_flash(&registered_masters[j], startchip, &flashes[chipcount], 0); + if (startchip == -1) + break; + chipcount++; + startchip++; + } } - } + timeout--; + if (!timeout) { + msg_cerr("Error: Timed out trying to detect a chip.\n"); + ret = 1; + goto out_shutdown; + } + } while (bruteforce && ( !chipcount || // wait for the correct chip detection + ((flashes[0].chip->manufacture_id == GENERIC_MANUF_ID) || + (flashes[0].chip->model_id == GENERIC_DEVICE_ID)) ) ); if (chipcount > 1) { msg_cinfo("Multiple flash chip definitions match the detected chip(s): \"%s\"", @@ -650,6 +667,7 @@ #if CONFIG_INTERNAL == 1 flashrom_flag_set(fill_flash, FLASHROM_FLAG_FORCE_BOARDMISMATCH, !!force_boardmismatch); #endif + flashrom_flag_set(fill_flash, FLASHROM_FLAG_BRUTEFORCE, !!bruteforce); flashrom_flag_set(fill_flash, FLASHROM_FLAG_VERIFY_AFTER_WRITE, !dont_verify_it); flashrom_flag_set(fill_flash, FLASHROM_FLAG_VERIFY_WHOLE_CHIP, !dont_verify_all); diff --git a/flash.h b/flash.h index 911214c..6ba116e 100644 --- a/flash.h +++ b/flash.h @@ -256,6 +256,7 @@ struct { bool force; bool force_boardmismatch; + bool bruteforce; bool verify_after_write; bool verify_whole_chip; } flags; diff --git a/flashrom.c b/flashrom.c index e82c32e..8f2c859 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1641,6 +1641,8 @@ size_t i, j; bool first = true; struct block_eraser *const eraser = &flashctx->chip->block_erasers[erasefunction]; + unsigned int bruteforce = flashrom_flag_get(flashctx, FLASHROM_FLAG_BRUTEFORCE); + int timeout; info->erase_start = 0; for (i = 0; i < NUM_ERASEREGIONS; ++i) { @@ -1662,9 +1664,34 @@ msg_cdbg(", "); msg_cdbg("0x%06x-0x%06x:", info->erase_start, info->erase_end); - ret = per_blockfn(flashctx, info, eraser->block_erase); - if (ret) - return ret; + if (!bruteforce) { + ret = per_blockfn(flashctx, info, eraser->block_erase); + if (ret) + return ret; + } else { + timeout = 30000; + while(1) { + timeout--; + if (!timeout) { + msg_cerr("%s timeout during command execution\n", __func__); + return 2; + } + + /* First probe. */ + if (flashctx->chip->probe(flashctx) != 1) + continue; + + ret = per_blockfn(flashctx, info, eraser->block_erase); + if (ret) + continue; + + /* Second probe. */ + if (flashctx->chip->probe(flashctx) != 1) + continue; + + break; + } + } } if (info->region_end < info->erase_start) break; diff --git a/libflashrom.c b/libflashrom.c index f90a22c..6dd0167 100644 --- a/libflashrom.c +++ b/libflashrom.c @@ -250,6 +250,7 @@ switch (flag) { case FLASHROM_FLAG_FORCE: flashctx->flags.force = value; break; case FLASHROM_FLAG_FORCE_BOARDMISMATCH: flashctx->flags.force_boardmismatch = value; break; + case FLASHROM_FLAG_BRUTEFORCE: flashctx->flags.bruteforce = value; break; case FLASHROM_FLAG_VERIFY_AFTER_WRITE: flashctx->flags.verify_after_write = value; break; case FLASHROM_FLAG_VERIFY_WHOLE_CHIP: flashctx->flags.verify_whole_chip = value; break; } @@ -267,6 +268,7 @@ switch (flag) { case FLASHROM_FLAG_FORCE: return flashctx->flags.force; case FLASHROM_FLAG_FORCE_BOARDMISMATCH: return flashctx->flags.force_boardmismatch; + case FLASHROM_FLAG_BRUTEFORCE: return flashctx->flags.bruteforce; case FLASHROM_FLAG_VERIFY_AFTER_WRITE: return flashctx->flags.verify_after_write; case FLASHROM_FLAG_VERIFY_WHOLE_CHIP: return flashctx->flags.verify_whole_chip; default: return false; diff --git a/libflashrom.h b/libflashrom.h index 38c95d2..0f2ead8 100644 --- a/libflashrom.h +++ b/libflashrom.h @@ -51,6 +51,7 @@ enum flashrom_flag { FLASHROM_FLAG_FORCE, FLASHROM_FLAG_FORCE_BOARDMISMATCH, + FLASHROM_FLAG_BRUTEFORCE, FLASHROM_FLAG_VERIFY_AFTER_WRITE, FLASHROM_FLAG_VERIFY_WHOLE_CHIP, }; diff --git a/spi25.c b/spi25.c index 8b6c462..832c836 100644 --- a/spi25.c +++ b/spi25.c @@ -21,6 +21,7 @@ #include <stddef.h> #include <string.h> #include <stdbool.h> +#include <stdlib.h> #include "flash.h" #include "flashchips.h" #include "chipdrivers.h" @@ -655,6 +656,48 @@ return spi_send_command(flash, 1 + addr_len, len, cmd, bytes); } +static int spi_rw_bruteforce(struct flashctx *flash, uint8_t *buf1, uint8_t *buf2, + unsigned int startrw_here, unsigned int torw_len, bool rw_flag) { + int rc = 0; + int timeout = 30000; + while (1) { + timeout--; + if (!timeout) { + msg_cerr("%s timeout during command execution\n", __func__); + return -1; + } + + /* First probe. */ + if (flash->chip->probe(flash) != 1) + continue; + + /* First operation. */ + if (rw_flag == 0) + rc = spi_nbyte_read(flash, startrw_here, buf1, torw_len); + else + rc = spi_nbyte_program(flash, startrw_here, buf1, torw_len); + + if (rc != 0) + break; + + /* Second probe. */ + if (flash->chip->probe(flash) != 1) + continue; + + /* Second operation. */ + rc = spi_nbyte_read(flash, startrw_here, buf2, torw_len); + if (rc != 0) + break; + + /* Compare two buffers. */ + if (memcmp(buf1, buf2, torw_len)) + continue; + + break; + } + return rc; +} + /* * Read a part of the flash chip. * FIXME: Use the chunk code from Michael Karcher instead. @@ -668,6 +711,19 @@ /* Limit for multi-die 4-byte-addressing chips. */ unsigned int area_size = min(flash->chip->total_size * 1024, 16 * 1024 * 1024); + unsigned int bruteforce = flashrom_flag_get(flash, FLASHROM_FLAG_BRUTEFORCE); + uint8_t *const buf1 = bruteforce ? malloc(chunksize) : NULL; + uint8_t *const buf2 = bruteforce ? malloc(chunksize) : NULL; + + if (bruteforce) { + if (!buf1 || !buf2) { + msg_gerr("Out of memory!\n"); + goto _free_ret; + } + msg_cdbg("spi_read_chunked: chunksize %i ---> %i\n", chunksize, min(chunksize, 256)); + chunksize = min(chunksize, 256); + } + /* Warning: This loop has a very unusual condition and body. * The loop needs to go through each area with at least one affected * byte. The lowest area number is (start / area_size) since that @@ -685,7 +741,11 @@ lenhere = min(start + len, (i + 1) * area_size) - starthere; for (j = 0; j < lenhere; j += chunksize) { toread = min(chunksize, lenhere - j); - rc = spi_nbyte_read(flash, starthere + j, buf + starthere - start + j, toread); + if (bruteforce) { + rc = spi_rw_bruteforce(flash, buf1, buf2, starthere + j, toread, 0 /* read */); + memcpy(buf + starthere - start + j, buf1, toread); + } else + rc = spi_nbyte_read(flash, starthere + j, buf + starthere - start + j, toread); if (rc) break; } @@ -693,6 +753,9 @@ break; } +_free_ret: + free(buf1); + free(buf2); return rc; } @@ -712,6 +775,19 @@ */ unsigned int page_size = flash->chip->page_size; + unsigned int bruteforce = flashrom_flag_get(flash, FLASHROM_FLAG_BRUTEFORCE); + uint8_t *const buf1 = bruteforce ? malloc(chunksize) : NULL; + uint8_t *const buf2 = bruteforce ? malloc(chunksize) : NULL; + + if (bruteforce) { + if (!buf1 || !buf2) { + msg_gerr("Out of memory!\n"); + goto _free_ret; + } + msg_cdbg("spi_write_chunked: chunksize %i ---> %i\n", chunksize, min(chunksize, 256)); + chunksize = min(chunksize, 256); + } + /* Warning: This loop has a very unusual condition and body. * The loop needs to go through each page with at least one affected * byte. The lowest page number is (start / page_size) since that @@ -731,12 +807,20 @@ int rc; towrite = min(chunksize, lenhere - j); - rc = spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite); + if (bruteforce) { + memcpy(buf1, buf + starthere - start + j, towrite); + rc = spi_rw_bruteforce(flash, buf1, buf2, starthere + j, towrite, 1 /* write */); + } else + rc = spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite); + if (rc) return rc; } } +_free_ret: + free(buf1); + free(buf2); return 0; } -- To view, visit https://review.coreboot.org/c/flashrom/+/31830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If47476793721a0061fd65bc6d1f98d48b03dc6c1 Gerrit-Change-Number: 31830 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

4 7

Change in flashrom[master]: dediprog: add serial argument
by David Hendricks (Code Review) Aug. 29, 2026

Aug. 29, 2026

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/37406 ) Change subject: dediprog: add serial argument ...................................................................... dediprog: add serial argument A quick hack to be able to select dediprogs by USB serial argument by just adding a @serial_number parameter to dediprog_open() and using it in preference to @id if available (since it is more specific). Change-Id: I9cdfbce6cf941c16bf7b7364aa4166b91369e661 Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez(a)intel.com> --- M dediprog.c M flashrom.8.tmpl 2 files changed, 23 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/06/37406/1 diff --git a/dediprog.c b/dediprog.c index 175e099..480cf67 100644 --- a/dediprog.c +++ b/dediprog.c @@ -1006,15 +1006,19 @@ /* * Open a dediprog_handle with the USB device at the given index. * @index index of the USB device + * @serial_number serial number of the USB device (id is ignored then) * @return 0 for success, -1 for error, -2 for busy device */ -static int dediprog_open(int index) +static int dediprog_open(int index, char *serial_number) { const uint16_t vid = devs_dediprog[0].vendor_id; const uint16_t pid = devs_dediprog[0].device_id; int ret; - dediprog_handle = usb_dev_get_by_vid_pid_number(usb_ctx, vid, pid, (unsigned int) index); + if (serial_number) + dediprog_handle = usb_dev_get_by_vid_pid_serial(usb_ctx, vid, pid, serial_number); + else + dediprog_handle = usb_dev_get_by_vid_pid_number(usb_ctx, vid, pid, (unsigned int) index); if (!dediprog_handle) { msg_perr("Could not find a Dediprog programmer on USB.\n"); libusb_exit(usb_ctx); @@ -1057,7 +1061,8 @@ int dediprog_init(void) { - char *voltage, *id_str, *device, *spispeed, *target_str; + char *voltage, *id_str, *device, *spispeed, *target_str, + *serial_number; int spispeed_idx = 1; int millivolt = 3500; int id = -1; /* -1 defaults to enumeration order */ @@ -1091,6 +1096,7 @@ msg_pinfo("Setting voltage to %i mV\n", millivolt); } + serial_number = extract_programmer_param("serial"); id_str = extract_programmer_param("id"); if (id_str) { char prefix0, prefix1; @@ -1183,9 +1189,14 @@ return 1; } - if (id != -1) { + if (serial_number) { + if (dediprog_open(0, serial_number)) { + return 1; + } + found_id = dediprog_read_id(); + } else if (id != -1) { for (i = 0; ; i++) { - ret = dediprog_open(i); + ret = dediprog_open(i, NULL); if (ret == -1) { /* no dev */ libusb_exit(usb_ctx); @@ -1218,7 +1229,7 @@ break; } } else { - if (dediprog_open(usedevice)) { + if (dediprog_open(usedevice, NULL)) { return 1; } found_id = dediprog_read_id(); @@ -1276,6 +1287,5 @@ if (register_spi_master(&spi_master_dediprog) || dediprog_set_leds(LED_NONE)) return 1; - return 0; } diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 27f3846..5af1a38 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -928,6 +928,12 @@ .BR 0V ", " 1.8V ", " 2.5V ", " 3.5V or the equivalent in mV. .sp +You can use the +.B serial +parameter to explicitly specify which dediprog device should be used +based on their USB serial number:: +.sp +.B " flashrom \-p dediprog:serial=1230A12" An optional .B device parameter specifies which of multiple connected Dediprog devices should be used. -- To view, visit https://review.coreboot.org/c/flashrom/+/37406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I9cdfbce6cf941c16bf7b7364aa4166b91369e661 Gerrit-Change-Number: 37406 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

6 11

Change in flashrom[master]: sb600spi.c: Improve IMC runtime detection in handle_imc()
by Edward O'Callaghan (Code Review) Aug. 29, 2026

Aug. 29, 2026

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/36424 ) Change subject: sb600spi.c: Improve IMC runtime detection in handle_imc() ...................................................................... sb600spi.c: Improve IMC runtime detection in handle_imc() The IMC detection in sb600spi is very rudimentary and incomplete. This expands it so that it can actually detect not only whether an IMC is in the system, but whether it's active or not. This is based off ChromiumOS's fork of flashrom where the solution looks to be originally authored by Martin Roth in b/62141938. Change-Id: I13fb2300475c06aad09a4f0e8cd032e212556b14 Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M sb600spi.c 1 file changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/24/36424/1 diff --git a/sb600spi.c b/sb600spi.c index c89d5a9..3c83b7b 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -55,6 +55,15 @@ #define FIFO_SIZE_OLD 8 #define FIFO_SIZE_YANGTZE 71 +#define PM_INDEX 0xCD6 +#define PM_DATA 0xCD7 +#define ISA_CONTROL 0x04 +#define MMIO_EN 0x02 +#define ACPI_MMIO_BASE 0xFED80000 +#define MISC_BASE 0xE00 +#define STRAP_STATUS 0x80 +#define EC_ENABLE_STRAP 0x04 + static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static int spi100_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, @@ -80,6 +89,12 @@ .write_aai = default_spi_write_aai, }; +static uint8_t pm_ioread(uint8_t addr) +{ + OUTB(addr, PM_INDEX); + return INB(PM_DATA); +} + static int find_smbus_dev(uint16_t vendor, uint16_t device) { struct pci_dev *smbus_dev = pci_dev_find(vendor, device); @@ -522,6 +537,25 @@ return 0; } + /* On Yangtze and newer chips, check the EcEnableStrap bit */ + if ((amd_gen >= CHIPSET_YANGTZE) && (pm_ioread(ISA_CONTROL) & MMIO_EN )) { + uint8_t *AcpiMMIO = rphysmap("AMD ACPI registers", ACPI_MMIO_BASE & 0xfffff000, 0x1000); + if (AcpiMMIO != ERROR_PTR) { + AcpiMMIO += MISC_BASE + STRAP_STATUS; + uint32_t straps = mmio_readl(AcpiMMIO); + if ((straps & EC_ENABLE_STRAP) == 0){ + msg_pinfo("IMC is not active.\n"); + return 0; + } else { + msg_pinfo("IMC IS active! Straps: %08x (%p)\n", straps, (void *)AcpiMMIO); + msg_pinfo("StrapOverride: %08x\n", mmio_readl(AcpiMMIO + 4)); + } + + } else { + msg_pinfo("Error reading AMD ACPI registers.\n"); + } + } + if (!amd_imc_force) programmer_may_write = 0; msg_pinfo("Writes have been disabled for safety reasons because the presence of the IMC\n" -- To view, visit https://review.coreboot.org/c/flashrom/+/36424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I13fb2300475c06aad09a4f0e8cd032e212556b14 Gerrit-Change-Number: 36424 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

4 5

Change in flashrom[master]: sb600spi -> fchspi: Rename AMD SPI programmer
by Edward O'Callaghan (Code Review) Aug. 29, 2026

Aug. 29, 2026

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/36434 ) Change subject: sb600spi -> fchspi: Rename AMD SPI programmer ...................................................................... sb600spi -> fchspi: Rename AMD SPI programmer The AMD FCH controller has two main SPI ip core variants, the so-called 'sb600' variant and the newer 'spi100' variant. The sb600spi.c driver supports both variants and so its name isn't very general. Here we rename it to be more general. Change-Id: Iad92fb224954d66968e7aeb75cb515f075a26ac8 Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M Makefile M chipset_enable.c R fchspi.c M meson.build M programmer.h 5 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/36434/1 diff --git a/Makefile b/Makefile index f0a1b61..143a8c1 100644 --- a/Makefile +++ b/Makefile @@ -767,7 +767,7 @@ FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o internal.o ifeq ($(ARCH), x86) -PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o amd_imc.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += it87spi.o it85spi.o fchspi.o amd_imc.o wbsio_spi.o mcp6x_spi.o PROGRAMMER_OBJS += ichspi.o dmi.o ifeq ($(CONFIG_INTERNAL_DMI), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL_DMI=1' diff --git a/chipset_enable.c b/chipset_enable.c index b55852c..e57a18e 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1297,7 +1297,7 @@ return enable_flash_amd_via(dev, name, 0xE0); } -static int enable_flash_sb600(struct pci_dev *dev, const char *name) +static int enable_flash_fch(struct pci_dev *dev, const char *name) { uint32_t prot; uint8_t reg; @@ -1330,7 +1330,7 @@ internal_buses_supported &= BUS_LPC | BUS_FWH; - ret = sb600_probe_spi(dev); + ret = fch_probe_spi(dev); /* Read ROM strap override register. */ OUTB(0x8f, 0xcd6); @@ -1685,16 +1685,16 @@ const struct penable chipset_enables[] = { #if defined(__i386__) || defined(__x86_64__) {0x1002, 0x4377, B_PFL, OK, "ATI", "SB400", enable_flash_sb400}, - {0x1002, 0x438d, B_FLS, OK, "AMD", "SB600", enable_flash_sb600}, - {0x1002, 0x439d, B_FLS, OK, "AMD", "SB7x0/SB8x0/SB9x0", enable_flash_sb600}, + {0x1002, 0x438d, B_FLS, OK, "AMD", "SB600", enable_flash_fch}, + {0x1002, 0x439d, B_FLS, OK, "AMD", "SB7x0/SB8x0/SB9x0", enable_flash_fch}, {0x100b, 0x0510, B_PFL, NT, "AMD", "SC1100", enable_flash_sc1100}, {0x1022, 0x2080, B_PFL, OK, "AMD", "CS5536", enable_flash_cs5536}, {0x1022, 0x2090, B_PFL, OK, "AMD", "CS5536", enable_flash_cs5536}, {0x1022, 0x3000, B_PFL, OK, "AMD", "Elan SC520", get_flashbase_sc520}, {0x1022, 0x7440, B_PFL, OK, "AMD", "AMD-768", enable_flash_amd_768_8111}, {0x1022, 0x7468, B_PFL, OK, "AMD", "AMD-8111", enable_flash_amd_768_8111}, - {0x1022, 0x780e, B_FLS, OK, "AMD", "FCH", enable_flash_sb600}, - {0x1022, 0x790e, B_FLS, OK, "AMD", "FP4", enable_flash_sb600}, + {0x1022, 0x780e, B_FLS, OK, "AMD", "FCH", enable_flash_fch}, + {0x1022, 0x790e, B_FLS, OK, "AMD", "FP4", enable_flash_fch}, {0x1039, 0x0406, B_PFL, NT, "SiS", "501/5101/5501", enable_flash_sis501}, {0x1039, 0x0496, B_PFL, NT, "SiS", "85C496+497", enable_flash_sis85c496}, {0x1039, 0x0530, B_PFL, OK, "SiS", "530", enable_flash_sis530}, diff --git a/sb600spi.c b/fchspi.c similarity index 99% rename from sb600spi.c rename to fchspi.c index 7bdd11f..e0eab07 100644 --- a/sb600spi.c +++ b/fchspi.c @@ -579,7 +579,7 @@ return amd_imc_shutdown(dev); } -int sb600_probe_spi(struct pci_dev *dev) +int fch_probe_spi(struct pci_dev *dev) { struct pci_dev *smbus_dev; uint32_t tmp; diff --git a/meson.build b/meson.build index d1f663f..d4bbff7 100644 --- a/meson.build +++ b/meson.build @@ -182,7 +182,7 @@ srcs += 'it85spi.c' srcs += 'it87spi.c' srcs += 'mcp6x_spi.c' - srcs += 'sb600spi.c' + srcs += 'fchspi.c' srcs += 'wbsio_spi.c' endif config_bitbang_spi = true diff --git a/programmer.h b/programmer.h index e42c6bb..e2cadd9 100644 --- a/programmer.h +++ b/programmer.h @@ -657,8 +657,8 @@ /* mcp6x_spi.c */ int mcp6x_spi_init(int want_spi); -/* sb600spi.c */ -int sb600_probe_spi(struct pci_dev *dev); +/* fchspi.c */ +int fch_probe_spi(struct pci_dev *dev); /* wbsio_spi.c */ int wbsio_check_for_spi(void); -- To view, visit https://review.coreboot.org/c/flashrom/+/36434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iad92fb224954d66968e7aeb75cb515f075a26ac8 Gerrit-Change-Number: 36434 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

4 3

Change in flashrom[master]: Match -c parameter against patterns in chip names
by Ryan O'Leary (Code Review) Aug. 29, 2026

Aug. 29, 2026

Ryan O'Leary has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/37723 ) Change subject: Match -c parameter against patterns in chip names ...................................................................... Match -c parameter against patterns in chip names This includes patterns such as "EN29GL064H/L", "Am29F002(N)BB" and "A25LQ032/A25LQ32A". This was inspired by a breakage in one of my scripts. The script hard-coded "-c CHIPX". When upstream changed the chip name to "CHIPX/CHIPY", my script broke. By recognizing this pattern, the -c parameter is more resilient to these types of changes. Since an exact match on the whole name takes priority (the current behavior), this should not break anyone's workflow. Change-Id: Iae00bb1108f2d5a0c10977cff63f9348b9fc017f Signed-off-by: Ryan O'Leary <ryanoleary(a)google.com> --- M cli_classic.c 1 file changed, 69 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/23/37723/1 diff --git a/cli_classic.c b/cli_classic.c index 73cc417..43aac0b 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -103,6 +103,68 @@ return 0; } +/* + * Return 1 if the chip name matches the pattern, otherwise 0. + * + * The pattern may be: + * 1. A single slash followed by a single character. + * Ex: "EN29GL064H/L" matches "EN29GL064H" and "EN29GL064L". + * 2. One character in parens. + * Ex: "Am29F002(N)BB" matches "Am29F002BB" and "Am29F002NBB". + * Ex: "EN29F002(A)(N)B" matches four different chip names. + * 3. A slash-separated list. + * Ex: "A25LQ032/A25LQ32A" matches "A25LQ032" and "A25LQ32A". + * Ex: "MX25L12835F/MX25L12845E/MX25L12865E" matches "MX25L12835F", "MX25L12845E" and "MX25L12865E". + * + * #2 may be nested in #3, for example "W29C010(M)/W29C011A/W29EE011/W29EE012". + */ +static int chip_name_match_pattern(const char *pattern, const char *chip) { + int plen = strlen(pattern); + int clen = strlen(chip); + + if (plen < 3 || clen < 3) { + return 0; + } + + /* Single slash followed by single character. */ + if (pattern[plen-2] == '/') { + for (int pidx = 0; pidx < plen - 2; pidx++) + if (pattern[pidx] == '/') + return 0; + return plen - 2 == clen && + strncmp(pattern, chip, plen - 3) == 0 && + (pattern[plen-1] == chip[clen-1] || + pattern[plen-3] == chip[clen-1]); + } + + int cidx = 0; + for (int pidx = 0; pidx < plen; pidx++) { + if (pattern[pidx] == '/') { + /* Check for termination. */ + if (cidx == clen) + break; + cidx = 0; /* Reset. */ + } else if (pattern[pidx] == '(') { + if (pidx + 2 >= plen || + pattern[pidx+1] == ')' || + pattern[pidx+1] == '(' || + pattern[pidx+2] != ')') + return 0; /* Invalid pattern. */ + if (pattern[pidx+1] == chip[cidx]) + cidx++; + pidx += 2; + } else if (pattern[pidx] == chip[cidx]) { + cidx++; + } else { + /* Reset to next slash. */ + while (pidx < plen && pattern[pidx] != '/') + pidx++; + cidx = 0; + } + } + return cidx == clen; +} + int main(int argc, char *argv[]) { const struct flashchip *chip = NULL; @@ -421,15 +483,22 @@ } /* Does a chip with the requested name exist in the flashchips array? */ if (chip_to_probe) { + /* First check for exact match. */ for (chip = flashchips; chip && chip->name; chip++) if (!strcmp(chip->name, chip_to_probe)) break; + /* Failing that, perform a pattern match. */ + if (!chip || !chip->name) + for (chip = flashchips; chip && chip->name; chip++) + if (chip_name_match_pattern(chip->name, chip_to_probe)) + break; if (!chip || !chip->name) { msg_cerr("Error: Unknown chip '%s' specified.\n", chip_to_probe); msg_gerr("Run flashrom -L to view the hardware supported in this flashrom version.\n"); ret = 1; goto out; } + msg_gdbg("Using chip \"%s\".\n", chip->name); /* Keep chip around for later usage in case a forced read is requested. */ } -- To view, visit https://review.coreboot.org/c/flashrom/+/37723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iae00bb1108f2d5a0c10977cff63f9348b9fc017f Gerrit-Change-Number: 37723 Gerrit-PatchSet: 1 Gerrit-Owner: Ryan O'Leary <ryanoleary(a)google.com> Gerrit-MessageType: newchange

3 2

Change in flashrom[master]: [RFC] udelay: Relax clock_gettime() resolution expectations
by Nico Huber (Code Review) Aug. 29, 2026

Aug. 29, 2026

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39864 ) Change subject: [RFC] udelay: Relax clock_gettime() resolution expectations ...................................................................... [RFC] udelay: Relax clock_gettime() resolution expectations Only few programmers actually want to delay by a single microsecond. So we can relax the expected mininum resolution by default and let indivi- dual programmers override as needed. UNTESTED Change-Id: Ia24f5c8440b7cb8abcc5a1509443d0c41fd2c559 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M bitbang_spi.c M cli_classic.c M nicintel_eeprom.c M udelay.c 4 files changed, 15 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/39864/1 diff --git a/bitbang_spi.c b/bitbang_spi.c index 7c183c3..8e5b8f2 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -104,6 +104,8 @@ mst.data = master; register_spi_master(&mst); + myusec_calibrate_delay(100); + /* Only mess with the bus if we're sure nobody else uses it. */ bitbang_spi_request_bus(master); bitbang_spi_set_cs(master, 1); diff --git a/cli_classic.c b/cli_classic.c index 73cc417..2436351 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -454,7 +454,7 @@ } /* FIXME: Delay calibration should happen in programmer code. */ - myusec_calibrate_delay(); + myusec_calibrate_delay(1000); if (programmer_init(prog, pparam)) { msg_perr("Error: Programmer initialization failed.\n"); diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c index 4d45f79..06284d4 100644 --- a/nicintel_eeprom.c +++ b/nicintel_eeprom.c @@ -449,6 +449,8 @@ int nicintel_ee_init(void) { + myusec_calibrate_delay(100); + if (rget_io_perms()) return 1; diff --git a/udelay.c b/udelay.c index 6c0efc4..3f0b6d1 100644 --- a/udelay.c +++ b/udelay.c @@ -52,11 +52,11 @@ } while (now.tv_sec < end.tv_sec || (now.tv_sec == end.tv_sec && now.tv_nsec < end.tv_nsec)); } -static int clock_check_res(void) +static int clock_check_res(const unsigned int resolution_ns) { struct timespec res; if (!clock_getres(clock_id, &res)) { - if (res.tv_sec == 0 && res.tv_nsec <= 100) { + if (res.tv_sec == 0 && res.tv_nsec <= resolution_ns) { msg_pinfo("Using clock_gettime for delay loops (clk_id: %d, resolution: %ldns).\n", (int)clock_id, res.tv_nsec); use_clock_gettime = true; @@ -65,7 +65,7 @@ } else if (clock_id != CLOCK_REALTIME && errno == EINVAL) { /* Try again with CLOCK_REALTIME. */ clock_id = CLOCK_REALTIME; - return clock_check_res(); + return clock_check_res(resolution_ns); } return 0; } @@ -77,7 +77,7 @@ #endif /* HAVE_CLOCK_GETTIME == 1 */ /* loops per microsecond */ -static unsigned long micro = 1; +static unsigned long micro; __attribute__ ((noinline)) void myusec_delay(unsigned int usecs) { @@ -133,15 +133,19 @@ return timeusec; } -void myusec_calibrate_delay(void) +void myusec_calibrate_delay(const unsigned int resolution_ns) { - if (clock_check_res()) + if (clock_check_res(resolution_ns)) return; + if (micro) + return; /* already calibrated */ + unsigned long count = 1000; unsigned long timeusec, resolution; int i, tries = 0; + micro = 1; msg_pinfo("Calibrating delay loop... "); resolution = measure_os_delay_resolution(); if (resolution) { -- To view, visit https://review.coreboot.org/c/flashrom/+/39864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia24f5c8440b7cb8abcc5a1509443d0c41fd2c559 Gerrit-Change-Number: 39864 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in flashrom[master]: linux_spi: add configurable spimode
by Leonard König (Code Review) Aug. 29, 2026

Aug. 29, 2026

Leonard König has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/38725 ) Change subject: linux_spi: add configurable spimode ...................................................................... linux_spi: add configurable spimode Signed-off-by: Leonard König <leonard.r.koenig(a)googlemail.com> Change-Id: I650cb20efd7a34c5c12bec187e25a4757388dcf8 --- M flashrom.8.tmpl M linux_spi.c 2 files changed, 40 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/25/38725/1 diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index aa5bcd4..1d0cff8 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -1079,6 +1079,12 @@ .sp .B " flashrom \-p linux_spi:dev=/dev/spidevX.Y,spispeed=8000" .sp +Similarly, you can set the SPI mode with the optional +.B spimode +parameter. The mode can be either 0/1/2/3 from the kernel interface, ie. +SPI mode 0 meaning that (CPOL,CPHA) is (0,0), a mode of 1 meaning (0,1), a mode +of 2 (1,0) and a mode of 3 (1,1). +.sp Please note that the linux_spi driver only works on Linux. .SS .BR "mstarddc_spi " programmer diff --git a/linux_spi.c b/linux_spi.c index aa73c18..c890b12 100644 --- a/linux_spi.c +++ b/linux_spi.c @@ -73,9 +73,9 @@ { char *p, *endp, *dev; uint32_t speed_hz = 2 * 1000 * 1000; - /* FIXME: make the following configurable by CLI options. */ /* SPI mode 0 (beware this also includes: MSB first, CS active low and others */ - const uint8_t mode = SPI_MODE_0; + uint8_t mode = SPI_MODE_0; + /* FIXME: make the following configurable by CLI options. */ const uint8_t bits = 8; p = extract_programmer_param("spispeed"); @@ -92,6 +92,38 @@ speed_hz / 1000); } free(p); + p = extract_programmer_param("spimode"); + if (p && strlen(p)) { + unsigned long x = strtoul(p, &endp, 10); + if (p == endp || x > 3 /* SPI_MODE_3 */) { + msg_perr("%s: invalid mode: %s\n", __func__, p); + free(p); + return 1; + } + switch (x) { + case 0: + mode = SPI_MODE_0; + break; + case 1: + mode = SPI_MODE_1; + break; + case 2: + mode = SPI_MODE_2; + break; + case 3: + mode = SPI_MODE_3; + break; + default: + /* unreachable */ + break; + } + } else { + msg_pinfo("Using default %"PRIu8" mode. " + "Use 'spimode' parameter to override.\n", + mode); + } + free(p); + dev = extract_programmer_param("dev"); if (!dev || !strlen(dev)) { -- To view, visit https://review.coreboot.org/c/flashrom/+/38725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I650cb20efd7a34c5c12bec187e25a4757388dcf8 Gerrit-Change-Number: 38725 Gerrit-PatchSet: 1 Gerrit-Owner: Leonard König <leonard.r.koenig(a)googlemail.com> Gerrit-MessageType: newchange

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