October 2020 - flashrom-gerrit

Change in flashrom[master]: programmer: Introduce programmer alias mechanism
by Edward O'Callaghan (Code Review) Aug. 29, 2026

Aug. 29, 2026

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/38671 ) Change subject: programmer: Introduce programmer alias mechanism ...................................................................... programmer: Introduce programmer alias mechanism Originally introduced in the downstream commit ba0827acee4da6740133345f43aae386923bbaad . This was originally authored by David Hendricks so that the various flash peripheral in ChromeOS devices can be flashed. For example, flashrom -p ec -r ec.bin flashrom -p host -r host.bin Note that this requires, `CONFIG_DEFAULT_PROGRAMMER=PROGRAMMER_INTERNAL make` to be defined as build-time. BUG=b:148755493 BRANCH=none TEST=ran ./flashrom -p host --flash-name Change-Id: I73766451cd8900a9e0fe08efc7a4d81b2a35ac8d Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M cli_classic.c M it85spi.c M linux_mtd.c M linux_spi.c M programmer.c M programmer.h 6 files changed, 98 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/71/38671/1 diff --git a/cli_classic.c b/cli_classic.c index 73cc417..d58562b 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -329,13 +329,51 @@ break; } } - if (prog == PROGRAMMER_INVALID) { + + for (i = 0; aliases[i].name; i++) { + name = aliases[i].name; + namelen = strlen(aliases[i].name); + + if (strncmp(optarg, name, namelen)) + continue; + + switch (optarg[namelen]) { + case ':': + pparam = strdup(optarg + namelen + 1); + if (!strlen(pparam)) { + free(pparam); + pparam = NULL; + } + break; + case '\0': + break; + default: + /* The continue refers to the for-loop. + * It is here to be able to + * differentiate between foo and foobar. + */ + continue; + } + + alias = &aliases[i]; + msg_gdbg("Programmer alias: \"%s\", parameter: " + " \"%s\",\n", alias->name, pparam); + break; + } + + if ((prog == PROGRAMMER_INVALID) && !alias) { fprintf(stderr, "Error: Unknown programmer \"%s\". Valid choices are:\n", optarg); list_programmers_linebreak(0, 80, 0); msg_ginfo(".\n"); cli_classic_abort_usage(NULL); } + + if ((prog != PROGRAMMER_INVALID) && alias) { + fprintf(stderr, "Error: Alias cannot be used " + "with programmer name.\n"); + cli_classic_abort_usage(NULL); + } break; case 'R': /* print_version() is always called during startup. */ diff --git a/it85spi.c b/it85spi.c index 5ce9193..47e2337 100644 --- a/it85spi.c +++ b/it85spi.c @@ -289,6 +289,9 @@ { int ret; + if (!programming_ec()) + return 1; + if (!(internal_buses_supported & BUS_FWH)) { msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__); return 1; diff --git a/linux_mtd.c b/linux_mtd.c index d2df95e..bee7cc5 100644 --- a/linux_mtd.c +++ b/linux_mtd.c @@ -363,6 +363,9 @@ int dev_num = 0; int ret = 1; + if (!programming_host()) + return 1; + param = extract_programmer_param("dev"); if (param) { char *endptr; diff --git a/linux_spi.c b/linux_spi.c index aa73c18..221a36e 100644 --- a/linux_spi.c +++ b/linux_spi.c @@ -78,6 +78,14 @@ const uint8_t mode = SPI_MODE_0; const uint8_t bits = 8; + /* + * FIXME: There might be other programmers with flash memory (such as + * an EC) connected via SPI. For now we rely on the device's driver to + * distinguish it and assume generic SPI implies host. + */ + if (!programming_host()) + return 1; + p = extract_programmer_param("spispeed"); if (p && strlen(p)) { speed_hz = (uint32_t)strtoul(p, &endp, 10) * 1000; diff --git a/programmer.c b/programmer.c index f4b4384..ffad784 100644 --- a/programmer.c +++ b/programmer.c @@ -128,6 +128,13 @@ return 0; } +struct programmer_alias aliases[] = { + { "ec", ALIAS_EC }, + { "host", ALIAS_HOST }, + { NULL }, +}; +struct programmer_alias *alias; + enum chipbustype get_buses_supported(void) { int i; diff --git a/programmer.h b/programmer.h index 3cf53b9..a7bd947 100644 --- a/programmer.h +++ b/programmer.h @@ -130,6 +130,44 @@ PROGRAMMER_INVALID /* This must always be the last entry. */ }; +enum alias_type { + ALIAS_NONE = 0, /* no alias (default) */ + ALIAS_EC, /* embedded controller */ + ALIAS_HOST, /* chipset / PCH / SoC / etc. */ +}; + +struct programmer_alias { + const char *name; + enum alias_type type; +}; + +extern struct programmer_alias *alias; +extern struct programmer_alias aliases[]; + +/** + * This function returns 'true' if current flashrom invocation is programming + * NONE. + */ +static inline int programming_none(void) { + return alias && (alias->type == ALIAS_NONE); +} + +/** + * This function returns 'true' if current flashrom invocation is programming + * the EC. + */ +static inline int programming_ec(void) { + return alias && (alias->type == ALIAS_EC); +} + +/** + * This function returns 'true' if current flashrom invocation is programming + * the HOST. + */ +static inline int programming_host(void) { + return alias && (alias->type == ALIAS_HOST); +} + enum programmer_type { PCI = 1, /* to detect uninitialized values */ USB, -- To view, visit https://review.coreboot.org/c/flashrom/+/38671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I73766451cd8900a9e0fe08efc7a4d81b2a35ac8d Gerrit-Change-Number: 38671 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: udelay.c: Enable providing delay calibration value through CLI
by Hrvoje Čavrak (Code Review) Aug. 29, 2026

Aug. 29, 2026

Hrvoje Čavrak has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44517 ) Change subject: udelay.c: Enable providing delay calibration value through CLI ...................................................................... udelay.c: Enable providing delay calibration value through CLI This commit implements --get-loop-delay/--set-loop-delay options to retrieve and provide the calibration loop delay through the command line. The delay calibration procedure can take up to few seconds, which adds up when executed a number of times consecutively. Therefore, this provides a means to execute it only once, and then re-use the calibrated value on subsequent runs. Also, it implements a sanity check, expecting the value to land within 10% of the theoretical delay expectance, otherwise it ignores the provided value and runs the calibration procedure instead. Signed-off-by: Hrvoje Cavrak <hrvoje(a)hrvoje.org> Change-Id: I7c9a491c5cb5fb3af56a691a0c6af9b53dcff550 --- M cli_classic.c M flashrom.8.tmpl M libflashrom.c M programmer.h M udelay.c 5 files changed, 60 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/17/44517/1 diff --git a/cli_classic.c b/cli_classic.c index 967ff50..b023c45 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -63,6 +63,8 @@ " -o | --output <logfile> log output to <logfile>\n" " --flash-contents <ref-file> assume flash contents to be <ref-file>\n" " -L | --list-supported print supported devices\n" + " --set-loop-delay <value> set loop delay calibration manually\n" + " --get-loop-delay retrieve loop delay calibration\n" #if CONFIG_PRINT_WIKI == 1 " -z | --list-supported-wiki print supported devices in wiki syntax\n" #endif @@ -118,6 +120,7 @@ int flash_name = 0, flash_size = 0; int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; int dont_verify_it = 0, dont_verify_all = 0, list_supported = 0, operation_specified = 0; + unsigned long provided_delay = 0; struct flashrom_layout *layout = NULL; enum programmer prog = PROGRAMMER_INVALID; enum { @@ -127,6 +130,8 @@ OPTION_FLASH_CONTENTS, OPTION_FLASH_NAME, OPTION_FLASH_SIZE, + OPTION_GET_LOOP_DELAY, + OPTION_SET_LOOP_DELAY, }; int ret = 0; @@ -156,6 +161,8 @@ {"help", 0, NULL, 'h'}, {"version", 0, NULL, 'R'}, {"output", 1, NULL, 'o'}, + {"get-loop-delay", 0, NULL, OPTION_GET_LOOP_DELAY}, + {"set-loop-delay", 1, NULL, OPTION_SET_LOOP_DELAY}, {NULL, 0, NULL, 0}, }; @@ -365,6 +372,14 @@ } #endif /* STANDALONE */ break; + case OPTION_GET_LOOP_DELAY: + /* Make it easy for scripts to parse this by omitting anything else */ + msg_pinfo("%lu\n", get_calibration_value()); + exit(0); + break; + case OPTION_SET_LOOP_DELAY: + provided_delay = strtoul(strdup(optarg), NULL, 0); + break; default: cli_classic_abort_usage(NULL); break; @@ -457,7 +472,10 @@ } /* FIXME: Delay calibration should happen in programmer code. */ - myusec_calibrate_delay(); + if (provided_delay) + set_external_calibration(provided_delay); + else + myusec_calibrate_delay(0); if (programmer_init(prog, pparam)) { msg_perr("Error: Programmer initialization failed.\n"); diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index db50d59..4aada91 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -50,7 +50,7 @@ [\fB\-E\fR|\fB\-r\fR <file>|\fB\-w\fR <file>|\fB\-v\fR <file>] [(\fB\-l\fR <file>|\fB\-\-ifd|\fB \-\-fmap\fR|\fB\-\-fmap-file\fR <file>) [\fB\-i\fR <image>]] [\fB\-n\fR] [\fB\-N\fR] [\fB\-f\fR])] - [\fB\-V\fR[\fBV\fR[\fBV\fR]]] [\fB-o\fR <logfile>] + [\fB\-V\fR[\fBV\fR[\fBV\fR]]] [\fB-o\fR <logfile>] [\fB-d\fR get | <value>] .SH DESCRIPTION .B flashrom is a utility for detecting, reading, writing, verifying and erasing flash @@ -364,6 +364,17 @@ .TP .B "\-R, \-\-version" Show version information and exit. +.TP +.B "\-\-get\-loop\-delay" +Retrieve the loop calibration delay value or provide one externally. Calibrate +delay procedure can take a few seconds and for repeated execution on a large +number of hosts it can provide a significant overhead. By getting the value, +it can later be provided by \-\-set\-loop\-delay +.TP +.B "\-\-set\-loop\-delay <value>" +This argument makes it possible to provide the calibration delay through the +command line option. + .SH PROGRAMMER-SPECIFIC INFORMATION Some programmer drivers accept further parameters to set programmer-specific parameters. These parameters are separated from the programmer name by a diff --git a/libflashrom.c b/libflashrom.c index ae2d33d..92e2527 100644 --- a/libflashrom.c +++ b/libflashrom.c @@ -51,7 +51,7 @@ { if (perform_selfcheck && selfcheck()) return 1; - myusec_calibrate_delay(); + myusec_calibrate_delay(0); return 0; } diff --git a/programmer.h b/programmer.h index c5cab18..e0925e2 100644 --- a/programmer.h +++ b/programmer.h @@ -280,9 +280,11 @@ /* udelay.c */ void myusec_delay(unsigned int usecs); -void myusec_calibrate_delay(void); +void myusec_calibrate_delay(int force); void internal_sleep(unsigned int usecs); void internal_delay(unsigned int usecs); +unsigned long get_calibration_value(void); +void set_external_calibration(unsigned long external_micro); #if CONFIG_INTERNAL == 1 /* board_enable.c */ diff --git a/udelay.c b/udelay.c index 6c0efc4..698f1ca 100644 --- a/udelay.c +++ b/udelay.c @@ -133,9 +133,9 @@ return timeusec; } -void myusec_calibrate_delay(void) +void myusec_calibrate_delay(int force) { - if (clock_check_res()) + if (clock_check_res() && !force) return; unsigned long count = 1000; @@ -221,6 +221,28 @@ msg_pinfo("OK.\n"); } +void set_external_calibration(unsigned long external_micro) +{ + micro = external_micro; + unsigned long elapsed = measure_delay(100000); + /* Do a sanity check if the provided parameter makes loops fall + * within 10% of the desired value. Otherwise, ignore provided value + * and recalibrate. + */ + if (elapsed > 90000 && elapsed < 110000) + msg_pinfo("Provided delay is acceptable!\n"); + else { + msg_pinfo("Elapsed: %lu, provided delay is NOT acceptable!\n", elapsed); + myusec_calibrate_delay(1); /* Ignore using the system clock for loop timing */ + } +} + +unsigned long get_calibration_value(void) +{ + myusec_calibrate_delay(1); /* Ignore using the system clock for loop timing */ + return micro; +} + /* Not very precise sleep. */ void internal_sleep(unsigned int usecs) { @@ -250,7 +272,7 @@ #else #include <libpayload.h> -void myusec_calibrate_delay(void) +void myusec_calibrate_delay(int force) { get_cpu_speed(); } -- To view, visit https://review.coreboot.org/c/flashrom/+/44517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7c9a491c5cb5fb3af56a691a0c6af9b53dcff550 Gerrit-Change-Number: 44517 Gerrit-PatchSet: 1 Gerrit-Owner: Hrvoje Čavrak <github(a)hrvoje.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: cbtable.c: don't assume high addresses can fully map 1MB
by Edward O'Callaghan (Code Review) Aug. 29, 2026

Aug. 29, 2026

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/45521 ) Change subject: cbtable.c: don't assume high addresses can fully map 1MB ...................................................................... cbtable.c: don't assume high addresses can fully map 1MB I do not know a clean way to compose find_lb_table() and find_lb_table_remap() or why this cannot always been done. However this is a fix ported from downstream found here: https://chromium-review.googlesource.com/685608 Change-Id: Ibf2323a0a793f693928b81c64acd09bb932a6b98 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M cbtable.c 1 file changed, 61 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/21/45521/1 diff --git a/cbtable.c b/cbtable.c index 6185f12..6dd4059 100644 --- a/cbtable.c +++ b/cbtable.c @@ -205,8 +205,68 @@ msg_pdbg("Found coreboot table at 0x%08lx.\n", addr); return head; + }; + + return NULL; +} + +static struct lb_header *find_lb_table_remap(unsigned long start_addr, + uint8_t **table_area) +{ + size_t offset; + unsigned long addr, end; + size_t mapping_size; + void *base; + + mapping_size = getpagesize(); + offset = start_addr % getpagesize(); + start_addr -= offset; + + base = physmap_ro("high tables", start_addr, mapping_size); + if (ERROR_PTR == base) { + msg_perr("Failed getting access to coreboot high tables.\n"); + return NULL; } + for (addr = offset, end = getpagesize(); addr < end; addr += 16) { + struct lb_record *recs; + struct lb_header *head; + + /* No more headers to check. */ + if (end - addr < sizeof(*head)) + return NULL; + + head = (struct lb_header *)(((char *)base) + addr); + + if (!lb_header_valid(head, addr)) + continue; + + if (mapping_size - addr < head->table_bytes + sizeof(*head)) { + size_t prev_mapping_size = mapping_size; + mapping_size = head->table_bytes + sizeof(*head); + mapping_size += addr; + mapping_size += getpagesize() - + (mapping_size % getpagesize()); + physunmap(base, prev_mapping_size); + base = physmap_ro("high tables", start_addr, + mapping_size); + if (ERROR_PTR == base) { + msg_perr("Failed getting access to coreboot high tables.\n"); + return NULL; + } + } + + head = (struct lb_header *)(((char *)base) + addr); + recs = + (struct lb_record *)(((char *)base) + addr + sizeof(*head)); + if (!lb_table_valid(head, recs)) + continue; + msg_pdbg("Found coreboot table at 0x%08lx.\n", addr); + *table_area = base; + return head; + } + + physunmap(base, mapping_size); return NULL; } @@ -283,15 +343,9 @@ (((char *)lb_table) + lb_table->header_bytes); if (forward->tag == LB_TAG_FORWARD) { start = forward->forward; - start &= ~(getpagesize() - 1); physunmap_unaligned(table_area, BYTES_TO_MAP); // FIXME: table_area is never unmapped below, nor is it unmapped above in the no-forward case - table_area = physmap_ro_unaligned("high tables", start, BYTES_TO_MAP); - if (ERROR_PTR == table_area) { - msg_perr("Failed getting access to coreboot high tables.\n"); - return -1; - } - lb_table = find_lb_table(table_area, 0x00000, 0x1000); + lb_table = find_lb_table_remap(start, &table_area); } } -- To view, visit https://review.coreboot.org/c/flashrom/+/45521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ibf2323a0a793f693928b81c64acd09bb932a6b98 Gerrit-Change-Number: 45521 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...flashrom[master]: [WIP]spi25.c: Implement fast read
by Arthur Heymans (Code Review) Aug. 29, 2026

Aug. 29, 2026

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/33034 Change subject: [WIP]spi25.c: Implement fast read ...................................................................... [WIP]spi25.c: Implement fast read Use the fast read OP by default and fall back to regular read if that failed. Change-Id: I96393e1beea0164daa8e366a1d09a573f2c6d16f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M ichspi.c M spi.h M spi25.c 3 files changed, 23 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/33034/1 diff --git a/ichspi.c b/ichspi.c index 0f1470d..54cb1f9 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1117,14 +1117,14 @@ opcode = &(curopcodes->opcode[opcode_index]); /* The following valid writecnt/readcnt combinations exist: - * writecnt = 4, readcnt >= 0 + * writecnt = 4 or 5, readcnt >= 0 (The dummy bit on fast reads gets discarded) * writecnt = 1, readcnt >= 0 * writecnt >= 4, readcnt = 0 * writecnt >= 1, readcnt = 0 * writecnt >= 1 is guaranteed for all commands. */ if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) && - (writecnt != 4)) { + ((writecnt != 4) && (writecnt != 5))) { msg_perr("%s: Internal command size error for opcode " "0x%02x, got writecnt=%i, want =4\n", __func__, cmd, writecnt); diff --git a/spi.h b/spi.h index 0073c71..65dc033 100644 --- a/spi.h +++ b/spi.h @@ -149,6 +149,7 @@ /* Read the memory */ #define JEDEC_READ 0x03 #define JEDEC_READ_OUTSIZE 0x04 +#define JEDEC_FAST_READ 0x0b /* JEDEC_READ_INSIZE : any length */ /* Read the memory (with delay after sending address) */ @@ -168,6 +169,7 @@ /* Read the memory with 4-byte address From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ #define JEDEC_READ_4BA 0x13 +#define JEDEC_FAST_READ_4BA 0x0c /* Read the memory with 4-byte address (and delay after sending address) From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ diff --git a/spi25.c b/spi25.c index 8b6c462..36d2436 100644 --- a/spi25.c +++ b/spi25.c @@ -645,12 +645,30 @@ unsigned int len) { const bool native_4ba = flash->chip->feature_bits & FEATURE_4BA_READ && spi_master_4ba(flash); - uint8_t cmd[1 + JEDEC_MAX_ADDR_LEN] = { native_4ba ? JEDEC_READ_4BA : JEDEC_READ, }; + bool fast_read = true; + uint8_t cmd[2 + JEDEC_MAX_ADDR_LEN]; + + if (native_4ba) + fast_read = flash->chip->feature_bits & FEATURE_4BA_FAST_READ; + + if (fast_read) + cmd[0] = native_4ba ? JEDEC_FAST_READ_4BA : JEDEC_FAST_READ; + else + cmd[0] = native_4ba ? JEDEC_READ_4BA : JEDEC_READ; const int addr_len = spi_prepare_address(flash, cmd, native_4ba, address); if (addr_len < 0) return 1; + if (fast_read) { + cmd[addr_len + 1] = 0; + int ret = spi_send_command(flash, 2 + addr_len, len, cmd, bytes); + if (!ret) + return ret; + msg_cinfo("%s: Fast Read did not succeed, falling back to regular read", __func__); + cmd[0] = native_4ba ? JEDEC_READ_4BA : JEDEC_READ; + } + /* Send Read */ return spi_send_command(flash, 1 + addr_len, len, cmd, bytes); } -- To view, visit https://review.coreboot.org/c/flashrom/+/33034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I96393e1beea0164daa8e366a1d09a573f2c6d16f Gerrit-Change-Number: 33034 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in flashrom[master]: nicintel: add I350 support
by Martijn Berger (Code Review) Aug. 29, 2026

Aug. 29, 2026

Martijn Berger has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39963 ) Change subject: nicintel: add I350 support ...................................................................... nicintel: add I350 support While trying to flash I350 Intel NIC's on arm64 linux I had to change some things to make it work well Change-Id: Id203d2ce247cf39a8d650887322ccced0151c6a9 Signed-off-by: Martijn Berger <martijn.berger(a)gmail.com> --- M nicintel_eeprom.c M nicintel_spi.c 2 files changed, 39 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/63/39963/1 diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c index 4d45f79..be03e41 100644 --- a/nicintel_eeprom.c +++ b/nicintel_eeprom.c @@ -27,6 +27,9 @@ * 8.4.3: EEPROM-Mode Read Register * 8.4.6: EEPROM-Mode Write Register * Write process inspired on kernel e1000_i210.c + * + * Intel I350 Gigabit controller Datasheet + * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/eth… */ #include <stdlib.h> @@ -75,8 +78,6 @@ static struct pci_dev *nicintel_pci; static bool done_i20_write = false; -#define UNPROG_DEVICE 0x1509 - /* * Warning: is_i210() below makes assumptions on these PCI ids. * It may have to be updated when this list is extended. @@ -87,7 +88,7 @@ {PCI_VENDOR_ID_INTEL, 0x1510, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Backplane)"}, {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Ext. PHY)"}, {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Dual Gigabit Ethernet Controller (Copper)"}, - {PCI_VENDOR_ID_INTEL, UNPROG_DEVICE, OK, "Intel", "Unprogrammed 82580 Quad/Dual Gigabit Ethernet Controller"}, + {PCI_VENDOR_ID_INTEL, 0x1509, OK, "Intel", "Unprogrammed 82580 Quad/Dual Gigabit Ethernet Controller"}, {PCI_VENDOR_ID_INTEL, 0x1531, NT, "Intel", "I210 Gigabit Network Connection Unprogrammed"}, {PCI_VENDOR_ID_INTEL, 0x1532, NT, "Intel", "I211 Gigabit Network Connection Unprogrammed"}, {PCI_VENDOR_ID_INTEL, 0x1533, OK, "Intel", "I210 Gigabit Network Connection"}, @@ -95,9 +96,26 @@ {PCI_VENDOR_ID_INTEL, 0x1537, NT, "Intel", "I210 Gigabit Network Connection SERDES Backplane"}, {PCI_VENDOR_ID_INTEL, 0x1538, NT, "Intel", "I210 Gigabit Network Connection SGMII"}, {PCI_VENDOR_ID_INTEL, 0x1539, NT, "Intel", "I211 Gigabit Network Connection"}, + {PCI_VENDOR_ID_INTEL, 0x151f, OK, "Intel", "I350 Gigabit Network Connection Unprogrammed"}, + {PCI_VENDOR_ID_INTEL, 0x1521, OK, "Intel", "I350 Gigabit Network Connection Copper"}, + {PCI_VENDOR_ID_INTEL, 0x1522, NT, "Intel", "I350 Gigabit Network Connection Fiber"}, + {PCI_VENDOR_ID_INTEL, 0x1523, NT, "Intel", "I350 Gigabit Network Connection 1000BASE-KX / 1000BASE-BX backplane"}, + {PCI_VENDOR_ID_INTEL, 0x1522, NT, "Intel", "I350 Gigabit Network Connection External SGMII PHY"}, {0}, }; +static inline bool is_unprog_device(uint16_t device_id) +{ + switch (device_id) + { + case 0x1509: // Unprogrammed 82580 Quad/Dual Gigabit Ethernet Controller + case 0x151f: // I350 Gigabit Network Connection Unprogrammed + return true; + default: + return false; + } +} + static inline bool is_i210(uint16_t device_id) { return (device_id & 0xfff0) == 0x1530; @@ -118,7 +136,7 @@ static int nicintel_ee_probe_82580(struct flashctx *flash) { - if (nicintel_pci->device_id == UNPROG_DEVICE) + if (is_unprog_device(nicintel_pci->device_id)) flash->chip->total_size = 16; /* Fall back to minimum supported size. */ else { uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); @@ -456,7 +474,7 @@ if (!dev) return 1; - uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + uintptr_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); if (!io_base_addr) return 1; @@ -466,7 +484,7 @@ return 1; nicintel_pci = dev; - if ((dev->device_id != UNPROG_DEVICE)) { + if (!is_unprog_device(dev->device_id)) { uint32_t eec = pci_mmio_readl(nicintel_eebar + EEC); /* C.f. 3.3.1.5 for the detection mechanism (maybe? contradicting diff --git a/nicintel_spi.c b/nicintel_spi.c index 1173ef7..09a37dc 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -28,6 +28,9 @@ * * Intel 82599 10 GbE Controller Datasheet (331520) * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/8259… + * + * Intel I350 Gigabit controller Datasheet + * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/eth… */ #include <stdlib.h> @@ -104,6 +107,11 @@ {PCI_VENDOR_ID_INTEL, 0x1538, NT, "Intel", "I210 Gigabit Network Connection SGMII"}, {PCI_VENDOR_ID_INTEL, 0x1539, NT, "Intel", "I211 Gigabit Network Connection"}, + {PCI_VENDOR_ID_INTEL, 0x151f, NT, "Intel", "I350 Gigabit Network Connection Unprogrammed"}, + {PCI_VENDOR_ID_INTEL, 0x1521, NT, "Intel", "I350 Gigabit Network Connection Copper"}, + {PCI_VENDOR_ID_INTEL, 0x1522, NT, "Intel", "I350 Gigabit Network Connection Fiber"}, + {PCI_VENDOR_ID_INTEL, 0x1523, NT, "Intel", "I350 Gigabit Network Connection 1000BASE-KX / 1000BASE-BX backplane"}, + {PCI_VENDOR_ID_INTEL, 0x1522, NT, "Intel", "I350 Gigabit Network Connection External SGMII PHY"}, {0}, }; @@ -252,7 +260,7 @@ if (!dev) return 1; - uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + uintptr_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); if (!io_base_addr) return 1; @@ -266,6 +274,12 @@ MEMMAP_SIZE); if (!nicintel_spibar || nicintel_spi_82599_enable_flash()) return 1; + } else if ((dev->device_id & 0xfff0) == 0x1510 || + (dev->device_id & 0xfff0) == 0x1520) { + nicintel_spibar = rphysmap("Intel I350 Gigabit w/ SPI flash", io_base_addr, + MEMMAP_SIZE); + if (!nicintel_spibar || nicintel_spi_i210_enable_flash()) + return 1; } else { nicintel_spibar = rphysmap("Intel 10 Gigabit NIC w/ SPI flash", io_base_addr + 0x10000, MEMMAP_SIZE); -- To view, visit https://review.coreboot.org/c/flashrom/+/39963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id203d2ce247cf39a8d650887322ccced0151c6a9 Gerrit-Change-Number: 39963 Gerrit-PatchSet: 1 Gerrit-Owner: Martijn Berger Gerrit-MessageType: newchange

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Change in flashrom[master]: Fix a handful of compiler warnings
by Ryan O'Leary (Code Review) Aug. 29, 2026

Aug. 29, 2026

Ryan O'Leary has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/36946 ) Change subject: Fix a handful of compiler warnings ...................................................................... Fix a handful of compiler warnings These warnings (which I believe are not enabled by default) were generated by -Wformat-security and -Wenum-conversion. Change-Id: I3d01f4ff620f4c4111dd675d49ce3254f2360b29 Signed-off-by: Ryan O'Leary <ryanoleary(a)google.com> --- M libflashrom.c M print.c M programmer.h 3 files changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/46/36946/1 diff --git a/libflashrom.c b/libflashrom.c index 0dec22e..b15b5f6 100644 --- a/libflashrom.c +++ b/libflashrom.c @@ -188,7 +188,8 @@ for (; i < boards_known_size; ++i) { supported_boards[i].vendor = binfo[i].vendor; supported_boards[i].name = binfo[i].name; - supported_boards[i].working = binfo[i].working; + supported_boards[i].working = + (enum flashrom_test_state)binfo[i].working; } } else { msg_gerr("Memory allocation error!\n"); @@ -226,8 +227,9 @@ supported_chipsets[i].chipset = chipset[i].device_name; supported_chipsets[i].vendor_id = chipset[i].vendor_id; supported_chipsets[i].chipset_id = chipset[i].device_id; - supported_chipsets[i].status = chipset[i].status; - } + supported_chipsets[i].status = + (enum flashrom_test_state)chipset[i].status; + } } else { msg_gerr("Memory allocation error!\n"); } diff --git a/print.c b/print.c index 596fc53..173c7da 100644 --- a/print.c +++ b/print.c @@ -401,7 +401,7 @@ for (i = 0; i < maxboardlen - strlen(b->name); i++) msg_ginfo(" "); - msg_pinfo(test_state_to_text(b->working)); + msg_pinfo("%s", test_state_to_text(b->working)); for (e = board_matches; e->vendor_name != NULL; e++) { if (strcmp(e->vendor_name, b->vendor) diff --git a/programmer.h b/programmer.h index 5a21b2e..96add05 100644 --- a/programmer.h +++ b/programmer.h @@ -307,7 +307,7 @@ /* cbtable.c */ int cb_parse_table(const char **vendor, const char **model); -int cb_check_image(const uint8_t *bios, unsigned int size); +int cb_check_image(const uint8_t *image, unsigned int size); /* dmi.c */ #if defined(__i386__) || defined(__x86_64__) -- To view, visit https://review.coreboot.org/c/flashrom/+/36946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3d01f4ff620f4c4111dd675d49ce3254f2360b29 Gerrit-Change-Number: 36946 Gerrit-PatchSet: 1 Gerrit-Owner: Ryan O'Leary <ryanoleary(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: util/ich_descriptor_tool: use clang's style suggestion
by Idwer Vollering (Code Review) Aug. 29, 2026

Aug. 29, 2026

Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34945 ) Change subject: util/ich_descriptor_tool: use clang's style suggestion ...................................................................... util/ich_descriptor_tool: use clang's style suggestion Tested on: FreeBSD clang version 8.0.1 (tags/RELEASE_801/final 366581) (based on LLVM 8.0.1) Target: x86_64-unknown-freebsd13.0 Change-Id: Ie80c4c4d70c8ccf357ba8e65f454fc4d4fa8c058 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- M util/ich_descriptors_tool/ich_descriptors_tool.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/45/34945/1 diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 2db0f62..9fcb2ba 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -152,7 +152,7 @@ const char *fn = NULL; const char *csn = NULL; enum ich_chipset cs = CHIPSET_ICH_UNKNOWN; - struct ich_descriptors desc = { 0 }; + struct ich_descriptors desc = { { 0 } }; while ((opt = getopt(argc, argv, "df:c:")) != -1) { switch (opt) { -- To view, visit https://review.coreboot.org/c/flashrom/+/34945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie80c4c4d70c8ccf357ba8e65f454fc4d4fa8c058 Gerrit-Change-Number: 34945 Gerrit-PatchSet: 1 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-MessageType: newchange

4 6

Change in flashrom[master]: realtek_mst_i2c_spi.c: Add bootloader slot param
by Edward O'Callaghan (Code Review) Aug. 29, 2026

Aug. 29, 2026

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/40772 ) Change subject: realtek_mst_i2c_spi.c: Add bootloader slot param ...................................................................... realtek_mst_i2c_spi.c: Add bootloader slot param Add spi_master parameter that allows the user to specify which firmware paritition slot to select in the bootloader upon flashing a new image. BUG=b:155051790 BRANCH=none TEST=builds Change-Id: I1fa6b30ea67e7feb0651dd4b4dc3d5c308fc83c8 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M realtek_mst_i2c_spi.c 1 file changed, 23 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/72/40772/1 diff --git a/realtek_mst_i2c_spi.c b/realtek_mst_i2c_spi.c index 6f7dd70..03c0893 100644 --- a/realtek_mst_i2c_spi.c +++ b/realtek_mst_i2c_spi.c @@ -38,6 +38,7 @@ struct realtek_mst_i2c_spi_data { int fd; + int slot; /* 0: slot A, 1: slot B, -1: undefined slot */ }; static int realtek_mst_i2c_spi_write_data(int fd, uint16_t addr, void *buf, uint16_t len) @@ -355,9 +356,9 @@ return ret; } -static int get_params(int *i2c_bus) +static int get_params(int *i2c_bus, int *slot) { - char *bus_str = NULL; + char *bus_str = NULL, *slot_str = NULL; int ret = SPI_GENERIC_ERROR; bus_str = extract_programmer_param("bus"); @@ -387,9 +388,26 @@ } else { msg_perr("%s: Bus number not specified.\n", __func__); } + + slot_str = extract_programmer_param("slot"); + if (slot_str) { + msg_pinfo("Using bootloader slot %s.\n", slot_str); + switch (slot_str[0]) { + case 'A': *slot = 0; break; + case 'B': *slot = 1; break; + default: + msg_perr("%s: Invalid slot specified.\n", __func__); + *slot = -1; + } + ret = 0; + goto get_params_done; + } + get_params_done: if (bus_str) free(bus_str); + if (slot_str) + free(slot_str); return ret; } @@ -397,9 +415,9 @@ int realtek_mst_i2c_spi_init(void) { int ret = 0; - int i2c_bus = 0; + int i2c_bus = 0, bl_slot = 0; - if (get_params(&i2c_bus)) + if (get_params(&i2c_bus, &bl_slot)) return SPI_GENERIC_ERROR; int fd = i2c_open(i2c_bus, REGISTER_ADDRESS, 0); @@ -428,6 +446,7 @@ } data->fd = fd; + data->slot = bl_slot; ret |= register_shutdown(realtek_mst_i2c_spi_shutdown, data); spi_master_i2c_realtek_mst.data = data; -- To view, visit https://review.coreboot.org/c/flashrom/+/40772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1fa6b30ea67e7feb0651dd4b4dc3d5c308fc83c8 Gerrit-Change-Number: 40772 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 4

Change in flashrom[master]: realtek_mst_i2c_spi.c: Fix wp gpio toggle
by Edward O'Callaghan (Code Review) Aug. 29, 2026

Aug. 29, 2026

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/41125 ) Change subject: realtek_mst_i2c_spi.c: Fix wp gpio toggle ...................................................................... realtek_mst_i2c_spi.c: Fix wp gpio toggle Allow for toggling the GPIO pin 108 that is routed to the WP pin in the reference design. This need not always apply however is largely harmless for a better out-of-the-box experience. BUG=b:152558985,b:148745673 BRANCH=none TEST=builds && A double cycle of erase+write works. Change-Id: I825df3179cdd16f7c7ecf556b5ca29bfe6394346 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M realtek_mst_i2c_spi.c 1 file changed, 8 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/25/41125/1 diff --git a/realtek_mst_i2c_spi.c b/realtek_mst_i2c_spi.c index 64458dd..6cb87fe 100644 --- a/realtek_mst_i2c_spi.c +++ b/realtek_mst_i2c_spi.c @@ -34,6 +34,7 @@ #define MCU_MODE 0x6F #define ENTER_ISP_MODE 0x80 #define START_WRITE_XFER 0xA0 +#define BUF_XFER_STATUS_MASK 0x10 #define WRITE_XFER_STATUS_MASK 0x20 #define MCU_DATA_PORT 0x70 @@ -145,7 +146,7 @@ return ret; } -static int realtek_mst_i2c_spi_disable_protection(int fd) +static int realtek_mst_i2c_spi_toggle_protection(int fd, int enable) { int ret = 0; uint8_t val = 0; @@ -164,8 +165,9 @@ ret |= realtek_mst_i2c_spi_write_register(fd, 0xF5, (val & 0xF8) | 0x01); /* Set pin value to high, 0xFFD7[0] = 1. */ + uint8_t en = enable ? 0x00 : 0x01; ret |= realtek_mst_i2c_spi_read_register(fd, 0xD7, &val); - ret |= realtek_mst_i2c_spi_write_register(fd, 0xD7, (val & 0xFE) | 0x01); + ret |= realtek_mst_i2c_spi_write_register(fd, 0xD7, (val & 0xFE) | en); return ret; } @@ -331,7 +333,7 @@ if (fd < 0) return SPI_GENERIC_ERROR; - ret = realtek_mst_i2c_spi_disable_protection(fd); + ret = realtek_mst_i2c_spi_toggle_protection(fd, 0); if (ret) return ret; @@ -349,7 +351,8 @@ break; /* Wait for empty buffer. */ - ret |= realtek_mst_i2c_spi_wait_command_done(fd, MCU_MODE, 0x10, 0x10, 1); + ret |= realtek_mst_i2c_spi_wait_command_done(fd, MCU_MODE, + BUF_XFER_STATUS_MASK, 0x10, 1); if (ret) break; @@ -362,8 +365,7 @@ break; } - - /* TODO: re-enable the write protection? */ + ret |= realtek_mst_i2c_spi_toggle_protection(fd, 1); return ret; } -- To view, visit https://review.coreboot.org/c/flashrom/+/41125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I825df3179cdd16f7c7ecf556b5ca29bfe6394346 Gerrit-Change-Number: 41125 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 3

Change in flashrom[master]: [WIP] Add uncrustify on/off markers where appropriate
by David Hendricks (Code Review) Aug. 29, 2026

Aug. 29, 2026

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/42555 ) Change subject: [WIP] Add uncrustify on/off markers where appropriate ...................................................................... [WIP] Add uncrustify on/off markers where appropriate Change-Id: I146a32e921d1c828a7d05ebb88373abe22e89053 Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- M board_enable.c M chipset_enable.c M print.c 3 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/55/42555/1 diff --git a/board_enable.c b/board_enable.c index 9cf0103..e95fcff 100644 --- a/board_enable.c +++ b/board_enable.c @@ -2349,6 +2349,7 @@ */ /* Please keep this list alphabetically ordered by vendor/board name. */ +/* *INDENT-OFF* */ const struct board_match board_matches[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier, coreboot id [2], phase, vendor name, board name max_rom_... OK? flash enable */ @@ -2530,6 +2531,7 @@ #endif { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, P3, NULL, NULL, 0, NT, NULL}, /* end marker */ }; +/* *INDENT-ON* */ int selfcheck_board_enables(void) { diff --git a/chipset_enable.c b/chipset_enable.c index 632679c..49f4f2e 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1690,6 +1690,7 @@ #define B_S (BUS_SPI) /* Please keep this list numerically sorted by vendor/device ID. */ +/* *INDENT-OFF* */ const struct penable chipset_enables[] = { #if defined(__i386__) || defined(__x86_64__) {0x1002, 0x4377, B_PFL, OK, "ATI", "SB400", enable_flash_sb400}, @@ -2066,6 +2067,7 @@ #endif {0}, }; +/* *INDENT-ON* */ int chipset_flash_enable(void) { diff --git a/print.c b/print.c index feca45e..06561ec 100644 --- a/print.c +++ b/print.c @@ -515,6 +515,7 @@ #endif /* Please keep this list alphabetically ordered by vendor/board. */ +/* *INDENT-OFF* */ const struct board_info boards_known[] = { #if defined(__i386__) || defined(__x86_64__) B("A-Trend", "ATC-6220", OK, "http://www.motherboard.cz/mb/atrend/atc6220.htm", NULL), @@ -1142,8 +1143,10 @@ {0}, }; +/* *INDENT-ON* */ /* Please keep this list alphabetically ordered by vendor/board. */ +/* *INDENT-OFF* */ const struct board_info laptops_known[] = { #if defined(__i386__) || defined(__x86_64__) B("Acer", "Aspire 1520", OK, "http://support.acer.com/us/en/acerpanam/notebook/0000/Acer/Aspire1520/Aspir…", NULL), @@ -1176,4 +1179,5 @@ {0}, }; +/* *INDENT-ON* */ #endif -- To view, visit https://review.coreboot.org/c/flashrom/+/42555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I146a32e921d1c828a7d05ebb88373abe22e89053 Gerrit-Change-Number: 42555 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

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