October 2020 - flashrom-gerrit

Change in flashrom[master]: linux_spi: Add max_xfer programmer parameter
by David Hendricks (Code Review) Aug. 29, 2026

Aug. 29, 2026

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/42405 ) Change subject: linux_spi: Add max_xfer programmer parameter ...................................................................... linux_spi: Add max_xfer programmer parameter This enables the user to manually set the max transfer size, overriding the value that would otherwise come from sysfs or getpagesize(). Change-Id: Iea868c2e48e61e981472ebcc5e15aaaaf161cab4 Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- M linux_spi.c 1 file changed, 48 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/05/42405/1 diff --git a/linux_spi.c b/linux_spi.c index 1ef8f2b..d804b48 100644 --- a/linux_spi.c +++ b/linux_spi.c @@ -46,7 +46,7 @@ static int fd = -1; #define BUF_SIZE_FROM_SYSFS "/sys/module/spidev/parameters/bufsiz" -static size_t max_kernel_buf_size; +static size_t max_xfer; static int linux_spi_shutdown(void *data); static int linux_spi_send_command(const struct flashctx *flash, unsigned int writecnt, @@ -110,6 +110,51 @@ } free(dev); + p = extract_programmer_param("max_xfer"); + if (p && strlen(p)) { + max_xfer = (uint32_t)strtoul(p, &endp, 0); + if (p == endp || max_xfer == 0) { + msg_perr("%s: invalid max transfer size: %s bytes\n", __func__, p); + free(p); + return 1; + } + } else { + /* Read max buffer size from sysfs, or use page size as fallback. */ + FILE *fp = fopen(BUF_SIZE_FROM_SYSFS, "r"); + if (!fp) { + msg_pwarn("Cannot open %s: %s.\n", BUF_SIZE_FROM_SYSFS, strerror(errno)); + goto out; + } + + char buf[10]; + if (!fgets(buf, sizeof(buf), fp)) { + if (feof(fp)) + msg_pwarn("Cannot read %s: file is empty.\n", BUF_SIZE_FROM_SYSFS); + else + msg_pwarn("Cannot read %s: %s.\n", BUF_SIZE_FROM_SYSFS, strerror(errno)); + fclose(fp); + goto out; + } + fclose(fp); + + long int tmp; + errno = 0; + tmp = strtol(buf, NULL, 0); + if ((tmp < 0) || errno) { + msg_pwarn("Buffer size %ld from %s seems wrong.\n", tmp, BUF_SIZE_FROM_SYSFS); + } else { + msg_pdbg("%s: Using value from %s as max_xfer size.\n", __func__, BUF_SIZE_FROM_SYSFS); + max_xfer = (size_t)tmp; + } + + if (!max_xfer) { + msg_pdbg("%s: Using page size as max_xfer size.\n", __func__); + max_xfer = (size_t)getpagesize(); + } + } + msg_pdbg("%s: max_xfer: %zu\n", __func__, max_xfer); + free(p); + if (register_shutdown(linux_spi_shutdown, NULL)) return 1; /* We rely on the shutdown function for cleanup from here on. */ @@ -133,43 +178,7 @@ return 1; } - /* Read max buffer size from sysfs, or use page size as fallback. */ - FILE *fp; - fp = fopen(BUF_SIZE_FROM_SYSFS, "r"); - if (!fp) { - msg_pwarn("Cannot open %s: %s.\n", BUF_SIZE_FROM_SYSFS, strerror(errno)); - goto out; - } - - char buf[10]; - if (!fgets(buf, sizeof(buf), fp)) { - if (feof(fp)) - msg_pwarn("Cannot read %s: file is empty.\n", BUF_SIZE_FROM_SYSFS); - else - msg_pwarn("Cannot read %s: %s.\n", BUF_SIZE_FROM_SYSFS, strerror(errno)); - goto out; - } - - long int tmp; - errno = 0; - tmp = strtol(buf, NULL, 0); - if ((tmp < 0) || errno) { - msg_pwarn("Buffer size %ld from %s seems wrong.\n", tmp, BUF_SIZE_FROM_SYSFS); - } else { - msg_pdbg("%s: Using value from %s as max buffer size.\n", __func__, BUF_SIZE_FROM_SYSFS); - max_kernel_buf_size = (size_t)tmp; - } - out: - if (fp) - fclose(fp); - - if (!max_kernel_buf_size) { - msg_pdbg("%s: Using page size as max buffer size.\n", __func__); - max_kernel_buf_size = (size_t)getpagesize(); - } - - msg_pdbg("%s: max_kernel_buf_size: %zu\n", __func__, max_kernel_buf_size); register_spi_master(&spi_master_linux); return 0; } @@ -225,13 +234,13 @@ { /* Older kernels use a single buffer for combined input and output data. So account for longest possible command + address, too. */ - return spi_read_chunked(flash, buf, start, len, max_kernel_buf_size - 5); + return spi_read_chunked(flash, buf, start, len, max_xfer - 5); } static int linux_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len) { /* 5 bytes must be reserved for longest possible command + address. */ - return spi_write_chunked(flash, buf, start, len, max_kernel_buf_size - 5); + return spi_write_chunked(flash, buf, start, len, max_xfer - 5); } #endif // CONFIG_LINUX_SPI == 1 -- To view, visit https://review.coreboot.org/c/flashrom/+/42405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iea868c2e48e61e981472ebcc5e15aaaaf161cab4 Gerrit-Change-Number: 42405 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

2 5

Change in flashrom[master]: [WIP] Add uncrustify config
by David Hendricks (Code Review) Aug. 29, 2026

Aug. 29, 2026

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/42556 ) Change subject: [WIP] Add uncrustify config ...................................................................... [WIP] Add uncrustify config Similar to CB:38673, this attempts to add a config file for uncrustify as an alternative to clang-format, which has some limitations as mentioned in the other patch. This adds a config file which is a copy of the linux.cfg file. Newer versions of this patch will tweak the config file as needed for flashrom. Change-Id: Ib6bd3ab49e841768f07c2705f71be66e9308bbca Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- M 82802ab.c M amd_imc.c M at45db.c M atahpt.c M atapromise.c M atavia.c M bitbang_spi.c M board_enable.c M buspirate_spi.c M cbtable.c M ch341a_spi.c M chipdrivers.h M chipset_enable.c M cli_classic.c M cli_common.c M cli_output.c M coreboot_tables.h M custom_baud.c M custom_baud.h M dediprog.c M developerbox_spi.c M digilent_spi.c M dmi.c M drkaiser.c M dummyflasher.c M edi.c M edi.h M en29lv640b.c M ene.h M flash.h M flashchips.c M flashchips.h M flashrom.c M fmap.c M fmap.h M ft2232_spi.c M gfxnvidia.c M helpers.c M hwaccess.c M hwaccess.h M i2c_helper.h M i2c_helper_linux.c M ich_descriptors.c M ich_descriptors.h M ichspi.c M internal.c M it8212.c M it85spi.c M it87spi.c M jedec.c M jlink_spi.c M layout.c M layout.h M libflashrom.c M libflashrom.h M linux_mtd.c M linux_spi.c M lspcon_i2c_spi.c M mcp6x_spi.c M mstarddc_spi.c M ni845x_spi.c M nic3com.c M nicintel.c M nicintel_eeprom.c M nicintel_spi.c M nicnatsemi.c M nicrealtek.c M ogp_spi.c M os.h M pcidev.c M physmap.c M pickit2_spi.c M platform.h M pony_spi.c M print.c M print_wiki.c M processor_enable.c M programmer.c M programmer.h M raiden_debug_spi.c M rayer_spi.c M realtek_mst_i2c_spi.c M satamv.c M satasii.c M sb600spi.c M serial.c M serprog.c M serprog.h M sfdp.c M spi.c M spi.h M spi25.c M spi25_statusreg.c M spi95.c M sst28sf040.c M sst_fwhub.c M stlinkv3_spi.c M udelay.c A uncrustify.cfg M usb_device.c M usb_device.h M usbblaster_spi.c M usbdev.c M w39.c M wbsio_spi.c 105 files changed, 17,980 insertions(+), 17,840 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/56/42556/1 -- To view, visit https://review.coreboot.org/c/flashrom/+/42556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib6bd3ab49e841768f07c2705f71be66e9308bbca Gerrit-Change-Number: 42556 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

4 15

Change in flashrom[master]: git-hooks: Add check-style for pre-commit hook
by David Hendricks (Code Review) Aug. 29, 2026

Aug. 29, 2026

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43602 ) Change subject: git-hooks: Add check-style for pre-commit hook ...................................................................... git-hooks: Add check-style for pre-commit hook This imports check-style and some related lint tools from coreboot for the pre-commit hook: - Add check-style rule to Makefile - Replace the current pre-commit hook with the one from coreboot, omitting lint-stable for the time being. - Import checkpatch.pl, along with certain dependencies (spelling.txt and const_structs.checkpatch) and .checkpatch.conf. - Add .clang-format from CB:38673. Change-Id: Ieb77aa1aa2911e081c69c93929a2f1c4430cd2b9 Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- A .checkpatch.conf A .clang-format M Makefile M util/git-hooks/pre-commit A util/lint/check-style A util/lint/checkpatch.pl A util/lint/const_structs.checkpatch A util/lint/lint-007-checkpatch A util/lint/spelling.txt 9 files changed, 16,655 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/02/43602/1 -- To view, visit https://review.coreboot.org/c/flashrom/+/43602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ieb77aa1aa2911e081c69c93929a2f1c4430cd2b9 Gerrit-Change-Number: 43602 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

4 8

Change in flashrom[master]: ich_descriptors.h: Upstream PCH100+ region comment
by Edward O'Callaghan (Code Review) Aug. 29, 2026

Aug. 29, 2026

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43896 ) Change subject: ich_descriptors.h: Upstream PCH100+ region comment ...................................................................... ich_descriptors.h: Upstream PCH100+ region comment Useful information we should extract out of the chromium fork of flashrom and ingest into upstream. Change-Id: I246c56aa86bb44f27c5934ab5883f555a8307784 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ich_descriptors.h 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/43896/1 diff --git a/ich_descriptors.h b/ich_descriptors.h index c6bf5d8..98535e1 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -234,6 +234,14 @@ :3; }; /* From Skylake on */ + /* + * Flash Descriptor Master Access settings for PCH100+ + * + * [31:20] Master Region Write Access (regions 11:0) + * [19:8] Master Region Read Access (regions 11:0) + * [7:4] Extended Region Write Access (regions 15:12) + * [3:0] Extended Region Read access (regions 15:12) + */ struct { uint32_t ext_read :4, ext_write :4, -- To view, visit https://review.coreboot.org/c/flashrom/+/43896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I246c56aa86bb44f27c5934ab5883f555a8307784 Gerrit-Change-Number: 43896 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 3

Change in flashrom[master]: ichspi.c: Consolidate ich_spi_mode select into a switch stmt
by Edward O'Callaghan (Code Review) Aug. 29, 2026

Aug. 29, 2026

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43894 ) Change subject: ichspi.c: Consolidate ich_spi_mode select into a switch stmt ...................................................................... ichspi.c: Consolidate ich_spi_mode select into a switch stmt Change-Id: I35535c3dac9fa796d204d60e5fc72a7d5f85d706 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ichspi.c 1 file changed, 12 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/94/43894/1 diff --git a/ichspi.c b/ichspi.c index 4dbe69a..1cc1cd7 100644 --- a/ichspi.c +++ b/ichspi.c @@ -2002,16 +2002,18 @@ ich_spi_mode = ich_hwseq; } - if (ich_spi_mode == ich_auto && - (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT || - ich_gen == CHIPSET_300_SERIES_CANNON_POINT)) { - msg_pdbg("Enabling hardware sequencing by default for 100+ series PCH.\n"); - ich_spi_mode = ich_hwseq; - } - - if (ich_spi_mode == ich_auto && ich_gen == CHIPSET_APOLLO_LAKE) { - msg_pdbg("Enabling hardware sequencing by default for Apollo Lake.\n"); - ich_spi_mode = ich_hwseq; + if (ich_spi_mode == ich_auto) { + switch (ich_gen) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_APOLLO_LAKE: + msg_pdbg("Enabling hardware sequencing by default " + "for 100+ series PCH.\n"); + ich_spi_mode = ich_hwseq; + break; + default: + break; + } } if (ich_spi_mode == ich_hwseq) { -- To view, visit https://review.coreboot.org/c/flashrom/+/43894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I35535c3dac9fa796d204d60e5fc72a7d5f85d706 Gerrit-Change-Number: 43894 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 3

Change in ...flashrom[master]: [RFC] cli_classic: Add `--mode (read|write|verify|erase)` parameter
by Nico Huber (Code Review) Aug. 29, 2026

Aug. 29, 2026

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/30979 Change subject: [RFC] cli_classic: Add `--mode (read|write|verify|erase)` parameter ...................................................................... [RFC] cli_classic: Add `--mode (read|write|verify|erase)` parameter In case the user only wants to specify files for specific layout regions, we need a way to set the operation without specifying a file. Instead of making the <filename> argument optional, we can add a new syntax for this particular purpose. This way, we avoid complex command line parsing and can do more sanity checks and provide better error messages. TODO: Update manpage in case this gets accepted. Change-Id: Idfba11ec9991aac423b07f68f7dc45e7bebbb06b Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M cli_classic.c 1 file changed, 42 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/30979/1 diff --git a/cli_classic.c b/cli_classic.c index 324e145..d09a8d1 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -39,7 +39,8 @@ "-z|" #endif "-p <programmername>[:<parameters>] [-c <chipname>]\n" - "[-E|(-r|-w|-v) <file>] [(-l <layoutfile>|--ifd) [-i <imagename>]...] [-n] [-N] [-f]]\n" + "[(-r|-w|-v|-E) <file>|-m (r|w|v|e)] [(-l <layoutfile>|--ifd) [-i <region>]...]\n" + "[-n] [-N] [-f]]\n" "[-V[V[V]]] [-o <logfile>]\n\n", name); printf(" -h | --help print this help text\n" @@ -47,6 +48,8 @@ " -r | --read <file> read flash and save to <file>\n" " -w | --write <file> write <file> to flash\n" " -v | --verify <file> verify flash against <file>\n" + " -m | --mode <operation> for use with --include <region>:<file>,\n" + " specify the mode of operation (r|w|v|e)\n" " -E | --erase erase flash memory\n" " -V | --verbose more verbose output\n" " -c | --chip <chipname> probe only for specified flash chip\n" @@ -123,6 +126,7 @@ {"write", 1, NULL, 'w'}, {"erase", 0, NULL, 'E'}, {"verify", 1, NULL, 'v'}, + {"mode", 1, NULL, 'm'}, {"noverify", 0, NULL, 'n'}, {"noverify-all", 0, NULL, 'N'}, {"chip", 1, NULL, 'c'}, @@ -200,6 +204,25 @@ filename = strdup(optarg); verify_it = 1; break; + case 'm': + if (++operation_specified > 1) { + fprintf(stderr, "More than one operation specified. Aborting.\n"); + cli_classic_abort_usage(); + } + /* check that `optarg` is a prefix of a known operation */ + if (strncmp(optarg, "read", strlen(optarg)) == 0) { + read_it = 1; + } else if (strncmp(optarg, "write", strlen(optarg)) == 0) { + write_it = 1; + } else if (strncmp(optarg, "verify", strlen(optarg)) == 0) { + verify_it = 1; + } else if (strncmp(optarg, "erase", strlen(optarg)) == 0) { + erase_it = 1; + } else { + fprintf(stderr, "Unknown operation specified: '%s'\n", optarg); + cli_classic_abort_usage(); + } + break; case 'n': if (verify_it) { fprintf(stderr, "--verify and --noverify are mutually exclusive. Aborting.\n"); @@ -404,7 +427,7 @@ cli_classic_abort_usage(); } - if ((read_it | write_it | verify_it) && check_filename(filename, "image")) { + if (filename && check_filename(filename, "image")) { cli_classic_abort_usage(); } if (layoutfile && check_filename(layoutfile, "layout")) { @@ -654,6 +677,23 @@ flashrom_flag_set(fill_flash, FLASHROM_FLAG_VERIFY_AFTER_WRITE, !dont_verify_it); flashrom_flag_set(fill_flash, FLASHROM_FLAG_VERIFY_WHOLE_CHIP, !dont_verify_all); + if (!filename && (read_it | write_it | verify_it)) { + if (layout->num_entries == 0) { + msg_gerr("Error: The specified operation requires a file.\n"); + ret = 1; + goto out_shutdown; + } + for (i = 0; i < layout->num_entries; i++) { + if (!layout->entries[i].file) { + msg_gerr("Error: Region \"%s\" requires a file argument.\n", + layout->entries[i].name); + ret = 1; + } + if (ret) + goto out_shutdown; + } + } + /* FIXME: We should issue an unconditional chip reset here. This can be * done once we have a .reset function in struct flashchip. * Give the chip time to settle. -- To view, visit https://review.coreboot.org/c/flashrom/+/30979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Idfba11ec9991aac423b07f68f7dc45e7bebbb06b Gerrit-Change-Number: 30979 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

6 19

Change in flashrom[master]: ichspi.c: WIP Put ich_spibar inside spi_master data feild
by Edward O'Callaghan (Code Review) Aug. 29, 2026

Aug. 29, 2026

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43507 ) Change subject: ichspi.c: WIP Put ich_spibar inside spi_master data feild ...................................................................... ichspi.c: WIP Put ich_spibar inside spi_master data feild Change-Id: I74469a48420eff9ef4f07040dcb2d297143859df Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ichspi.c 1 file changed, 10 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/07/43507/1 diff --git a/ichspi.c b/ichspi.c index 661236e..4ea80c8 100644 --- a/ichspi.c +++ b/ichspi.c @@ -240,6 +240,7 @@ struct ich_spi_data { enum ich_chipset ich_gen; + void *ich_spibar; }; typedef struct _OPCODE { @@ -1753,7 +1754,6 @@ } ich_spi_mode = ich_auto; size_t num_freg, num_pr, reg_pr0; - ich_spibar = spibar; struct ich_spi_data *ich_data = calloc(1, sizeof(struct ich_spi_data)); if (!ich_data) { msg_perr("Unable to allocate space for extra SPI master data.\n"); @@ -1761,6 +1761,7 @@ } ich_data->ich_gen = ich_gen; + ich_data->ich_spibar = spibar; spi_master_ich7.data = ich_data; spi_master_ich9.data = ich_data; @@ -2098,13 +2099,6 @@ /* Not sure if it speaks all these bus protocols. */ internal_buses_supported &= BUS_LPC | BUS_FWH; - struct ich_spi_data ich_data = { - .ich_gen = CHIPSET_ICH7, - }; - spi_master_via.data = &ich_data; - - register_spi_master(&spi_master_via); - msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2)); msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(ich_spibar + 4)); @@ -2135,9 +2129,17 @@ ichspi_lock = 1; } + struct ich_spi_data ich_data = { + .ich_gen = CHIPSET_ICH7, + .ich_spibar = ich_spibar, + }; + spi_master_via.data = &ich_data; + ich_set_bbar(0, ich_data.ich_gen); ich_init_opcodes(ich_data.ich_gen); + register_spi_master(&spi_master_via); + return 0; } -- To view, visit https://review.coreboot.org/c/flashrom/+/43507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I74469a48420eff9ef4f07040dcb2d297143859df Gerrit-Change-Number: 43507 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 2

Change in flashrom[master]: lspcon_i2c_spi.c: Add debug message that shows the active block.
by Shiyu Sun (Code Review) Aug. 29, 2026

Aug. 29, 2026

Shiyu Sun has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/41779 ) Change subject: lspcon_i2c_spi.c: Add debug message that shows the active block. ...................................................................... lspcon_i2c_spi.c: Add debug message that shows the active block. This is all for debug propose to verify A/B update work as expected. BUG=b:148746232 BRANCH=none TEST=flashrom -p lspcon_i2c_spi:bus=7 --flash-size -V verified the related message appears. Signed-off-by: Shiyu Sun <sshiyu(a)chromium.org> Change-Id: I1b3022542f98f114097c6f39254ef4c2cf188c90 --- M lspcon_i2c_spi.c 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/41779/1 diff --git a/lspcon_i2c_spi.c b/lspcon_i2c_spi.c index 7b9f1c0..e5e5dc9 100644 --- a/lspcon_i2c_spi.c +++ b/lspcon_i2c_spi.c @@ -27,6 +27,7 @@ #define REGISTER_ADDRESS (0x94 >> 1) #define PAGE_ADDRESS (0x9e >> 1) +#define ACTIVE_BLOCK_ADDRESS (0x9a >> 1) #define PAGE_SIZE 256 #define MAX_SPI_WAIT_RETRIES 1000 @@ -472,6 +473,27 @@ return ret; } +static void lspcon_i2c_spi_boot_block_info(int fd) +{ + uint8_t block_id = 0; + int ret = 0; + ret |= lspcon_i2c_spi_write_register(fd, 0xbc, 0xc0); + ret |= lspcon_i2c_spi_write_register(fd, 0xbc, 0x40); + ret |= lspcon_i2c_spi_write_register(fd, 0x8e, 0x00); + ret |= lspcon_i2c_spi_write_register(fd, 0x8f, 0x00); + struct timespec wait_10ms = { 0, (unsigned)1e7 }; + nanosleep(&wait_10ms, NULL); + + uint8_t command[] = { 0x0e }; + ret |= lspcon_i2c_spi_write_data(fd, ACTIVE_BLOCK_ADDRESS, command, 1); + ret |= lspcon_i2c_spi_read_data(fd, ACTIVE_BLOCK_ADDRESS, &block_id, 1); + if (ret) { + msg_pdbg("Failed to get LSPCON boot block information.\n"); + } else { + msg_pdbg("LSPCON is booting from block #%d.\n", block_id); + } +} + int lspcon_i2c_spi_init(void) { int lspcon_i2c_spi_bus = get_bus(); @@ -489,6 +511,9 @@ return ret; } + /* Show current activate block information for debug propose. */ + lspcon_i2c_spi_boot_block_info(fd); + struct lspcon_i2c_spi_data *data = calloc(1, sizeof(struct lspcon_i2c_spi_data)); if (!data) { msg_perr("Unable to allocate space for extra SPI master data.\n"); -- To view, visit https://review.coreboot.org/c/flashrom/+/41779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1b3022542f98f114097c6f39254ef4c2cf188c90 Gerrit-Change-Number: 41779 Gerrit-PatchSet: 1 Gerrit-Owner: Shiyu Sun <sshiyu(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: git-hooks: Use check-style in pre-commit hook
by David Hendricks (Code Review) Aug. 29, 2026

Aug. 29, 2026

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44095 ) Change subject: git-hooks: Use check-style in pre-commit hook ...................................................................... git-hooks: Use check-style in pre-commit hook This adds the check-style script to the pre-commit hook and makes some minor changes to warnings printed by the script. Errors are be non-fatal for now. Change-Id: I58b9e64f825de0ca222277a7d16c3904368edfe6 Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- M util/git-hooks/pre-commit M util/lint/check-style 2 files changed, 22 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/95/44095/1 diff --git a/util/git-hooks/pre-commit b/util/git-hooks/pre-commit index dbccb9e..db6b256 100755 --- a/util/git-hooks/pre-commit +++ b/util/git-hooks/pre-commit @@ -1,9 +1,22 @@ #!/bin/sh + # -# A hook script to verify what is about to be committed. -# Called by "git commit" with no arguments. The hook should -# exit with non-zero status after issuing an appropriate message if -# it wants to stop the commit. +# This file is part of the flashrom project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +set -e # -o errexit +set -u # -o nounset # Check for whitespace errors -git diff-index --check --cached HEAD -- || exit 1 +git diff-index --check --cached HEAD -- + +util/lint/check-style diff --git a/util/lint/check-style b/util/lint/check-style index 91ed197..06ced0b 100755 --- a/util/lint/check-style +++ b/util/lint/check-style @@ -89,6 +89,7 @@ printf "Warning: clang-format executable not found.\n" printf "Set the correct path in $(canonicalize_filename "$0").\n" printf "Skipping clang-format style check test.\n" + printf "Changes that violate style guidelines will not be accepted upstream.\n" # exit 1 exit 0 fi @@ -133,12 +134,7 @@ printf "and the clang-format rules:\n\n" cat "$patch" -printf "\nYou can apply these changes with:\n git apply $patch\n" -printf "(may need to be called from the root directory of your repository)\n" - -# FIXME: clang-format is currently unusable, so don't abort the commit. -# printf "Aborting commit. Apply changes and commit again or skip checking with" -# printf " --no-verify (not recommended).\n" -# exit 1 - +printf "\nApply these changes using:\n" +printf " git apply $patch\n" +printf "Changes that violate style guidelines will not be accepted upstream.\n" exit 0 -- To view, visit https://review.coreboot.org/c/flashrom/+/44095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I58b9e64f825de0ca222277a7d16c3904368edfe6 Gerrit-Change-Number: 44095 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: pcidev: Fix typo
by Martijn Berger (Code Review) Aug. 29, 2026

Aug. 29, 2026

Martijn Berger has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39966 ) Change subject: pcidev: Fix typo ...................................................................... pcidev: Fix typo Fix typo Change-Id: If70834715a51dea4111ba56e85df0680ed25c7a4 Signed-off-by: Martijn Berger <martijn.berger(a)gmail.com> --- M pcidev.c M programmer.h 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/66/39966/1 diff --git a/pcidev.c b/pcidev.c index 973acde..38b9380 100644 --- a/pcidev.c +++ b/pcidev.c @@ -30,7 +30,7 @@ TYPE_UNKNOWN }; -int pci_bar_nuber_from_offset(int offset) +int pci_bar_number_from_offset(int offset) { switch (offset) { case PCI_BASE_ADDRESS_0: @@ -63,7 +63,7 @@ headertype = pci_read_byte(dev, PCI_HEADER_TYPE) & 0x7f; msg_pspew("PCI header type 0x%02x\n", headertype); - bar_number = pci_bar_nuber_from_offset(bar); + bar_number = pci_bar_number_from_offset(bar); if (PCI_LIB_VERSION >= 0x030500 && bar_number > -1) { addr = dev->base_addr[bar_number]; diff --git a/programmer.h b/programmer.h index 5d4c1d7..42f646b 100644 --- a/programmer.h +++ b/programmer.h @@ -190,7 +190,7 @@ // FIXME: This needs to be local, not global(?) extern struct pci_access *pacc; int pci_init_common(void); -int pci_bar_nuber_from_offset(int offset); +int pci_bar_number_from_offset(int offset); uintptr_t pcidev_readbar(struct pci_dev *dev, int bar); struct pci_dev *pcidev_init(const struct dev_entry *devs, int bar); /* rpci_write_* are reversible writes. The original PCI config space register -- To view, visit https://review.coreboot.org/c/flashrom/+/39966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If70834715a51dea4111ba56e85df0680ed25c7a4 Gerrit-Change-Number: 39966 Gerrit-PatchSet: 1 Gerrit-Owner: Martijn Berger Gerrit-MessageType: newchange

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