July 2019 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: flashchips: Add missing N25Q/MT25Q 1.8v variants
by Jacob Creedon (Code Review) Nov. 10, 2019

Nov. 10, 2019

Jacob Creedon has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34491 ) Change subject: flashchips: Add missing N25Q/MT25Q 1.8v variants ...................................................................... flashchips: Add missing N25Q/MT25Q 1.8v variants This adds missing 1.8v variants for the 256Mb and 512Mb capacities for N25Q and MT25Q devices. Only the MT25QU512 has been tested in hardware, all other variants added are marked as untested. Signed-off-by: Jacob Creedon <jcreedon(a)google.com> Change-Id: I85630e4f6c0aa3b261f9871b7d363dad278b997e --- M flashchips.c 1 file changed, 178 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/91/34491/1 diff --git a/flashchips.c b/flashchips.c index d25f7a2..5424a04 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10545,6 +10545,46 @@ { .vendor = "Micron/Numonyx/ST", + .name = "N25Q256..1E", /* ..1E = 1.8V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q256__1E, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32768 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + }, + + { + .vendor = "Micron/Numonyx/ST", .name = "N25Q256..3E", /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, @@ -10585,6 +10625,46 @@ { .vendor = "Micron/Numonyx/ST", + .name = "N25Q512..1E", /* ..1E = 1.8V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q512__1E, + .total_size = 65536, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 16384} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 16384} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 1024} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 1024} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {65536 * 1024, 1} }, + .block_erase = spi_block_erase_c4, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + }, + + { + .vendor = "Micron/Numonyx/ST", .name = "N25Q512..3E", /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, @@ -10674,6 +10754,55 @@ { .vendor = "Micron", + .name = "MT25QU256", /* U = 1.8V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q256__1E, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32768 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, { + .eraseblocks = { {32768 * 1024, 1} }, + .block_erase = spi_block_erase_60, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + }, + + { + .vendor = "Micron", .name = "MT25QL512", /* L = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, @@ -10722,6 +10851,55 @@ }, { + .vendor = "Micron", + .name = "MT25QU512", /* U = 1.8V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q512__1E, + .total_size = 65536, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 16384} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 16384} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 2048} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 2048} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 1024} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 1024} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {65536 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, { + .eraseblocks = { {65536 * 1024, 1} }, + .block_erase = spi_block_erase_60, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + }, + + { .vendor = "MoselVitelic", .name = "V29C51000B", .bustype = BUS_PARALLEL, -- To view, visit https://review.coreboot.org/c/flashrom/+/34491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I85630e4f6c0aa3b261f9871b7d363dad278b997e Gerrit-Change-Number: 34491 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Creedon <jcreedon(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips: Add N25Q00A devices
by Jacob Creedon (Code Review) Oct. 14, 2019

Oct. 14, 2019

Jacob Creedon has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34521 ) Change subject: flashchips: Add N25Q00A devices ...................................................................... flashchips: Add N25Q00A devices This adds the 1Gb N25Q00A device in both the 1.8v and 3v variants. This is implemented from the datasheet and is marked as untested. Signed-off-by: Jacob Creedon <jcreedon(a)google.com> Change-Id: If36880f37746c95a97c8122a8f2fd0aecede5e8e --- M flashchips.c 1 file changed, 80 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/21/34521/1 diff --git a/flashchips.c b/flashchips.c index 021ae6c..5d292f1 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10304,6 +10304,86 @@ { .vendor = "Micron/Numonyx/ST", + .name = "N25Q00A..1G", /* ..1G = 1.8V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q00A__1G, + .total_size = 131072, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32768 * 1024, 4} }, + .block_erase = spi_block_erase_c4, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + }, + + { + .vendor = "Micron/Numonyx/ST", + .name = "N25Q00A..3G", /* ..3G = 3V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q00A__3G, + .total_size = 131072, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32768 * 1024, 4} }, + .block_erase = spi_block_erase_c4, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Micron/Numonyx/ST", .name = "N25Q016", .bustype = BUS_SPI, .manufacture_id = ST_ID, -- To view, visit https://review.coreboot.org/c/flashrom/+/34521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If36880f37746c95a97c8122a8f2fd0aecede5e8e Gerrit-Change-Number: 34521 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Creedon <jcreedon(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips: Fix part names for N25Q512 and N25Q00A
by Jacob Creedon (Code Review) Oct. 14, 2019

Oct. 14, 2019

Jacob Creedon has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34520 ) Change subject: flashchips: Fix part names for N25Q512 and N25Q00A ...................................................................... flashchips: Fix part names for N25Q512 and N25Q00A For the N25Q512 and N25Q00A, the 1G and 3G are used instead of 1E and 3E to represent 1.8v and 3v respectively. Signed-off-by: Jacob Creedon <jcreedon(a)google.com> Change-Id: I289c33f7293f47b9449907350654cd6183c778d4 --- M flashchips.c M flashchips.h 2 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/20/34520/1 diff --git a/flashchips.c b/flashchips.c index 3a0da8d..021ae6c 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10625,10 +10625,10 @@ { .vendor = "Micron/Numonyx/ST", - .name = "N25Q512..1E", /* ..1E = 1.8V, uniform 64KB/4KB blocks/sectors */ + .name = "N25Q512..1G", /* ..1G = 1.8V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, - .model_id = ST_N25Q512__1E, + .model_id = ST_N25Q512__1G, .total_size = 65536, .page_size = 256, /* supports SFDP */ @@ -10665,10 +10665,10 @@ { .vendor = "Micron/Numonyx/ST", - .name = "N25Q512..3E", /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */ + .name = "N25Q512..3G", /* ..3G = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, - .model_id = ST_N25Q512__3E, + .model_id = ST_N25Q512__3G, .total_size = 65536, .page_size = 256, /* supports SFDP */ @@ -10708,7 +10708,7 @@ .name = "MT25QL01G", /* L = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, - .model_id = ST_N25Q00A__3E, + .model_id = ST_N25Q00A__3G, .total_size = 131072, .page_size = 256, /* supports SFDP */ @@ -10754,7 +10754,7 @@ .name = "MT25QU01G", /* U = 1.8V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, - .model_id = ST_N25Q00A__1E, + .model_id = ST_N25Q00A__1G, .total_size = 131072, .page_size = 256, /* supports SFDP */ @@ -11070,7 +11070,7 @@ .name = "MT25QL512", /* L = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, - .model_id = ST_N25Q512__3E, + .model_id = ST_N25Q512__3G, .total_size = 65536, .page_size = 256, /* supports SFDP */ @@ -11119,7 +11119,7 @@ .name = "MT25QU512", /* U = 1.8V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, - .model_id = ST_N25Q512__1E, + .model_id = ST_N25Q512__1G, .total_size = 65536, .page_size = 256, /* supports SFDP */ diff --git a/flashchips.h b/flashchips.h index e53e0df..0dcf735 100644 --- a/flashchips.h +++ b/flashchips.h @@ -866,10 +866,10 @@ #define ST_N25Q128__1E 0xBB18 /* N25Q128/MT25QU128, 1.8V, (uniform sectors expected) */ #define ST_N25Q256__3E 0xBA19 /* N25Q256/MT25QL256, 3.0V, (uniform sectors expected) */ #define ST_N25Q256__1E 0xBB19 /* N25Q256/MT25QU256, 1.8V, (uniform sectors expected) */ -#define ST_N25Q512__3E 0xBA20 /* N25Q512/MT25QL512, 3.0V, (uniform sectors expected) */ -#define ST_N25Q512__1E 0xBB20 /* N25Q512/MT25QU512, 1.8V, (uniform sectors expected) */ -#define ST_N25Q00A__3E 0xBA21 /* N25Q00A/MT25QL01G, 3.0V, (uniform sectors expected) */ -#define ST_N25Q00A__1E 0xBB21 /* N25Q00A/MT25QU01G, 1.8V, (uniform sectors expected) */ +#define ST_N25Q512__3G 0xBA20 /* N25Q512/MT25QL512, 3.0V, (uniform sectors expected) */ +#define ST_N25Q512__1G 0xBB20 /* N25Q512/MT25QU512, 1.8V, (uniform sectors expected) */ +#define ST_N25Q00A__3G 0xBA21 /* N25Q00A/MT25QL01G, 3.0V, (uniform sectors expected) */ +#define ST_N25Q00A__1G 0xBB21 /* N25Q00A/MT25QU01G, 1.8V, (uniform sectors expected) */ #define ST_MT25QL02G 0xBA22 /* MT25QL02G, 3.0V, (uniform sectors expected) */ #define ST_MT25QU02G 0xBB22 /* MT25QU02G, 1.8V, (uniform sectors expected) */ #define ST_NP5Q032 0xDA16 /* Phase-change memory (PCM), 3V */ -- To view, visit https://review.coreboot.org/c/flashrom/+/34520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I289c33f7293f47b9449907350654cd6183c778d4 Gerrit-Change-Number: 34520 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Creedon <jcreedon(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips: Add missing MT25Q capacities
by Jacob Creedon (Code Review) Oct. 14, 2019

Oct. 14, 2019

Jacob Creedon has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34492 ) Change subject: flashchips: Add missing MT25Q capacities ...................................................................... flashchips: Add missing MT25Q capacities This adds the 128Mb, 1Gb, and 2Gb capacities of the MT25Q devices. All of these are implemented via the datasheet and should work but are untested in hardware. Signed-off-by: Jacob Creedon <jcreedon(a)google.com> Change-Id: Ice6ea9426361afc25d4b731e2e3079edf234fdda --- M flashchips.c M flashchips.h 2 files changed, 274 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/92/34492/1 diff --git a/flashchips.c b/flashchips.c index 5424a04..6b553fb 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10705,6 +10705,270 @@ { .vendor = "Micron", + .name = "MT25QL01G", /* L = 3V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q00A__3E, + .total_size = 131072, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 4096} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 4096} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {131072 * 1024, 1} }, + .block_erase = spi_block_erase_c4, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Micron", + .name = "MT25QU01G", /* U = 1.8V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q00A__1E, + .total_size = 131072, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 4096} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 4096} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {131072 * 1024, 1} }, + .block_erase = spi_block_erase_c4, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + }, + + { + .vendor = "Micron", + .name = "MT25QL02G", /* L = 3V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_MT25QL02G, + .total_size = 262144, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 65536} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 65536} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 8192} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 8192} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 4096} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 4096} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {262144 * 1024, 1} }, + .block_erase = spi_block_erase_c4, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Micron", + .name = "ST_MT25QU02G", /* U = 1.8V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q00A__1E, + .total_size = 262144, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 65536} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 65536} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 8192} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 8192} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 4096} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 4096} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {262144 * 1024, 1} }, + .block_erase = spi_block_erase_c4, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + }, + + { + .vendor = "Micron", + .name = "MT25QU128", /* U = 1.8V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q128__1E, + .total_size = 16384, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16384 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, { + .eraseblocks = { {16384 * 1024, 1} }, + .block_erase = spi_block_erase_60, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + }, + + { + .vendor = "Micron", + .name = "MT25QL128", /* L = 3V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q128__3E, + .total_size = 16384, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16384 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, { + .eraseblocks = { {16384 * 1024, 1} }, + .block_erase = spi_block_erase_60, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Micron", .name = "MT25QL256", /* L = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, diff --git a/flashchips.h b/flashchips.h index 006b95e..e53e0df 100644 --- a/flashchips.h +++ b/flashchips.h @@ -862,13 +862,16 @@ #define ST_N25Q032__1E 0xBB16 /* N25Q032, 1.8V, (uniform sectors expected) */ #define ST_N25Q064__3E 0xBA17 /* N25Q064, 3.0V, (uniform sectors expected) */ #define ST_N25Q064__1E 0xBB17 /* N25Q064, 1.8V, (uniform sectors expected) */ -#define ST_N25Q128__3E 0xBA18 /* N25Q128, 3.0V, (uniform sectors expected) */ -#define ST_N25Q128__1E 0xBB18 /* N25Q128, 1.8V, (uniform sectors expected) */ -#define ST_N25Q256__3E 0xBA19 /* N25Q256, 3.0V, (uniform sectors expected) */ -#define ST_N25Q256__1E 0xBB19 /* N25Q256, 1.8V, (uniform sectors expected) */ -#define ST_N25Q512__3E 0xBA20 /* N25Q512, 3.0V, (uniform sectors expected) */ -#define ST_N25Q512__1E 0xBB20 /* N25Q512, 1.8V, (uniform sectors expected) */ -#define ST_N25Q00A__3E 0xBA21 /* N25Q00A, 3.0V, (uniform sectors expected) */ +#define ST_N25Q128__3E 0xBA18 /* N25Q128/MT25QL128, 3.0V, (uniform sectors expected) */ +#define ST_N25Q128__1E 0xBB18 /* N25Q128/MT25QU128, 1.8V, (uniform sectors expected) */ +#define ST_N25Q256__3E 0xBA19 /* N25Q256/MT25QL256, 3.0V, (uniform sectors expected) */ +#define ST_N25Q256__1E 0xBB19 /* N25Q256/MT25QU256, 1.8V, (uniform sectors expected) */ +#define ST_N25Q512__3E 0xBA20 /* N25Q512/MT25QL512, 3.0V, (uniform sectors expected) */ +#define ST_N25Q512__1E 0xBB20 /* N25Q512/MT25QU512, 1.8V, (uniform sectors expected) */ +#define ST_N25Q00A__3E 0xBA21 /* N25Q00A/MT25QL01G, 3.0V, (uniform sectors expected) */ +#define ST_N25Q00A__1E 0xBB21 /* N25Q00A/MT25QU01G, 1.8V, (uniform sectors expected) */ +#define ST_MT25QL02G 0xBA22 /* MT25QL02G, 3.0V, (uniform sectors expected) */ +#define ST_MT25QU02G 0xBB22 /* MT25QU02G, 1.8V, (uniform sectors expected) */ #define ST_NP5Q032 0xDA16 /* Phase-change memory (PCM), 3V */ #define ST_NP5Q064 0xDA17 /* Phase-change memory (PCM), 3V */ #define ST_NP5Q128 0xDA18 /* Phase-change memory (PCM), 3V */ -- To view, visit https://review.coreboot.org/c/flashrom/+/34492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ice6ea9426361afc25d4b731e2e3079edf234fdda Gerrit-Change-Number: 34492 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Creedon <jcreedon(a)google.com> Gerrit-MessageType: newchange

3 8

Change in flashrom[master]: Add support for M95M02-A125
by Konstantin Grudnev (Code Review) Oct. 4, 2019

Oct. 4, 2019

Konstantin Grudnev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34496 ) Change subject: Add support for M95M02-A125 ...................................................................... Add support for M95M02-A125 Automotive 2 Mbit (256KiB) serial SPI bus EEPROM PREW tested successfully with use of ch341a programmer on Linux host 5.2.0-1-MANJARO x86_64 Signed-off-by: Konstantin Grudnev <grudnevkv(a)gmail.com> Change-Id: Ic29cd9051c7eac4822d620c299834134f987f01b --- M chipdrivers.h M flashchips.c M flashchips.h M spi.h M spi25.c 5 files changed, 102 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/34496/1 diff --git a/chipdrivers.h b/chipdrivers.h index e380878..0b4435c 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -34,6 +34,7 @@ int probe_spi_res1(struct flashctx *flash); int probe_spi_res2(struct flashctx *flash); int probe_spi_res3(struct flashctx *flash); +int probe_spi_st95(struct flashctx *flash); int probe_spi_at25f(struct flashctx *flash); int spi_write_enable(struct flashctx *flash); int spi_write_disable(struct flashctx *flash); @@ -51,6 +52,7 @@ int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_db(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_dc(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_emulation(struct flashctx *flash, unsigned int addr, unsigned int blocklen); erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode); int spi_chip_write_1(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int spi_nbyte_read(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); diff --git a/flashchips.c b/flashchips.c index 166af6a..44875c6 100644 --- a/flashchips.c +++ b/flashchips.c @@ -14104,6 +14104,33 @@ }, { + .vendor = "ST", + .name = "M95M02", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M95M02, + .total_size = 256, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_st95, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { { 256 * 1024, 1 } }, + .block_erase = spi_block_erase_emulation, + } + }, + + .printlock = spi_prettyprint_status_register_bp1_srwd, + .unlock = spi_disable_blockprotect_bp1_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2500, 5500}, + }, + + { .vendor = "Sanyo", .name = "LE25FU106B", .bustype = BUS_SPI, diff --git a/flashchips.h b/flashchips.h index 006b95e..d1eed91 100644 --- a/flashchips.h +++ b/flashchips.h @@ -851,6 +851,12 @@ #define ST_M58WR032KT 0x8814 #define ST_M58WR064KB 0x8811 #define ST_M58WR064KT 0x8810 + +/* 00h ST Manufacturer code ST_ID*/ +/* 01h SPI Family code 0x00*/ +/* 02h Memory Density code ST_M95XXX */ +#define ST_M95M02 0x0012 /* ST M95XXX 2Mbit (256KiB) */ + #define ST_MT28GU01G___1 0x88B0 #define ST_MT28GU01G___2 0x88B1 #define ST_MT28GU256___1 0x8901 diff --git a/spi.h b/spi.h index 0073c71..9f199f3 100644 --- a/spi.h +++ b/spi.h @@ -28,6 +28,12 @@ /* INSIZE may be 0x04 for some chips*/ #define JEDEC_RDID_INSIZE 0x03 +/* Some ST M95X model */ +#define ST_M95_RDID 0x83 +#define ST_M95_RDID_OUTSIZE 0x04 /* 8b op, 24bit addr where size >64KiB */ +#define ST_M95_RDID_INSIZE 0x03 + + /* Some Atmel AT25F* models have bit 3 as don't care bit in commands */ #define AT25F_RDID 0x15 /* 0x15 or 0x1d */ #define AT25F_RDID_OUTSIZE 0x01 diff --git a/spi25.c b/spi25.c index 2a1d492..ec35585 100644 --- a/spi25.c +++ b/spi25.c @@ -21,6 +21,7 @@ #include <stddef.h> #include <string.h> #include <stdbool.h> +#include <stdlib.h> #include "flash.h" #include "flashchips.h" #include "chipdrivers.h" @@ -262,6 +263,32 @@ return 1; } +/* Only used for some stm95080 and higher chip. */ +int probe_spi_st95(struct flashctx *flash) +{ + /* ST_M95_RDID_OUTSIZE depends on size of the flash and + * not all ST_M95XXX have RDID + */ + static const unsigned char cmd[ST_M95_RDID_OUTSIZE] = {ST_M95_RDID}; + unsigned char readarr[ST_M95_RDID_INSIZE]; + uint32_t id1, id2; + + spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr); + + id1 = readarr[0]; // manufacture id + id2 = readarr[2]; // model id + + msg_ginfo("RDID[%s: id1 0x%02x, id2 0x%02x, " + "L 0x%02x, M 0x%02x, H 0x%02x]\n", + __func__, flash->chip->manufacture_id, flash->chip->model_id, + readarr[0], readarr[1], readarr[2]); + + if (id1 == flash->chip->manufacture_id && id2 == flash->chip->model_id) + return 1; + + return 0; +} + /* Only used for some Atmel chips. */ int probe_spi_at25f(struct flashctx *flash) { @@ -440,6 +467,13 @@ return result ? result : status; } +static int spi_nbyte_program(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len) +{ + const bool native_4ba = flash->chip->feature_bits & FEATURE_4BA_WRITE && spi_master_4ba(flash); + const uint8_t op = native_4ba ? JEDEC_BYTE_PROGRAM_4BA : JEDEC_BYTE_PROGRAM; + return spi_write_cmd(flash, op, native_4ba, addr, bytes, len, 10); +} + static int spi_chip_erase_60(struct flashctx *flash) { /* This usually takes 1-85s, so wait in 1s steps. */ @@ -577,6 +611,33 @@ return spi_write_cmd(flash, 0xdc, true, addr, NULL, 0, 100 * 1000); } +/* some chips don't have erase function */ +int spi_block_erase_emulation(struct flashctx *flash, unsigned int addr, unsigned int blocklen) +{ + unsigned int i; + const unsigned int erase_len = flash->chip->page_size; + uint8_t *erased_contents = NULL; + int result = 0; + + erased_contents = (uint8_t*) malloc(erase_len * sizeof(uint8_t)); + if (!erased_contents) { + msg_cerr("Out of memory!\n"); + return 1; + } + + memset(erased_contents, ERASED_VALUE(flash), erase_len * sizeof(uint8_t)); + msg_cinfo("\n"); + for (i = addr; i < blocklen; i+=erase_len) { + if (spi_nbyte_program(flash, i, erased_contents, erase_len)) { + result = 1; + break; + } + } + + free(erased_contents); + return result; +} + erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode) { switch(opcode){ @@ -619,13 +680,6 @@ } } -static int spi_nbyte_program(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len) -{ - const bool native_4ba = flash->chip->feature_bits & FEATURE_4BA_WRITE && spi_master_4ba(flash); - const uint8_t op = native_4ba ? JEDEC_BYTE_PROGRAM_4BA : JEDEC_BYTE_PROGRAM; - return spi_write_cmd(flash, op, native_4ba, addr, bytes, len, 10); -} - int spi_nbyte_read(struct flashctx *flash, unsigned int address, uint8_t *bytes, unsigned int len) { -- To view, visit https://review.coreboot.org/c/flashrom/+/34496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic29cd9051c7eac4822d620c299834134f987f01b Gerrit-Change-Number: 34496 Gerrit-PatchSet: 1 Gerrit-Owner: Konstantin Grudnev <grudnevkv(a)gmail.com> Gerrit-MessageType: newchange

2 13

Change in flashrom[master]: tree: Enable -Wwrite-strings
by Jacob Garber (Code Review) Oct. 4, 2019

Oct. 4, 2019

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34577 ) Change subject: tree: Enable -Wwrite-strings ...................................................................... tree: Enable -Wwrite-strings When compiling, this warning gives string literals the type const char[] to help catch accidental modification (which is undefined behaviour). There currently aren't any instances of this in flashrom, so let's enable this warning to keep it that way. This requires adding const qualifiers to the declarations of several variables that work with string literals. Change-Id: I62d9bc194938a0c9a0e4cdff7ced8ea2e14cc1bc Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M Makefile M buspirate_spi.c M cli_classic.c M dmi.c M pony_spi.c M util/ich_descriptors_tool/ich_descriptors_tool.c 6 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/77/34577/1 diff --git a/Makefile b/Makefile index 545e84a..1a20933 100644 --- a/Makefile +++ b/Makefile @@ -30,7 +30,7 @@ DIFF = diff PREFIX ?= /usr/local MANDIR ?= $(PREFIX)/share/man -CFLAGS ?= -Os -Wall -Wshadow -Wmissing-prototypes +CFLAGS ?= -Os -Wall -Wshadow -Wmissing-prototypes -Wwrite-strings EXPORTDIR ?= . RANLIB ?= ranlib PKG_CONFIG ?= pkg-config diff --git a/buspirate_spi.c b/buspirate_spi.c index fb066c2..bc6776b 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -112,7 +112,7 @@ return 0; } -static int buspirate_wait_for_string(unsigned char *buf, char *key) +static int buspirate_wait_for_string(unsigned char *buf, const char *key) { unsigned int keylen = strlen(key); int ret; diff --git a/cli_classic.c b/cli_classic.c index 0591bfe..428efc1 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -77,7 +77,7 @@ exit(1); } -static int check_filename(char *filename, char *type) +static int check_filename(char *filename, const char *type) { if (!filename || (filename[0] == '\0')) { fprintf(stderr, "Error: No %s file specified.\n", type); diff --git a/dmi.c b/dmi.c index ae90f7c..6132b47 100644 --- a/dmi.c +++ b/dmi.c @@ -69,7 +69,7 @@ static const struct { uint8_t type; uint8_t is_laptop; - char *name; + const char *name; } dmi_chassis_types[] = { {0x01, 2, "Other"}, {0x02, 2, "Unknown"}, diff --git a/pony_spi.c b/pony_spi.c index 6c03308..ed9d326 100644 --- a/pony_spi.c +++ b/pony_spi.c @@ -115,7 +115,7 @@ int i, data_out; char *arg = NULL; enum pony_type type = TYPE_SI_PROG; - char *name; + const char *name; int have_device = 0; int have_prog = 0; diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 2c7966d..768401e 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -111,7 +111,7 @@ printf("\n"); } -static void usage(char *argv[], char *error) +static void usage(char *argv[], const char *error) { if (error != NULL) { fprintf(stderr, "%s\n", error); -- To view, visit https://review.coreboot.org/c/flashrom/+/34577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I62d9bc194938a0c9a0e4cdff7ced8ea2e14cc1bc Gerrit-Change-Number: 34577 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

6 8

Change in flashrom[master]: Removed strndup because it is not available in MingW
by Miklós Márton (Code Review) Oct. 4, 2019

Oct. 4, 2019

Miklós Márton has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34621 ) Change subject: Removed strndup because it is not available in MingW ...................................................................... Removed strndup because it is not available in MingW Signed-off-by: Miklós Márton <martonmiklosqdev(a)gmail.com> Change-Id: If418080bffff1f5961cacf2a300ea9c666682458 --- M libflashrom.c 1 file changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/21/34621/1 diff --git a/libflashrom.c b/libflashrom.c index af62002..a1c0a9c 100644 --- a/libflashrom.c +++ b/libflashrom.c @@ -371,6 +371,7 @@ struct flashctx *const flashctx, const struct fmap *const fmap) { int i; + size_t len; struct flashrom_layout *l = get_global_layout(); if (!fmap || !l) @@ -385,8 +386,15 @@ l->entries[l->num_entries].start = fmap->areas[i].offset; l->entries[l->num_entries].end = fmap->areas[i].offset + fmap->areas[i].size - 1; l->entries[l->num_entries].included = false; - l->entries[l->num_entries].name = - strndup((const char *)fmap->areas[i].name, FMAP_STRLEN); + // MingW does not have strndup + len = strlen((const char *)fmap->areas[i].name); + if (len > (FMAP_STRLEN - 1)) + len = (FMAP_STRLEN - 1); + l->entries[l->num_entries].name = malloc(len + 1); + strncpy(l->entries[l->num_entries].name, + (const char *)fmap->areas[i].name, + len); + l->entries[l->num_entries].name[len] = '\0'; if (!l->entries[l->num_entries].name) { msg_gerr("Error adding layout entry: %s\n", strerror(errno)); return 1; -- To view, visit https://review.coreboot.org/c/flashrom/+/34621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If418080bffff1f5961cacf2a300ea9c666682458 Gerrit-Change-Number: 34621 Gerrit-PatchSet: 1 Gerrit-Owner: Miklós Márton <martonmiklosqdev(a)gmail.com> Gerrit-MessageType: newchange

2 8

Change in ...flashrom[master]: flashchips.c: Sort file by vendor and model
by Alan Green (Code Review) Aug. 22, 2019

Aug. 22, 2019

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/33931 Change subject: flashchips.c: Sort file by vendor and model ...................................................................... flashchips.c: Sort file by vendor and model For self-consistency, and to allow tools to assist with merging the chromium fork of flashrom, sort the entries of flashchips.c. The file is already largely sorted, though deviations have crept in over time. This is a non-clever mostly ASCII-order sorting. It is not intended to be permanent. Post-merge we can explore options such as breaking apart flashchips.c into per-vendor files or directories. Change-Id: I75a99583592526f60ba5264e92391bf8b1213b20 --- M flashchips.c 1 file changed, 5,510 insertions(+), 5,510 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/31/33931/1 -- To view, visit https://review.coreboot.org/c/flashrom/+/33931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I75a99583592526f60ba5264e92391bf8b1213b20 Gerrit-Change-Number: 33931 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

5 19

Change in flashrom[master]: chipset_enable: Mark Intel/CM246 as DEP
by Nico Huber (Code Review) Aug. 8, 2019

Aug. 8, 2019

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34073 ) Change subject: chipset_enable: Mark Intel/CM246 as DEP ...................................................................... chipset_enable: Mark Intel/CM246 as DEP The usual ME-lock limitations apply, so this is DEP instead of OK. Tested on Siemens/Field PG M6, and also regression tested on Apollo Lake and Skylake. Flashrom works fine, and logs and descriptor dumps look good. Also, register and descriptor output agree on the flash layout and permissions. Change-Id: I40db4773f127bec63e377e1d2ab402b47edf9a61 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/34073/1 diff --git a/chipset_enable.c b/chipset_enable.c index 3773158..f75f94d 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2044,7 +2044,7 @@ {0x8086, 0xa30a, B_S, NT, "Intel", "C242", enable_flash_pch300}, {0x8086, 0xa30c, B_S, NT, "Intel", "QM370", enable_flash_pch300}, {0x8086, 0xa30d, B_S, NT, "Intel", "HM370", enable_flash_pch300}, - {0x8086, 0xa30e, B_S, NT, "Intel", "CM246", enable_flash_pch300}, + {0x8086, 0xa30e, B_S, DEP, "Intel", "CM246", enable_flash_pch300}, #endif {0}, }; -- To view, visit https://review.coreboot.org/c/flashrom/+/34073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I40db4773f127bec63e377e1d2ab402b47edf9a61 Gerrit-Change-Number: 34073 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

2 3

Change in flashrom[master]: chipset_enable: Add support for Cannon Lake U Premium
by Matt DeVillier (Code Review) Aug. 8, 2019

Aug. 8, 2019

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34076 ) Change subject: chipset_enable: Add support for Cannon Lake U Premium ...................................................................... chipset_enable: Add support for Cannon Lake U Premium Add support for Cannon Lake U Premium (CFL-U/WHL-U). Same as discrete 300-series CNP PCH. Tested on out-of-tree WHL-U board. Change-Id: I8a318d63cf408a3b2cec436a3fa6e26cf8552ead Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M chipset_enable.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/76/34076/1 diff --git a/chipset_enable.c b/chipset_enable.c index 3773158..e880e73 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1995,6 +1995,7 @@ {0x8086, 0x9d53, B_S, NT, "Intel", "Kaby Lake U Base", enable_flash_pch100}, {0x8086, 0x9d56, B_S, NT, "Intel", "Kaby Lake Y Premium", enable_flash_pch100}, {0x8086, 0x9d58, B_S, NT, "Intel", "Kaby Lake U Premium", enable_flash_pch100}, + {0x8086, 0x9d84, B_S, NT, "Intel", "Cannon Lake U Premium", enable_flash_pch300}, {0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100}, {0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100}, {0x8086, 0xa143, B_S, NT, "Intel", "H110", enable_flash_pch100}, -- To view, visit https://review.coreboot.org/c/flashrom/+/34076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8a318d63cf408a3b2cec436a3fa6e26cf8552ead Gerrit-Change-Number: 34076 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

2 7

Change in flashrom[master]: ichspi: Add support for discrete Cannon Lake PCHs
by Nico Huber (Code Review) Aug. 8, 2019

Aug. 8, 2019

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34072 ) Change subject: ichspi: Add support for discrete Cannon Lake PCHs ...................................................................... ichspi: Add support for discrete Cannon Lake PCHs Only minor differences in the Firmware Descriptor, compared to their predecessors. We extend our check on the `ICCRIBA` field in the descriptor to dis- tinguish it from older generation. Alas, the `freq_read` field was repurposed, so we can't use it as sanity check any more. Change-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipset_enable.c M ich_descriptors.c M ich_descriptors.h M ichspi.c M util/ich_descriptors_tool/ich_descriptors_tool.c 5 files changed, 87 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/72/34072/1 diff --git a/chipset_enable.c b/chipset_enable.c index 4b0bab5..3773158 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2035,16 +2035,16 @@ {0x8086, 0xa2c9, B_S, NT, "Intel", "Z370", enable_flash_pch100}, {0x8086, 0xa2d2, B_S, NT, "Intel", "X299", enable_flash_pch100}, {0x8086, 0x5ae8, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, - {0x8086, 0xa303, B_S, BAD, "Intel", "H310", enable_flash_pch300}, - {0x8086, 0xa304, B_S, BAD, "Intel", "H370", enable_flash_pch300}, - {0x8086, 0xa305, B_S, BAD, "Intel", "Z390", enable_flash_pch300}, - {0x8086, 0xa306, B_S, BAD, "Intel", "Q370", enable_flash_pch300}, - {0x8086, 0xa308, B_S, BAD, "Intel", "B360", enable_flash_pch300}, - {0x8086, 0xa309, B_S, BAD, "Intel", "C246", enable_flash_pch300}, - {0x8086, 0xa30a, B_S, BAD, "Intel", "C242", enable_flash_pch300}, - {0x8086, 0xa30c, B_S, BAD, "Intel", "QM370", enable_flash_pch300}, - {0x8086, 0xa30d, B_S, BAD, "Intel", "HM370", enable_flash_pch300}, - {0x8086, 0xa30e, B_S, BAD, "Intel", "CM246", enable_flash_pch300}, + {0x8086, 0xa303, B_S, NT, "Intel", "H310", enable_flash_pch300}, + {0x8086, 0xa304, B_S, NT, "Intel", "H370", enable_flash_pch300}, + {0x8086, 0xa305, B_S, NT, "Intel", "Z390", enable_flash_pch300}, + {0x8086, 0xa306, B_S, NT, "Intel", "Q370", enable_flash_pch300}, + {0x8086, 0xa308, B_S, NT, "Intel", "B360", enable_flash_pch300}, + {0x8086, 0xa309, B_S, NT, "Intel", "C246", enable_flash_pch300}, + {0x8086, 0xa30a, B_S, NT, "Intel", "C242", enable_flash_pch300}, + {0x8086, 0xa30c, B_S, NT, "Intel", "QM370", enable_flash_pch300}, + {0x8086, 0xa30d, B_S, NT, "Intel", "HM370", enable_flash_pch300}, + {0x8086, 0xa30e, B_S, NT, "Intel", "CM246", enable_flash_pch300}, #endif {0}, }; diff --git a/ich_descriptors.c b/ich_descriptors.c index a757add..9653d60 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -45,6 +45,7 @@ case CHIPSET_APOLLO_LAKE: return 6; case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: return 16; case CHIPSET_100_SERIES_SUNRISE_POINT: return 10; @@ -106,7 +107,7 @@ "5 series Ibex Peak", "6 series Cougar Point", "7 series Panther Point", "8 series Lynx Point", "Baytrail", "8 series Lynx Point LP", "8 series Wellsburg", "9 series Wildcat Point", "9 series Wildcat Point LP", "100 series Sunrise Point", - "C620 series Lewisburg", "Apollo Lake", + "C620 series Lewisburg", "300 series Cannon Point", "Apollo Lake", }; if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names)) cs = 0; @@ -198,6 +199,7 @@ case CHIPSET_9_SERIES_WILDCAT_POINT_LP: case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: { uint8_t size_enc; if (idx == 0) { @@ -265,6 +267,7 @@ return freq_str[0][value]; case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: return freq_str[1][value]; case CHIPSET_APOLLO_LAKE: return freq_str[2][value]; @@ -281,6 +284,7 @@ switch (cs) { case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: has_flill1 = true; break; @@ -398,7 +402,8 @@ msg_pdbg2("\n"); msg_pdbg2("--- Details ---\n"); - if (cs == CHIPSET_100_SERIES_SUNRISE_POINT) { + if (cs == CHIPSET_100_SERIES_SUNRISE_POINT || + cs == CHIPSET_300_SERIES_CANNON_POINT) { const char *const master_names[] = { "BIOS", "ME", "GbE", "unknown", "EC", }; @@ -408,14 +413,26 @@ return; } - msg_pdbg2(" FD BIOS ME GbE Pltf Reg5 Reg6 Reg7 EC Reg9\n"); + size_t num_regions; + msg_pdbg2(" FD BIOS ME GbE Pltf Reg5 Reg6 Reg7 EC Reg9"); + if (cs == CHIPSET_100_SERIES_SUNRISE_POINT) { + num_regions = 10; + msg_pdbg2("\n"); + } else { + num_regions = 16; + msg_pdbg2(" RegA RegB RegC RegD RegE RegF\n"); + } for (i = 0; i < nm; i++) { size_t j; msg_pdbg2("%-4s", master_names[i]); - for (j = 0; j < 10; j++) + for (j = 0; j < min(num_regions, 12); j++) msg_pdbg2(" %c%c ", desc->master.mstr[i].read & (1 << j) ? 'r' : ' ', desc->master.mstr[i].write & (1 << j) ? 'w' : ' '); + for (; j < num_regions; j++) + msg_pdbg2(" %c%c ", + desc->master.mstr[i].ext_read & (1 << (j - 12)) ? 'r' : ' ', + desc->master.mstr[i].ext_write & (1 << (j - 12)) ? 'w' : ' '); msg_pdbg2("\n"); } } else if (cs == CHIPSET_C620_SERIES_LEWISBURG) { @@ -919,10 +936,15 @@ return CHIPSET_8_SERIES_LYNX_POINT; msg_pwarn("Peculiar firmware descriptor, assuming Wildcat Point compatibility.\n"); return CHIPSET_9_SERIES_WILDCAT_POINT; - } else if (content->NM == 6) { - return CHIPSET_C620_SERIES_LEWISBURG; + } else if (content->ICCRIBA < 0x34) { + if (content->NM == 6) + return CHIPSET_C620_SERIES_LEWISBURG; + else + return CHIPSET_100_SERIES_SUNRISE_POINT; } else { - return CHIPSET_100_SERIES_SUNRISE_POINT; + if (content->ICCRIBA > 0x34) + msg_pwarn("Unknown firmware descriptor, assuming 300 series compatibility.\n"); + return CHIPSET_300_SERIES_CANNON_POINT; } } @@ -938,6 +960,9 @@ const enum ich_chipset guess = guess_ich_chipset_from_content(content); switch (guess) { + case CHIPSET_300_SERIES_CANNON_POINT: + /* `freq_read` was repurposed, so can't check on it any more. */ + return guess; case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_APOLLO_LAKE: @@ -1089,6 +1114,7 @@ case CHIPSET_9_SERIES_WILDCAT_POINT_LP: case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; @@ -1123,6 +1149,7 @@ switch (cs) { case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: mmio_le_writel(control, spibar + PCH100_REG_FDOC); return mmio_le_readl(spibar + PCH100_REG_FDOD); diff --git a/ich_descriptors.h b/ich_descriptors.h index 4225286..c6bf5d8 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -170,8 +170,9 @@ * Chipset/Generation #FLREGs width (bits) * ICH8 .. Panther Point/7 5 13 * Lynx Point/8 .. Wildcat Point/9 7 15 - * Sunrise Point/100 .. 10 15 + * Sunrise Point/100 .. 200 Series 10 15 * Lewisburg/100 .. 16 15 + * Cannon Point/300 .. 16 15 */ union { uint32_t FLREGs[MAX_NUM_FLREGS]; /* Flash Descriptor Regions */ @@ -234,9 +235,10 @@ }; /* From Skylake on */ struct { - uint32_t :8, - read :12, - write :12; + uint32_t ext_read :4, + ext_write :4, + read :12, + write :12; } mstr[MAX_NUM_MASTERS]; }; }; diff --git a/ichspi.c b/ichspi.c index e1ede60..68bd5d7 100644 --- a/ichspi.c +++ b/ichspi.c @@ -395,15 +395,25 @@ pprint_reg(HSFS, FDONE, reg_val, ", "); pprint_reg(HSFS, FCERR, reg_val, ", "); pprint_reg(HSFS, AEL, reg_val, ", "); - if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT && - ich_generation != CHIPSET_C620_SERIES_LEWISBURG) { + switch (ich_generation) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: + break; + default: pprint_reg(HSFS, BERASE, reg_val, ", "); + break; } pprint_reg(HSFS, SCIP, reg_val, ", "); - if (ich_generation == CHIPSET_100_SERIES_SUNRISE_POINT || - ich_generation == CHIPSET_C620_SERIES_LEWISBURG) { + switch (ich_generation) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: pprint_reg(HSFS, PRR34_LOCKDN, reg_val, ", "); pprint_reg(HSFS, WRSDIS, reg_val, ", "); + break; + default: + break; } pprint_reg(HSFS, FDOPSS, reg_val, ", "); pprint_reg(HSFS, FDV, reg_val, ", "); @@ -414,12 +424,16 @@ { msg_pdbg("HSFC: "); pprint_reg(HSFC, FGO, reg_val, ", "); - if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT && - ich_generation != CHIPSET_C620_SERIES_LEWISBURG) { - pprint_reg(HSFC, FCYCLE, reg_val, ", "); - } else { + switch (ich_generation) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: _pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", "); pprint_reg(HSFC, WET, reg_val, ", "); + break; + default: + pprint_reg(HSFC, FCYCLE, reg_val, ", "); + break; } pprint_reg(HSFC, FDBC, reg_val, ", "); pprint_reg(HSFC, SME, reg_val, "\n"); @@ -1567,9 +1581,10 @@ static enum ich_access_protection ich9_handle_frap(uint32_t frap, int i) { const int rwperms_unknown = ARRAY_SIZE(access_names); - static const char *const region_names[6] = { + static const char *const region_names[] = { "Flash Descriptor", "BIOS", "Management Engine", "Gigabit Ethernet", "Platform Data", "Device Expansion", + "BIOS2", "unknown", "EC/BMC", }; const char *const region_name = i < ARRAY_SIZE(region_names) ? region_names[i] : "unknown"; @@ -1724,6 +1739,7 @@ switch (ich_generation) { case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: num_pr = 6; /* Includes GPR0 */ reg_pr0 = PCH100_REG_FPR0; @@ -1754,6 +1770,7 @@ case CHIPSET_C620_SERIES_LEWISBURG: num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */ break; + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: num_freg = 16; break; @@ -1848,6 +1865,7 @@ switch (ich_gen) { case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: tmp = mmio_readl(ich_spibar + PCH100_REG_DLOCK); msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp); @@ -1921,6 +1939,7 @@ case CHIPSET_ICH8: case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_BAYTRAIL: break; @@ -1952,6 +1971,7 @@ case CHIPSET_ICH8: case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: break; default: @@ -1981,8 +2001,10 @@ ich_spi_mode = ich_hwseq; } - if (ich_spi_mode == ich_auto && ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT) { - msg_pdbg("Enabling hardware sequencing by default for 100 series PCH.\n"); + if (ich_spi_mode == ich_auto && + (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT || + ich_gen == CHIPSET_300_SERIES_CANNON_POINT)) { + msg_pdbg("Enabling hardware sequencing by default for 100+ series PCH.\n"); ich_spi_mode = ich_hwseq; } diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 2c7966d..2db0f62 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -133,6 +133,7 @@ "\t- \"8\" or \"lynx\" for Intel's 8 series chipsets.\n" "\t- \"9\" or \"wildcat\" for Intel's 9 series chipsets.\n" "\t- \"100\" or \"sunrise\" for Intel's 100 series chipsets.\n" +"\t- \"300\" or \"cannon\" for Intel's 300 series chipsets.\n" "If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n" "the GbE blob that is required to initialize the GbE are also dumped to files.\n", argv[0], argv[0]); @@ -221,6 +222,9 @@ else if ((strcmp(csn, "100") == 0) || (strcmp(csn, "sunrise") == 0)) cs = CHIPSET_100_SERIES_SUNRISE_POINT; + else if ((strcmp(csn, "300") == 0) || + (strcmp(csn, "cannon") == 0)) + cs = CHIPSET_300_SERIES_CANNON_POINT; else if (strcmp(csn, "apollo") == 0) cs = CHIPSET_APOLLO_LAKE; } -- To view, visit https://review.coreboot.org/c/flashrom/+/34072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02 Gerrit-Change-Number: 34072 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 3

Change in flashrom[master]: chipset_enable: Add support for discrete Cannon Lake PCHs
by Nico Huber (Code Review) Aug. 8, 2019

Aug. 8, 2019

Hello Thomas Heijligen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/flashrom/+/34071 to review the following change. Change subject: chipset_enable: Add support for discrete Cannon Lake PCHs ...................................................................... chipset_enable: Add support for discrete Cannon Lake PCHs The Cannon Lake "300 Series" PCHs [1,2] share the register layout of the Skylake "100 Series". Mark them as BAD until `ichspi.c` is adapted. [1] Intel® 300 Series and Intel® C240 Seri Chipset Family Platform Controller Hub Datasheet - Volume 1 of 2 Revison 4 (Dec 2018) Document Number 337347 [2] Intel® 300 Series Chipset Families Platform Controller Hu Datasheet - Volume 2 of 2 Revision 2? (Oct 2018) Document Number 337348 Change-Id: If0b54799d5b93169ee660409bad57ae14677340c Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipset_enable.c M programmer.h 2 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/71/34071/1 diff --git a/chipset_enable.c b/chipset_enable.c index 08feda5..4b0bab5 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -598,6 +598,7 @@ break; case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: reg_name = "BIOS_SPI_BC"; gcs = pci_read_long(dev, 0xdc); @@ -692,6 +693,7 @@ case CHIPSET_9_SERIES_WILDCAT_POINT_LP: case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: boot_straps = boot_straps_pch8_lp; break; case CHIPSET_APOLLO_LAKE: @@ -719,6 +721,7 @@ break; case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: bbs = (gcs >> 6) & 0x1; break; @@ -947,6 +950,11 @@ return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_C620_SERIES_LEWISBURG); } +static int enable_flash_pch300(struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_300_SERIES_CANNON_POINT); +} + static int enable_flash_apl(struct pci_dev *const dev, const char *const name) { return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE); @@ -2027,6 +2035,16 @@ {0x8086, 0xa2c9, B_S, NT, "Intel", "Z370", enable_flash_pch100}, {0x8086, 0xa2d2, B_S, NT, "Intel", "X299", enable_flash_pch100}, {0x8086, 0x5ae8, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, + {0x8086, 0xa303, B_S, BAD, "Intel", "H310", enable_flash_pch300}, + {0x8086, 0xa304, B_S, BAD, "Intel", "H370", enable_flash_pch300}, + {0x8086, 0xa305, B_S, BAD, "Intel", "Z390", enable_flash_pch300}, + {0x8086, 0xa306, B_S, BAD, "Intel", "Q370", enable_flash_pch300}, + {0x8086, 0xa308, B_S, BAD, "Intel", "B360", enable_flash_pch300}, + {0x8086, 0xa309, B_S, BAD, "Intel", "C246", enable_flash_pch300}, + {0x8086, 0xa30a, B_S, BAD, "Intel", "C242", enable_flash_pch300}, + {0x8086, 0xa30c, B_S, BAD, "Intel", "QM370", enable_flash_pch300}, + {0x8086, 0xa30d, B_S, BAD, "Intel", "HM370", enable_flash_pch300}, + {0x8086, 0xa30e, B_S, BAD, "Intel", "CM246", enable_flash_pch300}, #endif {0}, }; diff --git a/programmer.h b/programmer.h index f4e8b46..4a51243 100644 --- a/programmer.h +++ b/programmer.h @@ -626,6 +626,7 @@ CHIPSET_9_SERIES_WILDCAT_POINT_LP, CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) variants */ CHIPSET_C620_SERIES_LEWISBURG, + CHIPSET_300_SERIES_CANNON_POINT, CHIPSET_APOLLO_LAKE, }; -- To view, visit https://review.coreboot.org/c/flashrom/+/34071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If0b54799d5b93169ee660409bad57ae14677340c Gerrit-Change-Number: 34071 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

4 5

Change in flashrom[master]: flashchips: Split MT25Q from N25Q
by Jacob Creedon (Code Review) Aug. 5, 2019

Aug. 5, 2019

Jacob Creedon has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34488 ) Change subject: flashchips: Split MT25Q from N25Q ...................................................................... flashchips: Split MT25Q from N25Q The MT25Q is the successor to the N25Q from Micron/Numonyx/ST. The MT25Q is almost entirely backwards compatible with the N25Q series, however, the MT25Q has additional subsector erase commands available, and there are differences in stacked devices in the higher capacity variants. The N25Q devices are left with "Micron/Numonyx/ST" as the vendor and MT25Q devices are set with "Micron" as the vendor. Signed-off-by: Jacob Creedon <jcreedon(a)google.com> Change-Id: I9d79978544b19cf9acd5f3ea6196cf6f3b3435ef --- M flashchips.c 1 file changed, 82 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/88/34488/1 diff --git a/flashchips.c b/flashchips.c index 166af6a..e6116ae 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10544,8 +10544,88 @@ }, { + .vendor = "Micron/Numonyx/ST", + .name = "N25Q256..3E", /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q256__3E, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32768 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Micron/Numonyx/ST", + .name = "N25Q512..3E", /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q512__3E, + .total_size = 65536, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 16384} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 16384} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 1024} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 1024} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {65536 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { .vendor = "Micron", - .name = "N25Q256..3E/MT25QL256", /* ..3E/L = 3V, uniform 64KB/4KB blocks/sectors */ + .name = "MT25QL256", /* L = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, .model_id = ST_N25Q256__3E, @@ -10585,7 +10665,7 @@ { .vendor = "Micron", - .name = "N25Q512..3E/MT25QL512", /* ..3E/L = 3V, uniform 64KB/4KB blocks/sectors */ + .name = "MT25QL512", /* L = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, .model_id = ST_N25Q512__3E, -- To view, visit https://review.coreboot.org/c/flashrom/+/34488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I9d79978544b19cf9acd5f3ea6196cf6f3b3435ef Gerrit-Change-Number: 34488 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Creedon <jcreedon(a)google.com> Gerrit-MessageType: newchange

3 10

Change in flashrom[master]: flashchips: Add missing MT25Q erase commands
by Jacob Creedon (Code Review) Aug. 5, 2019

Aug. 5, 2019

Jacob Creedon has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34490 ) Change subject: flashchips: Add missing MT25Q erase commands ...................................................................... flashchips: Add missing MT25Q erase commands This adds additional 32KiB subsecor erase commands 0x5c and 0x52 and an additional bulk erase command of 0x60. Signed-off-by: Jacob Creedon <jcreedon(a)google.com> Change-Id: I5307c4b96cbd62203f5bad0c94737180fda621aa --- M flashchips.c 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/90/34490/1 diff --git a/flashchips.c b/flashchips.c index 78873eb..d25f7a2 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10646,6 +10646,12 @@ .eraseblocks = { {4 * 1024, 8192} }, .block_erase = spi_block_erase_20, }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52, + }, { .eraseblocks = { {64 * 1024, 512} }, .block_erase = spi_block_erase_dc, }, { @@ -10654,6 +10660,9 @@ }, { .eraseblocks = { {32768 * 1024, 1} }, .block_erase = spi_block_erase_c7, + }, { + .eraseblocks = { {32768 * 1024, 1} }, + .block_erase = spi_block_erase_60, } }, .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ @@ -10686,6 +10695,12 @@ .eraseblocks = { {4 * 1024, 16384} }, .block_erase = spi_block_erase_20, }, { + .eraseblocks = { {32 * 1024, 2048} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 2048} }, + .block_erase = spi_block_erase_52, + }, { .eraseblocks = { {64 * 1024, 1024} }, .block_erase = spi_block_erase_dc, }, { @@ -10694,6 +10709,9 @@ }, { .eraseblocks = { {65536 * 1024, 1} }, .block_erase = spi_block_erase_c7, + }, { + .eraseblocks = { {65536 * 1024, 1} }, + .block_erase = spi_block_erase_60, } }, .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ -- To view, visit https://review.coreboot.org/c/flashrom/+/34490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5307c4b96cbd62203f5bad0c94737180fda621aa Gerrit-Change-Number: 34490 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Creedon <jcreedon(a)google.com> Gerrit-MessageType: newchange

2 4

Change in flashrom[master]: flashchips: Fix N25Q512 bulk erase
by Jacob Creedon (Code Review) Aug. 5, 2019

Aug. 5, 2019

Jacob Creedon has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34489 ) Change subject: flashchips: Fix N25Q512 bulk erase ...................................................................... flashchips: Fix N25Q512 bulk erase The N25Q is a stacked device, so it requires 0xC4 to perform a die erase. Signed-off-by: Jacob Creedon <jcreedon(a)google.com> Change-Id: Ib408fbe5633abd8b657e3907142b997e88b33f84 --- M flashchips.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/89/34489/1 diff --git a/flashchips.c b/flashchips.c index e6116ae..78873eb 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10613,7 +10613,7 @@ .block_erase = spi_block_erase_d8, }, { .eraseblocks = { {65536 * 1024, 1} }, - .block_erase = spi_block_erase_c7, + .block_erase = spi_block_erase_c4, } }, .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ -- To view, visit https://review.coreboot.org/c/flashrom/+/34489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib408fbe5633abd8b657e3907142b997e88b33f84 Gerrit-Change-Number: 34489 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Creedon <jcreedon(a)google.com> Gerrit-MessageType: newchange

3 5

Change in flashrom[master]: Add support for continuous SPI reads
by Edward O'Callaghan (Code Review) Aug. 3, 2019

Aug. 3, 2019

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34584 ) Change subject: Add support for continuous SPI reads ...................................................................... Add support for continuous SPI reads Forward port the original patch from Duncan Laurie <dlaurie(a)chromium.org> in commit 06ffd5263892061c5ebf46e52b7878786cf2cece so that it fits for upstream consumption. This patch adds support for "unbounded reads" which are for continous reads to a SPI flash chip instead of reading in page size blocks. This speeds up the flash process over FTDI by quite a bit, testing the read of a 16MB part it goes from 2m11s to 0m15s. Change-Id: I804545aeb1b827ffdd41b21024fd618475e8263a Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M chipdrivers.h M flash.h M spi.c M spi25.c 4 files changed, 40 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/84/34584/1 diff --git a/chipdrivers.h b/chipdrivers.h index e380878..77e1943 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -55,6 +55,7 @@ int spi_chip_write_1(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int spi_nbyte_read(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); int spi_read_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize); +int spi_read_unbound(struct flashchip *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize); int spi_write_chunked(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize); int spi_enter_4ba(struct flashctx *flash); int spi_exit_4ba(struct flashctx *flash); diff --git a/flash.h b/flash.h index b60a980..981f88b 100644 --- a/flash.h +++ b/flash.h @@ -143,6 +143,8 @@ #define ERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff) +#define FEATURE_UNBOUND_READ (1 << 19) + enum test_state { OK = 0, NT = 1, /* Not tested */ diff --git a/spi.c b/spi.c index 489baf3..23f4cfe 100644 --- a/spi.c +++ b/spi.c @@ -75,13 +75,18 @@ unsigned int len) { unsigned int max_data = flash->mst->spi.max_data_read; + int rc; if (max_data == MAX_DATA_UNSPECIFIED) { msg_perr("%s called, but SPI read chunk size not defined " "on this hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); return 1; } - return spi_read_chunked(flash, buf, start, len, max_data); + if (flash->feature_bits & FEATURE_UNBOUND_READ) + rc = spi_read_unbound(flash, buf, start, len, max_data); + else + rc = spi_read_chunked(flash, buf, start, len, max_data); + return rc; } int default_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len) diff --git a/spi25.c b/spi25.c index 2a1d492..3327110 100644 --- a/spi25.c +++ b/spi25.c @@ -659,6 +659,37 @@ } /* + * Read a part of the flash chip. + * Ignore pages and read the data continuously, the only bound is the chunksize. + */ +int spi_read_unbound(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize) +{ + int rc = 0; + unsigned int i; + + for (i = start; i < (start + len); i += chunksize) { + int chunk_status = 0; + unsigned int toread = min(chunksize, start + len - i); + + chunk_status = spi_nbyte_read(flash, i, buf + (i - start), toread); + if (chunk_status) { + if (ignore_error(chunk_status)) { + /* fill this chunk with 0xff bytes and + let caller know about the error */ + memset(buf + (i - start), 0xff, toread); + rc = chunk_status; + continue; + } else { + rc = chunk_status; + break; + } + } + } + + return rc; +} + +/* * Write a part of the flash chip. * FIXME: Use the chunk code from Michael Karcher instead. * Each page is written separately in chunks with a maximum size of chunksize. -- To view, visit https://review.coreboot.org/c/flashrom/+/34584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I804545aeb1b827ffdd41b21024fd618475e8263a Gerrit-Change-Number: 34584 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

2 4

Change in flashrom[master]: flashchips.c: Mark AMD Am29F010A/B as TEST_OK_PRE,
by Alan Green (Code Review) Aug. 3, 2019

Aug. 3, 2019

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34534 ) Change subject: flashchips.c: Mark AMD Am29F010A/B as TEST_OK_PRE, ...................................................................... flashchips.c: Mark AMD Am29F010A/B as TEST_OK_PRE, The AMD Am29F010 was marked TEST_OK_PRE in chromium repo change SHA d217d1219ccaa43a01cd75475409183bd5714410. There are no other differences in the definition of this chip. This is the only change from the Chromium repo to be upstreamed for AMD chips. Signed-off-by: Alan Green <avg(a)google.com> Change-Id: I7fa10d33b42c09d035c611535a54592083c4eaa0 --- M flashchips.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/34534/1 diff --git a/flashchips.c b/flashchips.c index b859bf6..15c33c1 100644 --- a/flashchips.c +++ b/flashchips.c @@ -156,7 +156,7 @@ .total_size = 128, .page_size = 16 * 1024, .feature_bits = FEATURE_ADDR_2AA | FEATURE_EITHER_RESET, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PRE, .probe = probe_jedec, .probe_timing = TIMING_ZERO, .block_erasers = -- To view, visit https://review.coreboot.org/c/flashrom/+/34534 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7fa10d33b42c09d035c611535a54592083c4eaa0 Gerrit-Change-Number: 34534 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

4 5

Change in flashrom[master]: flashchips.c: Mark Intel 82802AB as TEST_OK_PREW
by Alan Green (Code Review) Aug. 3, 2019

Aug. 3, 2019

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34533 ) Change subject: flashchips.c: Mark Intel 82802AB as TEST_OK_PREW ...................................................................... flashchips.c: Mark Intel 82802AB as TEST_OK_PREW Intel 82802AB Was marked as TEST_OK_PREW in the Chromium fork in their SHA312d9ff1fb1ccb5533a867d4248eb1be95ec3fbc. The definitions in the fork and here in upstream are otherwise substantially similar. Signed-off-by: Alan Green <avg(a)google.com> Change-Id: Iec75f0b1c35000308601fa6fdd63ab1738d0ef94 --- M flashchips.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/33/34533/1 diff --git a/flashchips.c b/flashchips.c index 166af6a..b859bf6 100644 --- a/flashchips.c +++ b/flashchips.c @@ -7671,7 +7671,7 @@ .total_size = 512, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_82802ab, .probe_timing = TIMING_IGNORED, /* routine does not use probe_timing (82802ab.c) */ .block_erasers = -- To view, visit https://review.coreboot.org/c/flashrom/+/34533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iec75f0b1c35000308601fa6fdd63ab1738d0ef94 Gerrit-Change-Number: 34533 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

4 4

Change in flashrom[master]: Fix -Wunused-parameter issues
by Nico Huber (Code Review) July 31, 2019

July 31, 2019

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/30410 ) Change subject: Fix -Wunused-parameter issues ...................................................................... Patch Set 5: > I personally think "(void)flash;" looks really ugly It really does. Though, I try not to judge it by asthetics but the potential benefit of the warning. Does anybody recall or imagine bugs that would be prevented by -Wunused-parameter? -- To view, visit https://review.coreboot.org/c/flashrom/+/30410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If831398c91e9f49bd5216a03ed4caaa2a7ab02bd Gerrit-Change-Number: 30410 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Richard Hughes <richard(a)hughsie.com> Gerrit-Reviewer: Stefan T <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 31 Jul 2019 08:49:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in flashrom[master]: Fix -Wunused-parameter issues
by Richard Hughes (Code Review) July 31, 2019

July 31, 2019

Richard Hughes has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/30410 ) Change subject: Fix -Wunused-parameter issues ...................................................................... Patch Set 5: I personally think "(void)flash;" looks really ugly -- I'd rather just see Wunused-parameter disabled. -- To view, visit https://review.coreboot.org/c/flashrom/+/30410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If831398c91e9f49bd5216a03ed4caaa2a7ab02bd Gerrit-Change-Number: 30410 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Richard Hughes <richard(a)hughsie.com> Gerrit-Reviewer: Stefan T <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 31 Jul 2019 08:33:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in flashrom[master]: Fix -Wunused-parameter issues
by Nico Huber (Code Review) July 31, 2019

July 31, 2019

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/30410 ) Change subject: Fix -Wunused-parameter issues ...................................................................... Patch Set 5: The idea here is to enable -Wextra eventually. The alternative obviously is to keep -Wunused-parameter disabled. Does anyone have a preference? -- To view, visit https://review.coreboot.org/c/flashrom/+/30410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If831398c91e9f49bd5216a03ed4caaa2a7ab02bd Gerrit-Change-Number: 30410 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Richard Hughes <richard(a)hughsie.com> Gerrit-Reviewer: Stefan T <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 31 Jul 2019 08:30:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in flashrom[master]: chipset_enable: Fix recent -Wmissing-field-initializer trouble
by Nico Huber (Code Review) July 31, 2019

July 31, 2019

Hello Jacob Garber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/flashrom/+/34551 to review the following change. Change subject: chipset_enable: Fix recent -Wmissing-field-initializer trouble ...................................................................... chipset_enable: Fix recent -Wmissing-field-initializer trouble Change-Id: Idb2ec4a767bdc8fdfab6a78b6448e76ea3388a32 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M chipset_enable.c 1 file changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/51/34551/1 diff --git a/chipset_enable.c b/chipset_enable.c index 44e3e22..7fb06ee 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -631,13 +631,13 @@ }; static const struct boot_straps boot_straps_EP80579[] = { { "SPI", BUS_SPI }, - { "reserved" }, - { "reserved" }, + { "reserved", 0 }, + { "reserved", 0 }, { "LPC", BUS_LPC | BUS_FWH } }; static const struct boot_straps boot_straps_ich7_nm10[] = - { { "reserved" }, + { { "reserved", 0 }, { "SPI", BUS_SPI }, - { "PCI" }, + { "PCI", 0 }, { "LPC", BUS_LPC | BUS_FWH } }; static const struct boot_straps boot_straps_tunnel_creek[] = { { "SPI", BUS_SPI }, @@ -645,29 +645,29 @@ static const struct boot_straps boot_straps_ich8910[] = { { "SPI", BUS_SPI }, { "SPI", BUS_SPI }, - { "PCI" }, + { "PCI", 0 }, { "LPC", BUS_LPC | BUS_FWH } }; static const struct boot_straps boot_straps_pch567[] = { { "LPC", BUS_LPC | BUS_FWH }, - { "reserved" }, - { "PCI" }, + { "reserved", 0 }, + { "PCI", 0 }, { "SPI", BUS_SPI } }; static const struct boot_straps boot_straps_pch89_baytrail[] = { { "LPC", BUS_LPC | BUS_FWH }, - { "reserved" }, - { "reserved" }, + { "reserved", 0 }, + { "reserved", 0 }, { "SPI", BUS_SPI } }; static const struct boot_straps boot_straps_pch8_lp[] = { { "SPI", BUS_SPI }, { "LPC", BUS_LPC | BUS_FWH } }; static const struct boot_straps boot_straps_apl[] = { { "SPI", BUS_SPI }, - { "reserved" } }; + { "reserved", 0 } }; static const struct boot_straps boot_straps_unknown[] = - { { "unknown" }, - { "unknown" }, - { "unknown" }, - { "unknown" } }; + { { "unknown", 0 }, + { "unknown", 0 }, + { "unknown", 0 }, + { "unknown", 0 } }; const struct boot_straps *boot_straps; switch (ich_generation) { -- To view, visit https://review.coreboot.org/c/flashrom/+/34551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Idb2ec4a767bdc8fdfab6a78b6448e76ea3388a32 Gerrit-Change-Number: 34551 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

2 6

Change in flashrom[master]: Fix -Wsign-compare trouble
by Nico Huber (Code Review) July 31, 2019

July 31, 2019

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/flashrom/+/30409 ) Change subject: Fix -Wsign-compare trouble ...................................................................... Fix -Wsign-compare trouble Mostly by changing to `unsigned` types where applicable, sometimes `signed` types, and casting as a last resort. Change-Id: I08895543ffb7a48058bcf91ef6500ca113f2d305 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/30409 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M 82802ab.c M at45db.c M bitbang_spi.c M board_enable.c M buspirate_spi.c M cbtable.c M cli_classic.c M dediprog.c M dmi.c M dummyflasher.c M en29lv640b.c M flash.h M flashrom.c M fmap.c M helpers.c M ich_descriptors.c M ichspi.c M it85spi.c M it87spi.c M jedec.c M layout.c M pickit2_spi.c M print.c M print_wiki.c M programmer.h M sb600spi.c M serial.c M serprog.c M sst28sf040.c M sst_fwhub.c M usbblaster_spi.c M wbsio_spi.c 32 files changed, 116 insertions(+), 107 deletions(-) Approvals: build bot (Jenkins): Verified Jacob Garber: Looks good to me, approved diff --git a/82802ab.c b/82802ab.c index 1046da4..281b66e 100644 --- a/82802ab.c +++ b/82802ab.c @@ -126,7 +126,7 @@ /* chunksize is 1 */ int write_82802ab(struct flashctx *flash, const uint8_t *src, unsigned int start, unsigned int len) { - int i; + unsigned int i; chipaddr dst = flash->virtual_memory + start; for (i = 0; i < len; i++) { @@ -144,7 +144,7 @@ { chipaddr bios = flash->virtual_memory; uint8_t mcfg, bcfg, need_unlock = 0, can_unlock = 0; - int i; + unsigned int i; /* Clear status register */ chip_writeb(flash, 0x50, bios); @@ -197,7 +197,7 @@ chipaddr bios = flash->virtual_memory; uint8_t mcfg, bcfg; uint8_t need_unlock = 0, can_unlock = 0; - int i; + unsigned int i; /* Wait if chip is busy */ wait_82802ab(flash); diff --git a/at45db.c b/at45db.c index 38c0685..5f949bb 100644 --- a/at45db.c +++ b/at45db.c @@ -463,9 +463,9 @@ } /* Create a suitable buffer to store opcode, address and data chunks for buffer1. */ - const int max_data_write = flash->mst->spi.max_data_write - 4; - const unsigned int max_chunk = (max_data_write > 0 && max_data_write <= page_size) ? - max_data_write : page_size; + const unsigned int max_data_write = flash->mst->spi.max_data_write; + const unsigned int max_chunk = max_data_write > 4 && max_data_write - 4 <= page_size ? + max_data_write - 4 : page_size; uint8_t buf[4 + max_chunk]; buf[0] = AT45DB_BUFFER1_WRITE; diff --git a/bitbang_spi.c b/bitbang_spi.c index 2dad149..7c183c3 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -150,7 +150,7 @@ const unsigned char *writearr, unsigned char *readarr) { - int i; + unsigned int i; const struct bitbang_spi_master *master = flash->mst->spi.data; /* FIXME: Run bitbang_spi_request_bus here or in programmer init? diff --git a/board_enable.c b/board_enable.c index 5876036..74612f5 100644 --- a/board_enable.c +++ b/board_enable.c @@ -373,7 +373,8 @@ static const struct winbond_chip *winbond_superio_chipdef(void) { - int i, j; + int i; + unsigned int j; for (i = 0; i < superio_count; i++) { if (superios[i].vendor != SUPERIO_VENDOR_WINBOND) diff --git a/buspirate_spi.c b/buspirate_spi.c index fb066c2..08cd04c 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -76,7 +76,8 @@ static int buspirate_sendrecv(unsigned char *buf, unsigned int writecnt, unsigned int readcnt) { - int i, ret = 0; + unsigned int i; + int ret = 0; msg_pspew("%s: write %i, read %i ", __func__, writecnt, readcnt); if (!writecnt && !readcnt) { diff --git a/cbtable.c b/cbtable.c index fe0c368..bdf53ce 100644 --- a/cbtable.c +++ b/cbtable.c @@ -34,7 +34,7 @@ * -1 if IDs in the image do not match the IDs embedded in the current firmware, * 0 if the IDs could not be found in the image or if they match correctly. */ -int cb_check_image(const uint8_t *image, int size) +int cb_check_image(const uint8_t *image, unsigned int size) { const unsigned int *walk; unsigned int mb_part_offset, mb_vendor_offset; @@ -138,10 +138,10 @@ ((((char *)rec) + rec->size) <= (((char *)head) + sizeof(*head) + head->table_bytes)); \ rec = (struct lb_record *)(((char *)rec) + rec->size)) -static int count_lb_records(struct lb_header *head) +static unsigned int count_lb_records(struct lb_header *head) { struct lb_record *rec; - int count; + unsigned int count; count = 0; for_each_lbrec(head, rec) { diff --git a/cli_classic.c b/cli_classic.c index 0591bfe..b4112fd 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -507,7 +507,7 @@ for (j = 0; j < registered_master_count; j++) { startchip = 0; - while (chipcount < ARRAY_SIZE(flashes)) { + while (chipcount < (int)ARRAY_SIZE(flashes)) { startchip = probe_flash(&registered_masters[j], startchip, &flashes[chipcount], 0); if (startchip == -1) break; diff --git a/dediprog.c b/dediprog.c index 3566109..fbd6930 100644 --- a/dediprog.c +++ b/dediprog.c @@ -474,7 +474,7 @@ return 1; int ret = dediprog_write(CMD_READ, value, idx, data_packet, sizeof(data_packet)); - if (ret != sizeof(data_packet)) { + if (ret != (int)sizeof(data_packet)) { msg_perr("Command Read SPI Bulk failed, %i %s!\n", ret, libusb_error_name(ret)); return 1; } @@ -487,7 +487,7 @@ /* Allocate bulk transfers. */ unsigned int i; - for (i = 0; i < min(DEDIPROG_ASYNC_TRANSFERS, count); ++i) { + for (i = 0; i < MIN(DEDIPROG_ASYNC_TRANSFERS, count); ++i) { transfers[i] = libusb_alloc_transfer(0); if (!transfers[i]) { msg_perr("Allocating libusb transfer %i failed: %s!\n", i, libusb_error_name(ret)); @@ -630,7 +630,7 @@ if (prepare_rw_cmd(flash, data_packet, count, dedi_spi_cmd, &value, &idx, start, 0)) return 1; int ret = dediprog_write(CMD_WRITE, value, idx, data_packet, sizeof(data_packet)); - if (ret != sizeof(data_packet)) { + if (ret != (int)sizeof(data_packet)) { msg_perr("Command Write SPI Bulk failed, %s!\n", libusb_error_name(ret)); return 1; } @@ -743,7 +743,7 @@ value = 0; } ret = dediprog_write(CMD_TRANSCEIVE, value, idx, writearr, writecnt); - if (ret != writecnt) { + if (ret != (int)writecnt) { msg_perr("Send SPI failed, expected %i, got %i %s!\n", writecnt, ret, libusb_error_name(ret)); return 1; @@ -770,7 +770,7 @@ ret = dediprog_read(CMD_TRANSCEIVE, value, idx, readarr, readcnt); */ ret = dediprog_read(CMD_TRANSCEIVE, 0, 0, readarr, readcnt); - if (ret != readcnt) { + if (ret != (int)readcnt) { msg_perr("Receive SPI failed, expected %i, got %i %s!\n", readcnt, ret, libusb_error_name(ret)); return 1; } @@ -804,7 +804,7 @@ int sfnum; int fw[3]; if (sscanf(buf, "SF%d V:%d.%d.%d ", &sfnum, &fw[0], &fw[1], &fw[2]) != 4 || - sfnum != dediprog_devicetype) { + sfnum != (int)dediprog_devicetype) { msg_perr("Unexpected firmware version string '%s'\n", buf); return 1; } diff --git a/dmi.c b/dmi.c index ae90f7c..9ec935a 100644 --- a/dmi.c +++ b/dmi.c @@ -147,7 +147,7 @@ static void dmi_chassis_type(uint8_t code) { - int i; + unsigned int i; code &= 0x7f; /* bits 6:0 are chassis type, 7th bit is the lock bit */ is_laptop = 2; for (i = 0; i < ARRAY_SIZE(dmi_chassis_types); i++) { @@ -161,7 +161,7 @@ static void dmi_table(uint32_t base, uint16_t len, uint16_t num) { - int i = 0, j = 0; + unsigned int i = 0, j = 0; uint8_t *dmi_table_mem = physmap_ro("DMI Table", base, len); if (dmi_table_mem == NULL) { @@ -346,7 +346,7 @@ static int dmi_fill(void) { - int i; + unsigned int i; char *chassis_type; msg_pdbg("Using External DMI decoder.\n"); @@ -376,7 +376,7 @@ static int dmi_shutdown(void *data) { - int i; + unsigned int i; for (i = 0; i < ARRAY_SIZE(dmi_strings); i++) { free(dmi_strings[i].value); dmi_strings[i].value = NULL; @@ -406,7 +406,7 @@ } has_dmi_support = 1; - int i; + unsigned int i; for (i = 0; i < ARRAY_SIZE(dmi_strings); i++) { msg_pdbg("DMI string %s: \"%s\"\n", dmi_strings[i].keyword, (dmi_strings[i].value == NULL) ? "" : dmi_strings[i].value); @@ -463,7 +463,7 @@ int dmi_match(const char *pattern) { - int i; + unsigned int i; if (!has_dmi_support) return 0; diff --git a/dummyflasher.c b/dummyflasher.c index 8f3dfda..0caffc9 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -58,8 +58,8 @@ static unsigned int emu_jedec_ce_c7_size = 0; static unsigned char spi_blacklist[256]; static unsigned char spi_ignorelist[256]; -static int spi_blacklist_size = 0; -static int spi_ignorelist_size = 0; +static unsigned int spi_blacklist_size = 0; +static unsigned int spi_ignorelist_size = 0; static uint8_t emu_status = 0; /* A legit complete SFDP table based on the MX25L6436E (rev. 1.8) datasheet. */ @@ -151,7 +151,7 @@ { char *bustext = NULL; char *tmp = NULL; - int i; + unsigned int i; #if EMULATE_SPI_CHIP char *status = NULL; #endif @@ -231,7 +231,7 @@ msg_pdbg("SPI blacklist is "); for (i = 0; i < spi_blacklist_size; i++) msg_pdbg("%02x ", spi_blacklist[i]); - msg_pdbg(", size %i\n", spi_blacklist_size); + msg_pdbg(", size %u\n", spi_blacklist_size); } free(tmp); @@ -267,7 +267,7 @@ msg_pdbg("SPI ignorelist is "); for (i = 0; i < spi_ignorelist_size; i++) msg_pdbg("%02x ", spi_ignorelist[i]); - msg_pdbg(", size %i\n", spi_ignorelist_size); + msg_pdbg(", size %u\n", spi_ignorelist_size); } free(tmp); @@ -819,7 +819,7 @@ const unsigned char *writearr, unsigned char *readarr) { - int i; + unsigned int i; msg_pspew("%s:", __func__); diff --git a/en29lv640b.c b/en29lv640b.c index 550642d..5b01904 100644 --- a/en29lv640b.c +++ b/en29lv640b.c @@ -29,7 +29,7 @@ /* chunksize is 1 */ int write_en29lv640b(struct flashctx *flash, const uint8_t *src, unsigned int start, unsigned int len) { - int i; + unsigned int i; chipaddr bios = flash->virtual_memory; chipaddr dst = flash->virtual_memory + start; diff --git a/flash.h b/flash.h index b60a980..c1d8980 100644 --- a/flash.h +++ b/flash.h @@ -301,7 +301,11 @@ /* helpers.c */ uint32_t address_to_bits(uint32_t addr); -int bitcount(unsigned long a); +unsigned int bitcount(unsigned long a); +#undef MIN +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#undef MAX +#define MAX(a, b) ((a) > (b) ? (a) : (b)) int max(int a, int b); int min(int a, int b); char *strcat_realloc(char *dest, const char *src); diff --git a/flashrom.c b/flashrom.c index cb1dca6..06b1854 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1253,7 +1253,7 @@ ret = 1; goto out; } - if (image_stat.st_size != size) { + if (image_stat.st_size != (intmax_t)size) { msg_gerr("Error: Image size (%jd B) doesn't match the flash chip's size (%lu B)!\n", (intmax_t)image_stat.st_size, size); ret = 1; diff --git a/fmap.c b/fmap.c index 31f282f..ca25651 100644 --- a/fmap.c +++ b/fmap.c @@ -96,7 +96,7 @@ off_t offset; bool fmap_found = 0; - for (offset = 0; offset <= len - sizeof(struct fmap); offset++) { + for (offset = 0; offset <= (off_t)(len - sizeof(struct fmap)); offset++) { if (is_valid_fmap((struct fmap *)&buf[offset])) { fmap_found = 1; break; @@ -178,7 +178,7 @@ } static int fmap_bsearch_rom(struct fmap **fmap_out, struct flashctx *const flashctx, - size_t rom_offset, size_t len, int min_stride) + size_t rom_offset, size_t len, size_t min_stride) { size_t stride, fmap_len = 0; int ret = 1, fmap_found = 0, check_offset_0 = 1; diff --git a/helpers.c b/helpers.c index a714908..cfa9812 100644 --- a/helpers.c +++ b/helpers.c @@ -30,9 +30,9 @@ return 32 - lzb; } -int bitcount(unsigned long a) +unsigned int bitcount(unsigned long a) { - int i = 0; + unsigned int i = 0; for (; a != 0; a >>= 1) if (a & 1) i++; diff --git a/ich_descriptors.c b/ich_descriptors.c index a757add..684b845 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -35,10 +35,6 @@ #include "flash.h" /* for msg_* */ #include "programmer.h" -#ifndef min -#define min(a, b) (((a) < (b)) ? (a) : (b)) -#endif - ssize_t ich_number_of_regions(const enum ich_chipset cs, const struct ich_desc_content *const cont) { switch (cs) { @@ -365,7 +361,7 @@ void prettyprint_ich_descriptor_region(const enum ich_chipset cs, const struct ich_descriptors *const desc) { - size_t i; + ssize_t i; const ssize_t nr = ich_number_of_regions(cs, &desc->content); msg_pdbg2("=== Region Section ===\n"); if (nr < 0) { @@ -374,18 +370,18 @@ return; } for (i = 0; i < nr; i++) - msg_pdbg2("FLREG%zu 0x%08x\n", i, desc->region.FLREGs[i]); + msg_pdbg2("FLREG%zd 0x%08x\n", i, desc->region.FLREGs[i]); msg_pdbg2("\n"); msg_pdbg2("--- Details ---\n"); for (i = 0; i < nr; i++) - pprint_freg(&desc->region, i); + pprint_freg(&desc->region, (uint32_t)i); msg_pdbg2("\n"); } void prettyprint_ich_descriptor_master(const enum ich_chipset cs, const struct ich_descriptors *const desc) { - size_t i; + ssize_t i; const ssize_t nm = ich_number_of_masters(cs, &desc->content); msg_pdbg2("=== Master Section ===\n"); if (nm < 0) { @@ -394,7 +390,7 @@ return; } for (i = 0; i < nm; i++) - msg_pdbg2("FLMSTR%zu 0x%08x\n", i + 1, desc->master.FLMSTRs[i]); + msg_pdbg2("FLMSTR%zd 0x%08x\n", i + 1, desc->master.FLMSTRs[i]); msg_pdbg2("\n"); msg_pdbg2("--- Details ---\n"); @@ -402,7 +398,7 @@ const char *const master_names[] = { "BIOS", "ME", "GbE", "unknown", "EC", }; - if (nm >= ARRAY_SIZE(master_names)) { + if (nm >= (ssize_t)ARRAY_SIZE(master_names)) { msg_pdbg2("%s: number of masters too high (%d).\n", __func__, desc->content.NM + 1); return; @@ -423,7 +419,7 @@ "BIOS", "ME", "GbE", "DE", "BMC", "IE", }; /* NM starts at 1 instead of 0 for LBG */ - if (nm > ARRAY_SIZE(master_names)) { + if (nm > (ssize_t)ARRAY_SIZE(master_names)) { msg_pdbg2("%s: number of masters too high (%d).\n", __func__, desc->content.NM); return; @@ -446,14 +442,14 @@ } } else if (cs == CHIPSET_APOLLO_LAKE) { const char *const master_names[] = { "BIOS", "TXE", }; - if (nm > ARRAY_SIZE(master_names)) { + if (nm > (ssize_t)ARRAY_SIZE(master_names)) { msg_pdbg2("%s: number of masters too high (%d).\n", __func__, desc->content.NM); return; } msg_pdbg2(" FD IFWI TXE n/a Platf DevExp\n"); for (i = 0; i < nm; i++) { - size_t j; + ssize_t j; msg_pdbg2("%-4s", master_names[i]); for (j = 0; j < ich_number_of_regions(cs, &desc->content); j++) msg_pdbg2(" %c%c ", @@ -799,7 +795,7 @@ unsigned int i, max_count; msg_pdbg2("=== Softstraps ===\n"); - max_count = min(ARRAY_SIZE(desc->north.STRPs), desc->content.MSL); + max_count = MIN(ARRAY_SIZE(desc->north.STRPs), desc->content.MSL); if (max_count < desc->content.MSL) { msg_pdbg2("MSL (%u) is greater than the current maximum of %u entries.\n", desc->content.MSL, max_count); @@ -811,7 +807,7 @@ msg_pdbg2("STRP%-2d = 0x%08x\n", i, desc->north.STRPs[i]); msg_pdbg2("\n"); - max_count = min(ARRAY_SIZE(desc->south.STRPs), desc->content.ISL); + max_count = MIN(ARRAY_SIZE(desc->south.STRPs), desc->content.ISL); if (max_count < desc->content.ISL) { msg_pdbg2("ISL (%u) is greater than the current maximum of %u entries.\n", desc->content.ISL, max_count); @@ -965,8 +961,8 @@ int read_ich_descriptors_from_dump(const uint32_t *const dump, const size_t len, enum ich_chipset *const cs, struct ich_descriptors *const desc) { - size_t i, max_count; - uint8_t pch_bug_offset = 0; + ssize_t i, max_count; + size_t pch_bug_offset = 0; if (dump == NULL || desc == NULL) return ICH_RET_PARAM; @@ -1000,14 +996,14 @@ /* region */ const ssize_t nr = ich_number_of_regions(*cs, &desc->content); - if (nr < 0 || len < getFRBA(&desc->content) + nr * 4) + if (nr < 0 || len < getFRBA(&desc->content) + (size_t)nr * 4) return ICH_RET_OOB; for (i = 0; i < nr; i++) desc->region.FLREGs[i] = dump[(getFRBA(&desc->content) >> 2) + i]; /* master */ const ssize_t nm = ich_number_of_masters(*cs, &desc->content); - if (nm < 0 || len < getFMBA(&desc->content) + nm * 4) + if (nm < 0 || len < getFMBA(&desc->content) + (size_t)nm * 4) return ICH_RET_OOB; for (i = 0; i < nm; i++) desc->master.FLMSTRs[i] = dump[(getFMBA(&desc->content) >> 2) + i]; @@ -1034,7 +1030,7 @@ return ICH_RET_OOB; /* limit the range to be written */ - max_count = min(sizeof(desc->north.STRPs) / 4, desc->content.MSL); + max_count = MIN(sizeof(desc->north.STRPs) / 4, desc->content.MSL); for (i = 0; i < max_count; i++) desc->north.STRPs[i] = dump[(getFMSBA(&desc->content) >> 2) + i]; @@ -1043,7 +1039,7 @@ return ICH_RET_OOB; /* limit the range to be written */ - max_count = min(sizeof(desc->south.STRPs) / 4, desc->content.ISL); + max_count = MIN(sizeof(desc->south.STRPs) / 4, desc->content.ISL); for (i = 0; i < max_count; i++) desc->south.STRPs[i] = dump[(getFISBA(&desc->content) >> 2) + i]; @@ -1134,7 +1130,7 @@ int read_ich_descriptors_via_fdo(enum ich_chipset cs, void *spibar, struct ich_descriptors *desc) { - size_t i; + ssize_t i; struct ich_desc_region *r = &desc->region; /* Test if bit-fields are working as expected. @@ -1226,7 +1222,8 @@ memset(layout, 0x00, sizeof(*layout)); ssize_t i, j; - for (i = 0, j = 0; i < min(ich_number_of_regions(cs, &desc.content), ARRAY_SIZE(regions)); ++i) { + const ssize_t nr = MIN(ich_number_of_regions(cs, &desc.content), (ssize_t)ARRAY_SIZE(regions)); + for (i = 0, j = 0; i < nr; ++i) { const chipoff_t base = ICH_FREG_BASE(desc.region.FLREGs[i]); const chipoff_t limit = ICH_FREG_LIMIT(desc.region.FLREGs[i]); if (limit <= base) diff --git a/ichspi.c b/ichspi.c index e1ede60..8b8f0f6 100644 --- a/ichspi.c +++ b/ichspi.c @@ -470,7 +470,7 @@ static uint8_t lookup_spi_type(uint8_t opcode) { - int a; + unsigned int a; for (a = 0; a < ARRAY_SIZE(POSSIBLE_OPCODES); a++) { if (POSSIBLE_OPCODES[a].opcode == opcode) @@ -1564,7 +1564,7 @@ "locked", "read-only", "write-only", "read-write" }; -static enum ich_access_protection ich9_handle_frap(uint32_t frap, int i) +static enum ich_access_protection ich9_handle_frap(uint32_t frap, unsigned int i) { const int rwperms_unknown = ARRAY_SIZE(access_names); static const char *const region_names[6] = { @@ -1595,23 +1595,23 @@ limit = ICH_FREG_LIMIT(freg); if (base > limit || (freg == 0 && i > 0)) { /* this FREG is disabled */ - msg_pdbg2("0x%02X: 0x%08x FREG%i: %s region is unused.\n", + msg_pdbg2("0x%02X: 0x%08x FREG%u: %s region is unused.\n", offset, freg, i, region_name); return NO_PROT; } msg_pdbg("0x%02X: 0x%08x ", offset, freg); if (rwperms == 0x3) { - msg_pdbg("FREG%i: %s region (0x%08x-0x%08x) is %s.\n", i, + msg_pdbg("FREG%u: %s region (0x%08x-0x%08x) is %s.\n", i, region_name, base, limit, access_names[rwperms]); return NO_PROT; } if (rwperms == rwperms_unknown) { - msg_pdbg("FREG%i: %s region (0x%08x-0x%08x) has unknown permissions.\n", + msg_pdbg("FREG%u: %s region (0x%08x-0x%08x) has unknown permissions.\n", i, region_name, base, limit); return NO_PROT; } - msg_pinfo("FREG%i: %s region (0x%08x-0x%08x) is %s.\n", i, + msg_pinfo("FREG%u: %s region (0x%08x-0x%08x) is %s.\n", i, region_name, base, limit, access_names[rwperms]); return access_perms_to_protection[rwperms]; } @@ -1625,7 +1625,7 @@ #define ICH_PR_PERMS(pr) (((~((pr) >> PR_RP_OFF) & 1) << 0) | \ ((~((pr) >> PR_WP_OFF) & 1) << 1)) -static enum ich_access_protection ich9_handle_pr(const size_t reg_pr0, int i) +static enum ich_access_protection ich9_handle_pr(const size_t reg_pr0, unsigned int i) { uint8_t off = reg_pr0 + (i * 4); uint32_t pr = mmio_readl(ich_spibar + off); @@ -1701,7 +1701,7 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen) { - int i; + unsigned int i; uint16_t tmp2; uint32_t tmp; char *arg; @@ -1786,7 +1786,7 @@ for (i = 0; i < 3; i++) { int offs; offs = 0x60 + (i * 4); - msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, + msg_pdbg("0x%02x: 0x%08x (PBR%u)\n", offs, mmio_readl(ich_spibar + offs), i); } if (mmio_readw(ich_spibar) & (1 << 15)) { diff --git a/it85spi.c b/it85spi.c index 3cd5514..5ce9193 100644 --- a/it85spi.c +++ b/it85spi.c @@ -327,7 +327,7 @@ const unsigned char *writearr, unsigned char *readarr) { - int i; + unsigned int i; it85xx_enter_scratch_rom(); /* Exit scratch ROM ONLY when programmer shuts down. Otherwise, the diff --git a/it87spi.c b/it87spi.c index f8b2b0f..f5955fe 100644 --- a/it87spi.c +++ b/it87spi.c @@ -281,7 +281,6 @@ unsigned char *readarr) { uint8_t busy, writeenc; - int i; do { busy = INB(it8716f_flashport) & 0x80; @@ -330,6 +329,8 @@ | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport); if (readcnt > 0) { + unsigned int i; + do { busy = INB(it8716f_flashport) & 0x80; } while (busy); diff --git a/jedec.c b/jedec.c index ac1ea0d..0709efa 100644 --- a/jedec.c +++ b/jedec.c @@ -408,7 +408,8 @@ int write_jedec_1(struct flashctx *flash, const uint8_t *src, unsigned int start, unsigned int len) { - int i, failed = 0; + unsigned int i; + int failed = 0; chipaddr dst = flash->virtual_memory + start; chipaddr olddst; unsigned int mask; @@ -430,7 +431,8 @@ static int write_page_write_jedec_common(struct flashctx *flash, const uint8_t *src, unsigned int start, unsigned int page_size) { - int i, tried = 0, failed; + unsigned int i; + int tried = 0, failed; const uint8_t *s = src; chipaddr bios = flash->virtual_memory; chipaddr dst = bios + start; diff --git a/layout.c b/layout.c index 6e476c2..d80b01f 100644 --- a/layout.c +++ b/layout.c @@ -46,7 +46,8 @@ struct flashrom_layout *const layout = get_global_layout(); FILE *romlayout; char tempstr[256], tempname[256]; - int i, ret = 1; + unsigned int i; + int ret = 1; romlayout = fopen(name, "r"); @@ -154,7 +155,7 @@ */ int process_include_args(struct flashrom_layout *l, const struct layout_include_args *const args) { - int found = 0; + unsigned int found = 0; const struct layout_include_args *tmp; if (args == NULL) @@ -193,7 +194,7 @@ void layout_cleanup(struct layout_include_args **args) { struct flashrom_layout *const layout = get_global_layout(); - int i; + unsigned int i; struct layout_include_args *tmp; while (*args) { @@ -216,7 +217,7 @@ chipsize_t total_size = flash->chip->total_size * 1024; int ret = 0; - int i; + unsigned int i; for (i = 0; i < layout->num_entries; i++) { if (layout->entries[i].start >= total_size || layout->entries[i].end >= total_size) { msg_gwarn("Warning: Address range of region \"%s\" exceeds the current chip's " diff --git a/pickit2_spi.c b/pickit2_spi.c index 52021d9..784dc13 100644 --- a/pickit2_spi.c +++ b/pickit2_spi.c @@ -209,7 +209,7 @@ } uint8_t buf[CMD_LENGTH] = {CMD_DOWNLOAD_DATA, writecnt}; - int i = 2; + unsigned int i = 2; for (; i < writecnt + 2; i++) { buf[i] = writearr[i - 2]; } diff --git a/print.c b/print.c index cfe6267..2901c50 100644 --- a/print.c +++ b/print.c @@ -19,6 +19,7 @@ #include <stdio.h> #include <string.h> #include <stdlib.h> +#include <stddef.h> #include "flash.h" #include "programmer.h" @@ -314,20 +315,20 @@ #if CONFIG_INTERNAL == 1 static void print_supported_chipsets(void) { - int i, chipsetcount = 0; + unsigned int i, chipsetcount = 0; const struct penable *c = chipset_enables; - int maxvendorlen = strlen("Vendor") + 1; - int maxchipsetlen = strlen("Chipset") + 1; + size_t maxvendorlen = strlen("Vendor") + 1; + size_t maxchipsetlen = strlen("Chipset") + 1; for (c = chipset_enables; c->vendor_name != NULL; c++) { chipsetcount++; - maxvendorlen = max(maxvendorlen, strlen(c->vendor_name)); - maxchipsetlen = max(maxchipsetlen, strlen(c->device_name)); + maxvendorlen = MAX(maxvendorlen, strlen(c->vendor_name)); + maxchipsetlen = MAX(maxchipsetlen, strlen(c->device_name)); } maxvendorlen++; maxchipsetlen++; - msg_ginfo("Supported chipsets (total: %d):\n\n", chipsetcount); + msg_ginfo("Supported chipsets (total: %u):\n\n", chipsetcount); msg_ginfo("Vendor"); for (i = strlen("Vendor"); i < maxvendorlen; i++) @@ -354,12 +355,12 @@ static void print_supported_boards_helper(const struct board_info *boards, const char *devicetype) { - int i; + unsigned int i; unsigned int boardcount_good = 0, boardcount_bad = 0, boardcount_nt = 0; const struct board_match *e = board_matches; const struct board_info *b = boards; - int maxvendorlen = strlen("Vendor") + 1; - int maxboardlen = strlen("Board") + 1; + size_t maxvendorlen = strlen("Vendor") + 1; + size_t maxboardlen = strlen("Board") + 1; for (b = boards; b->vendor != NULL; b++) { maxvendorlen = max(maxvendorlen, strlen(b->vendor)); diff --git a/print_wiki.c b/print_wiki.c index ea8c4d7..b2ac65c 100644 --- a/print_wiki.c +++ b/print_wiki.c @@ -245,7 +245,7 @@ "<span id=\"%s_note%d\">%d. [[#%s_ref%d|↑]]</span>" " <nowiki>%s</nowiki><br />\n", devicetype, num_notes, num_notes, devicetype, num_notes, boards[i].note); - if (ret < 0 || ret >= sizeof(tmp)) { + if (ret < 0 || (unsigned int)ret >= sizeof(tmp)) { fprintf(stderr, "Footnote text #%d of %s truncated (ret=%d, sizeof(tmp)=%zu)\n", num_notes, devicetype, ret, sizeof(tmp)); } diff --git a/programmer.h b/programmer.h index f4e8b46..dfa6ebd 100644 --- a/programmer.h +++ b/programmer.h @@ -304,7 +304,7 @@ /* cbtable.c */ int cb_parse_table(const char **vendor, const char **model); -int cb_check_image(const uint8_t *bios, int size); +int cb_check_image(const uint8_t *bios, unsigned int size); /* dmi.c */ #if defined(__i386__) || defined(__x86_64__) diff --git a/sb600spi.c b/sb600spi.c index fd9487c..3026836 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -247,7 +247,7 @@ reset_internal_fifo_pointer(); msg_pspew("Filling FIFO: "); - int count; + unsigned int count; for (count = 0; count < writecnt; count++) { msg_pspew("[%02x]", writearr[count]); mmio_writeb(writearr[count], sb600_spibar + 0xC); @@ -326,7 +326,7 @@ mmio_writeb(readcnt, sb600_spibar + 0x4b); msg_pspew("Filling buffer: "); - int count; + unsigned int count; for (count = 0; count < writecnt; count++) { msg_pspew("[%02x]", writearr[count]); mmio_writeb(writearr[count], sb600_spibar + 0x80 + count); diff --git a/serial.c b/serial.c index e61df74..3a99dbf 100644 --- a/serial.c +++ b/serial.c @@ -480,10 +480,10 @@ } #endif - int i; - int rd_bytes = 0; + unsigned int i; + unsigned int rd_bytes = 0; for (i = 0; i < timeout; i++) { - msg_pspew("readcnt %d rd_bytes %d\n", readcnt, rd_bytes); + msg_pspew("readcnt %u rd_bytes %u\n", readcnt, rd_bytes); #if IS_WINDOWS ReadFile(sp_fd, c + rd_bytes, readcnt - rd_bytes, &rv, NULL); msg_pspew("read %lu bytes\n", rv); @@ -560,10 +560,10 @@ } #endif - int i; - int wr_bytes = 0; + unsigned int i; + unsigned int wr_bytes = 0; for (i = 0; i < timeout; i++) { - msg_pspew("writecnt %d wr_bytes %d\n", writecnt, wr_bytes); + msg_pspew("writecnt %u wr_bytes %u\n", writecnt, wr_bytes); #if IS_WINDOWS WriteFile(sp_fd, buf + wr_bytes, writecnt - wr_bytes, &rv, NULL); msg_pspew("wrote %lu bytes\n", rv); diff --git a/serprog.c b/serprog.c index b6c85c9..37a9db4 100644 --- a/serprog.c +++ b/serprog.c @@ -71,8 +71,8 @@ static uint32_t sp_write_n_bytes = 0; /* sp_streamed_* used for flow control checking */ -static int sp_streamed_transmit_ops = 0; -static int sp_streamed_transmit_bytes = 0; +static unsigned int sp_streamed_transmit_ops = 0; +static unsigned int sp_streamed_transmit_bytes = 0; /* sp_opbuf_usage used for counting the amount of on-device operation buffer used */ diff --git a/sst28sf040.c b/sst28sf040.c index 9df27b9..3da25f1 100644 --- a/sst28sf040.c +++ b/sst28sf040.c @@ -75,7 +75,7 @@ /* chunksize is 1 */ int write_28sf040(struct flashctx *flash, const uint8_t *src, unsigned int start, unsigned int len) { - int i; + unsigned int i; chipaddr bios = flash->virtual_memory; chipaddr dst = flash->virtual_memory + start; diff --git a/sst_fwhub.c b/sst_fwhub.c index c712303..d688a35 100644 --- a/sst_fwhub.c +++ b/sst_fwhub.c @@ -21,7 +21,7 @@ #include "flash.h" #include "chipdrivers.h" -static int check_sst_fwhub_block_lock(struct flashctx *flash, int offset) +static int check_sst_fwhub_block_lock(struct flashctx *flash, unsigned int offset) { chipaddr registers = flash->virtual_registers; uint8_t blockstatus; @@ -47,7 +47,7 @@ return blockstatus & 0x1; } -static int clear_sst_fwhub_block_lock(struct flashctx *flash, int offset) +static int clear_sst_fwhub_block_lock(struct flashctx *flash, unsigned int offset) { chipaddr registers = flash->virtual_registers; uint8_t blockstatus; @@ -67,7 +67,7 @@ int printlock_sst_fwhub(struct flashctx *flash) { - int i; + unsigned int i; for (i = 0; i < flash->chip->total_size * 1024; i += flash->chip->page_size) check_sst_fwhub_block_lock(flash, i); @@ -77,7 +77,8 @@ int unlock_sst_fwhub(struct flashctx *flash) { - int i, ret=0; + unsigned int i; + int ret = 0; for (i = 0; i < flash->chip->total_size * 1024; i += flash->chip->page_size) { diff --git a/usbblaster_spi.c b/usbblaster_spi.c index 886cb57..d6b5084 100644 --- a/usbblaster_spi.c +++ b/usbblaster_spi.c @@ -119,11 +119,11 @@ static int send_write(unsigned int writecnt, const unsigned char *writearr) { - int i; uint8_t buf[BUF_SIZE]; memset(buf, 0, sizeof(buf)); while (writecnt) { + unsigned int i; unsigned int n_write = min(writecnt, BUF_SIZE - 1); msg_pspew("writing %d-byte packet\n", n_write); diff --git a/wbsio_spi.c b/wbsio_spi.c index 28b568e..f4f6af9 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -115,7 +115,7 @@ const unsigned char *writearr, unsigned char *readarr) { - int i; + unsigned int i; uint8_t mode = 0; msg_pspew("%s:", __func__); -- To view, visit https://review.coreboot.org/c/flashrom/+/30409 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I08895543ffb7a48058bcf91ef6500ca113f2d305 Gerrit-Change-Number: 30409 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in flashrom[master]: Fix -Wsign-compare trouble
by Nico Huber (Code Review) July 31, 2019

July 31, 2019

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/30409 ) Change subject: Fix -Wsign-compare trouble ...................................................................... Patch Set 5: Many thanks for the review! -- To view, visit https://review.coreboot.org/c/flashrom/+/30409 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I08895543ffb7a48058bcf91ef6500ca113f2d305 Gerrit-Change-Number: 30409 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 31 Jul 2019 08:26:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: Makefile,meson.build: Enable/assume -Wextra
by Jacob Garber (Code Review) July 30, 2019

July 30, 2019

Jacob Garber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/30411 ) Change subject: Makefile,meson.build: Enable/assume -Wextra ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/flashrom/+/30411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id2ece264c2d483e34019985dd3a7631c4889abe6 Gerrit-Change-Number: 30411 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 30 Jul 2019 18:11:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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