July 2019 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: flashchips: Add missing MT25Q capacities
by Jacob Creedon (Code Review) Oct. 14, 2019

Oct. 14, 2019

Jacob Creedon has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34492 ) Change subject: flashchips: Add missing MT25Q capacities ...................................................................... flashchips: Add missing MT25Q capacities This adds the 128Mb, 1Gb, and 2Gb capacities of the MT25Q devices. All of these are implemented via the datasheet and should work but are untested in hardware. Signed-off-by: Jacob Creedon <jcreedon(a)google.com> Change-Id: Ice6ea9426361afc25d4b731e2e3079edf234fdda --- M flashchips.c M flashchips.h 2 files changed, 274 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/92/34492/1 diff --git a/flashchips.c b/flashchips.c index 5424a04..6b553fb 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10705,6 +10705,270 @@ { .vendor = "Micron", + .name = "MT25QL01G", /* L = 3V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q00A__3E, + .total_size = 131072, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 4096} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 4096} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {131072 * 1024, 1} }, + .block_erase = spi_block_erase_c4, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Micron", + .name = "MT25QU01G", /* U = 1.8V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q00A__1E, + .total_size = 131072, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 4096} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 4096} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {131072 * 1024, 1} }, + .block_erase = spi_block_erase_c4, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + }, + + { + .vendor = "Micron", + .name = "MT25QL02G", /* L = 3V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_MT25QL02G, + .total_size = 262144, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 65536} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 65536} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 8192} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 8192} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 4096} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 4096} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {262144 * 1024, 1} }, + .block_erase = spi_block_erase_c4, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Micron", + .name = "ST_MT25QU02G", /* U = 1.8V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q00A__1E, + .total_size = 262144, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 65536} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 65536} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 8192} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 8192} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 4096} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 4096} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {262144 * 1024, 1} }, + .block_erase = spi_block_erase_c4, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + }, + + { + .vendor = "Micron", + .name = "MT25QU128", /* U = 1.8V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q128__1E, + .total_size = 16384, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16384 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, { + .eraseblocks = { {16384 * 1024, 1} }, + .block_erase = spi_block_erase_60, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + }, + + { + .vendor = "Micron", + .name = "MT25QL128", /* L = 3V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q128__3E, + .total_size = 16384, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16384 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, { + .eraseblocks = { {16384 * 1024, 1} }, + .block_erase = spi_block_erase_60, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Micron", .name = "MT25QL256", /* L = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, diff --git a/flashchips.h b/flashchips.h index 006b95e..e53e0df 100644 --- a/flashchips.h +++ b/flashchips.h @@ -862,13 +862,16 @@ #define ST_N25Q032__1E 0xBB16 /* N25Q032, 1.8V, (uniform sectors expected) */ #define ST_N25Q064__3E 0xBA17 /* N25Q064, 3.0V, (uniform sectors expected) */ #define ST_N25Q064__1E 0xBB17 /* N25Q064, 1.8V, (uniform sectors expected) */ -#define ST_N25Q128__3E 0xBA18 /* N25Q128, 3.0V, (uniform sectors expected) */ -#define ST_N25Q128__1E 0xBB18 /* N25Q128, 1.8V, (uniform sectors expected) */ -#define ST_N25Q256__3E 0xBA19 /* N25Q256, 3.0V, (uniform sectors expected) */ -#define ST_N25Q256__1E 0xBB19 /* N25Q256, 1.8V, (uniform sectors expected) */ -#define ST_N25Q512__3E 0xBA20 /* N25Q512, 3.0V, (uniform sectors expected) */ -#define ST_N25Q512__1E 0xBB20 /* N25Q512, 1.8V, (uniform sectors expected) */ -#define ST_N25Q00A__3E 0xBA21 /* N25Q00A, 3.0V, (uniform sectors expected) */ +#define ST_N25Q128__3E 0xBA18 /* N25Q128/MT25QL128, 3.0V, (uniform sectors expected) */ +#define ST_N25Q128__1E 0xBB18 /* N25Q128/MT25QU128, 1.8V, (uniform sectors expected) */ +#define ST_N25Q256__3E 0xBA19 /* N25Q256/MT25QL256, 3.0V, (uniform sectors expected) */ +#define ST_N25Q256__1E 0xBB19 /* N25Q256/MT25QU256, 1.8V, (uniform sectors expected) */ +#define ST_N25Q512__3E 0xBA20 /* N25Q512/MT25QL512, 3.0V, (uniform sectors expected) */ +#define ST_N25Q512__1E 0xBB20 /* N25Q512/MT25QU512, 1.8V, (uniform sectors expected) */ +#define ST_N25Q00A__3E 0xBA21 /* N25Q00A/MT25QL01G, 3.0V, (uniform sectors expected) */ +#define ST_N25Q00A__1E 0xBB21 /* N25Q00A/MT25QU01G, 1.8V, (uniform sectors expected) */ +#define ST_MT25QL02G 0xBA22 /* MT25QL02G, 3.0V, (uniform sectors expected) */ +#define ST_MT25QU02G 0xBB22 /* MT25QU02G, 1.8V, (uniform sectors expected) */ #define ST_NP5Q032 0xDA16 /* Phase-change memory (PCM), 3V */ #define ST_NP5Q064 0xDA17 /* Phase-change memory (PCM), 3V */ #define ST_NP5Q128 0xDA18 /* Phase-change memory (PCM), 3V */ -- To view, visit https://review.coreboot.org/c/flashrom/+/34492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ice6ea9426361afc25d4b731e2e3079edf234fdda Gerrit-Change-Number: 34492 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Creedon <jcreedon(a)google.com> Gerrit-MessageType: newchange

3 8

Change in flashrom[master]: Add support for M95M02-A125
by Konstantin Grudnev (Code Review) Oct. 4, 2019

Oct. 4, 2019

Konstantin Grudnev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34496 ) Change subject: Add support for M95M02-A125 ...................................................................... Add support for M95M02-A125 Automotive 2 Mbit (256KiB) serial SPI bus EEPROM PREW tested successfully with use of ch341a programmer on Linux host 5.2.0-1-MANJARO x86_64 Signed-off-by: Konstantin Grudnev <grudnevkv(a)gmail.com> Change-Id: Ic29cd9051c7eac4822d620c299834134f987f01b --- M chipdrivers.h M flashchips.c M flashchips.h M spi.h M spi25.c 5 files changed, 102 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/34496/1 diff --git a/chipdrivers.h b/chipdrivers.h index e380878..0b4435c 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -34,6 +34,7 @@ int probe_spi_res1(struct flashctx *flash); int probe_spi_res2(struct flashctx *flash); int probe_spi_res3(struct flashctx *flash); +int probe_spi_st95(struct flashctx *flash); int probe_spi_at25f(struct flashctx *flash); int spi_write_enable(struct flashctx *flash); int spi_write_disable(struct flashctx *flash); @@ -51,6 +52,7 @@ int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_db(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_dc(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_emulation(struct flashctx *flash, unsigned int addr, unsigned int blocklen); erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode); int spi_chip_write_1(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int spi_nbyte_read(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); diff --git a/flashchips.c b/flashchips.c index 166af6a..44875c6 100644 --- a/flashchips.c +++ b/flashchips.c @@ -14104,6 +14104,33 @@ }, { + .vendor = "ST", + .name = "M95M02", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M95M02, + .total_size = 256, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_st95, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { { 256 * 1024, 1 } }, + .block_erase = spi_block_erase_emulation, + } + }, + + .printlock = spi_prettyprint_status_register_bp1_srwd, + .unlock = spi_disable_blockprotect_bp1_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2500, 5500}, + }, + + { .vendor = "Sanyo", .name = "LE25FU106B", .bustype = BUS_SPI, diff --git a/flashchips.h b/flashchips.h index 006b95e..d1eed91 100644 --- a/flashchips.h +++ b/flashchips.h @@ -851,6 +851,12 @@ #define ST_M58WR032KT 0x8814 #define ST_M58WR064KB 0x8811 #define ST_M58WR064KT 0x8810 + +/* 00h ST Manufacturer code ST_ID*/ +/* 01h SPI Family code 0x00*/ +/* 02h Memory Density code ST_M95XXX */ +#define ST_M95M02 0x0012 /* ST M95XXX 2Mbit (256KiB) */ + #define ST_MT28GU01G___1 0x88B0 #define ST_MT28GU01G___2 0x88B1 #define ST_MT28GU256___1 0x8901 diff --git a/spi.h b/spi.h index 0073c71..9f199f3 100644 --- a/spi.h +++ b/spi.h @@ -28,6 +28,12 @@ /* INSIZE may be 0x04 for some chips*/ #define JEDEC_RDID_INSIZE 0x03 +/* Some ST M95X model */ +#define ST_M95_RDID 0x83 +#define ST_M95_RDID_OUTSIZE 0x04 /* 8b op, 24bit addr where size >64KiB */ +#define ST_M95_RDID_INSIZE 0x03 + + /* Some Atmel AT25F* models have bit 3 as don't care bit in commands */ #define AT25F_RDID 0x15 /* 0x15 or 0x1d */ #define AT25F_RDID_OUTSIZE 0x01 diff --git a/spi25.c b/spi25.c index 2a1d492..ec35585 100644 --- a/spi25.c +++ b/spi25.c @@ -21,6 +21,7 @@ #include <stddef.h> #include <string.h> #include <stdbool.h> +#include <stdlib.h> #include "flash.h" #include "flashchips.h" #include "chipdrivers.h" @@ -262,6 +263,32 @@ return 1; } +/* Only used for some stm95080 and higher chip. */ +int probe_spi_st95(struct flashctx *flash) +{ + /* ST_M95_RDID_OUTSIZE depends on size of the flash and + * not all ST_M95XXX have RDID + */ + static const unsigned char cmd[ST_M95_RDID_OUTSIZE] = {ST_M95_RDID}; + unsigned char readarr[ST_M95_RDID_INSIZE]; + uint32_t id1, id2; + + spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr); + + id1 = readarr[0]; // manufacture id + id2 = readarr[2]; // model id + + msg_ginfo("RDID[%s: id1 0x%02x, id2 0x%02x, " + "L 0x%02x, M 0x%02x, H 0x%02x]\n", + __func__, flash->chip->manufacture_id, flash->chip->model_id, + readarr[0], readarr[1], readarr[2]); + + if (id1 == flash->chip->manufacture_id && id2 == flash->chip->model_id) + return 1; + + return 0; +} + /* Only used for some Atmel chips. */ int probe_spi_at25f(struct flashctx *flash) { @@ -440,6 +467,13 @@ return result ? result : status; } +static int spi_nbyte_program(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len) +{ + const bool native_4ba = flash->chip->feature_bits & FEATURE_4BA_WRITE && spi_master_4ba(flash); + const uint8_t op = native_4ba ? JEDEC_BYTE_PROGRAM_4BA : JEDEC_BYTE_PROGRAM; + return spi_write_cmd(flash, op, native_4ba, addr, bytes, len, 10); +} + static int spi_chip_erase_60(struct flashctx *flash) { /* This usually takes 1-85s, so wait in 1s steps. */ @@ -577,6 +611,33 @@ return spi_write_cmd(flash, 0xdc, true, addr, NULL, 0, 100 * 1000); } +/* some chips don't have erase function */ +int spi_block_erase_emulation(struct flashctx *flash, unsigned int addr, unsigned int blocklen) +{ + unsigned int i; + const unsigned int erase_len = flash->chip->page_size; + uint8_t *erased_contents = NULL; + int result = 0; + + erased_contents = (uint8_t*) malloc(erase_len * sizeof(uint8_t)); + if (!erased_contents) { + msg_cerr("Out of memory!\n"); + return 1; + } + + memset(erased_contents, ERASED_VALUE(flash), erase_len * sizeof(uint8_t)); + msg_cinfo("\n"); + for (i = addr; i < blocklen; i+=erase_len) { + if (spi_nbyte_program(flash, i, erased_contents, erase_len)) { + result = 1; + break; + } + } + + free(erased_contents); + return result; +} + erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode) { switch(opcode){ @@ -619,13 +680,6 @@ } } -static int spi_nbyte_program(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len) -{ - const bool native_4ba = flash->chip->feature_bits & FEATURE_4BA_WRITE && spi_master_4ba(flash); - const uint8_t op = native_4ba ? JEDEC_BYTE_PROGRAM_4BA : JEDEC_BYTE_PROGRAM; - return spi_write_cmd(flash, op, native_4ba, addr, bytes, len, 10); -} - int spi_nbyte_read(struct flashctx *flash, unsigned int address, uint8_t *bytes, unsigned int len) { -- To view, visit https://review.coreboot.org/c/flashrom/+/34496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic29cd9051c7eac4822d620c299834134f987f01b Gerrit-Change-Number: 34496 Gerrit-PatchSet: 1 Gerrit-Owner: Konstantin Grudnev <grudnevkv(a)gmail.com> Gerrit-MessageType: newchange

2 13

Change in flashrom[master]: tree: Enable -Wwrite-strings
by Jacob Garber (Code Review) Oct. 4, 2019

Oct. 4, 2019

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34577 ) Change subject: tree: Enable -Wwrite-strings ...................................................................... tree: Enable -Wwrite-strings When compiling, this warning gives string literals the type const char[] to help catch accidental modification (which is undefined behaviour). There currently aren't any instances of this in flashrom, so let's enable this warning to keep it that way. This requires adding const qualifiers to the declarations of several variables that work with string literals. Change-Id: I62d9bc194938a0c9a0e4cdff7ced8ea2e14cc1bc Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M Makefile M buspirate_spi.c M cli_classic.c M dmi.c M pony_spi.c M util/ich_descriptors_tool/ich_descriptors_tool.c 6 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/77/34577/1 diff --git a/Makefile b/Makefile index 545e84a..1a20933 100644 --- a/Makefile +++ b/Makefile @@ -30,7 +30,7 @@ DIFF = diff PREFIX ?= /usr/local MANDIR ?= $(PREFIX)/share/man -CFLAGS ?= -Os -Wall -Wshadow -Wmissing-prototypes +CFLAGS ?= -Os -Wall -Wshadow -Wmissing-prototypes -Wwrite-strings EXPORTDIR ?= . RANLIB ?= ranlib PKG_CONFIG ?= pkg-config diff --git a/buspirate_spi.c b/buspirate_spi.c index fb066c2..bc6776b 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -112,7 +112,7 @@ return 0; } -static int buspirate_wait_for_string(unsigned char *buf, char *key) +static int buspirate_wait_for_string(unsigned char *buf, const char *key) { unsigned int keylen = strlen(key); int ret; diff --git a/cli_classic.c b/cli_classic.c index 0591bfe..428efc1 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -77,7 +77,7 @@ exit(1); } -static int check_filename(char *filename, char *type) +static int check_filename(char *filename, const char *type) { if (!filename || (filename[0] == '\0')) { fprintf(stderr, "Error: No %s file specified.\n", type); diff --git a/dmi.c b/dmi.c index ae90f7c..6132b47 100644 --- a/dmi.c +++ b/dmi.c @@ -69,7 +69,7 @@ static const struct { uint8_t type; uint8_t is_laptop; - char *name; + const char *name; } dmi_chassis_types[] = { {0x01, 2, "Other"}, {0x02, 2, "Unknown"}, diff --git a/pony_spi.c b/pony_spi.c index 6c03308..ed9d326 100644 --- a/pony_spi.c +++ b/pony_spi.c @@ -115,7 +115,7 @@ int i, data_out; char *arg = NULL; enum pony_type type = TYPE_SI_PROG; - char *name; + const char *name; int have_device = 0; int have_prog = 0; diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 2c7966d..768401e 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -111,7 +111,7 @@ printf("\n"); } -static void usage(char *argv[], char *error) +static void usage(char *argv[], const char *error) { if (error != NULL) { fprintf(stderr, "%s\n", error); -- To view, visit https://review.coreboot.org/c/flashrom/+/34577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I62d9bc194938a0c9a0e4cdff7ced8ea2e14cc1bc Gerrit-Change-Number: 34577 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

6 8

Change in flashrom[master]: Removed strndup because it is not available in MingW
by Miklós Márton (Code Review) Oct. 4, 2019

Oct. 4, 2019

Miklós Márton has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34621 ) Change subject: Removed strndup because it is not available in MingW ...................................................................... Removed strndup because it is not available in MingW Signed-off-by: Miklós Márton <martonmiklosqdev(a)gmail.com> Change-Id: If418080bffff1f5961cacf2a300ea9c666682458 --- M libflashrom.c 1 file changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/21/34621/1 diff --git a/libflashrom.c b/libflashrom.c index af62002..a1c0a9c 100644 --- a/libflashrom.c +++ b/libflashrom.c @@ -371,6 +371,7 @@ struct flashctx *const flashctx, const struct fmap *const fmap) { int i; + size_t len; struct flashrom_layout *l = get_global_layout(); if (!fmap || !l) @@ -385,8 +386,15 @@ l->entries[l->num_entries].start = fmap->areas[i].offset; l->entries[l->num_entries].end = fmap->areas[i].offset + fmap->areas[i].size - 1; l->entries[l->num_entries].included = false; - l->entries[l->num_entries].name = - strndup((const char *)fmap->areas[i].name, FMAP_STRLEN); + // MingW does not have strndup + len = strlen((const char *)fmap->areas[i].name); + if (len > (FMAP_STRLEN - 1)) + len = (FMAP_STRLEN - 1); + l->entries[l->num_entries].name = malloc(len + 1); + strncpy(l->entries[l->num_entries].name, + (const char *)fmap->areas[i].name, + len); + l->entries[l->num_entries].name[len] = '\0'; if (!l->entries[l->num_entries].name) { msg_gerr("Error adding layout entry: %s\n", strerror(errno)); return 1; -- To view, visit https://review.coreboot.org/c/flashrom/+/34621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If418080bffff1f5961cacf2a300ea9c666682458 Gerrit-Change-Number: 34621 Gerrit-PatchSet: 1 Gerrit-Owner: Miklós Márton <martonmiklosqdev(a)gmail.com> Gerrit-MessageType: newchange

2 8

Change in ...flashrom[master]: flashchips.c: Sort file by vendor and model
by Alan Green (Code Review) Aug. 22, 2019

Aug. 22, 2019

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/33931 Change subject: flashchips.c: Sort file by vendor and model ...................................................................... flashchips.c: Sort file by vendor and model For self-consistency, and to allow tools to assist with merging the chromium fork of flashrom, sort the entries of flashchips.c. The file is already largely sorted, though deviations have crept in over time. This is a non-clever mostly ASCII-order sorting. It is not intended to be permanent. Post-merge we can explore options such as breaking apart flashchips.c into per-vendor files or directories. Change-Id: I75a99583592526f60ba5264e92391bf8b1213b20 --- M flashchips.c 1 file changed, 5,510 insertions(+), 5,510 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/31/33931/1 -- To view, visit https://review.coreboot.org/c/flashrom/+/33931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I75a99583592526f60ba5264e92391bf8b1213b20 Gerrit-Change-Number: 33931 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

5 19

Change in flashrom[master]: chipset_enable: Mark Intel/CM246 as DEP
by Nico Huber (Code Review) Aug. 8, 2019

Aug. 8, 2019

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34073 ) Change subject: chipset_enable: Mark Intel/CM246 as DEP ...................................................................... chipset_enable: Mark Intel/CM246 as DEP The usual ME-lock limitations apply, so this is DEP instead of OK. Tested on Siemens/Field PG M6, and also regression tested on Apollo Lake and Skylake. Flashrom works fine, and logs and descriptor dumps look good. Also, register and descriptor output agree on the flash layout and permissions. Change-Id: I40db4773f127bec63e377e1d2ab402b47edf9a61 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/34073/1 diff --git a/chipset_enable.c b/chipset_enable.c index 3773158..f75f94d 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2044,7 +2044,7 @@ {0x8086, 0xa30a, B_S, NT, "Intel", "C242", enable_flash_pch300}, {0x8086, 0xa30c, B_S, NT, "Intel", "QM370", enable_flash_pch300}, {0x8086, 0xa30d, B_S, NT, "Intel", "HM370", enable_flash_pch300}, - {0x8086, 0xa30e, B_S, NT, "Intel", "CM246", enable_flash_pch300}, + {0x8086, 0xa30e, B_S, DEP, "Intel", "CM246", enable_flash_pch300}, #endif {0}, }; -- To view, visit https://review.coreboot.org/c/flashrom/+/34073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I40db4773f127bec63e377e1d2ab402b47edf9a61 Gerrit-Change-Number: 34073 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

2 3

Change in flashrom[master]: chipset_enable: Add support for Cannon Lake U Premium
by Matt DeVillier (Code Review) Aug. 8, 2019

Aug. 8, 2019

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34076 ) Change subject: chipset_enable: Add support for Cannon Lake U Premium ...................................................................... chipset_enable: Add support for Cannon Lake U Premium Add support for Cannon Lake U Premium (CFL-U/WHL-U). Same as discrete 300-series CNP PCH. Tested on out-of-tree WHL-U board. Change-Id: I8a318d63cf408a3b2cec436a3fa6e26cf8552ead Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M chipset_enable.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/76/34076/1 diff --git a/chipset_enable.c b/chipset_enable.c index 3773158..e880e73 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1995,6 +1995,7 @@ {0x8086, 0x9d53, B_S, NT, "Intel", "Kaby Lake U Base", enable_flash_pch100}, {0x8086, 0x9d56, B_S, NT, "Intel", "Kaby Lake Y Premium", enable_flash_pch100}, {0x8086, 0x9d58, B_S, NT, "Intel", "Kaby Lake U Premium", enable_flash_pch100}, + {0x8086, 0x9d84, B_S, NT, "Intel", "Cannon Lake U Premium", enable_flash_pch300}, {0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100}, {0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100}, {0x8086, 0xa143, B_S, NT, "Intel", "H110", enable_flash_pch100}, -- To view, visit https://review.coreboot.org/c/flashrom/+/34076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8a318d63cf408a3b2cec436a3fa6e26cf8552ead Gerrit-Change-Number: 34076 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

2 7

Change in flashrom[master]: ichspi: Add support for discrete Cannon Lake PCHs
by Nico Huber (Code Review) Aug. 8, 2019

Aug. 8, 2019

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34072 ) Change subject: ichspi: Add support for discrete Cannon Lake PCHs ...................................................................... ichspi: Add support for discrete Cannon Lake PCHs Only minor differences in the Firmware Descriptor, compared to their predecessors. We extend our check on the `ICCRIBA` field in the descriptor to dis- tinguish it from older generation. Alas, the `freq_read` field was repurposed, so we can't use it as sanity check any more. Change-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipset_enable.c M ich_descriptors.c M ich_descriptors.h M ichspi.c M util/ich_descriptors_tool/ich_descriptors_tool.c 5 files changed, 87 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/72/34072/1 diff --git a/chipset_enable.c b/chipset_enable.c index 4b0bab5..3773158 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2035,16 +2035,16 @@ {0x8086, 0xa2c9, B_S, NT, "Intel", "Z370", enable_flash_pch100}, {0x8086, 0xa2d2, B_S, NT, "Intel", "X299", enable_flash_pch100}, {0x8086, 0x5ae8, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, - {0x8086, 0xa303, B_S, BAD, "Intel", "H310", enable_flash_pch300}, - {0x8086, 0xa304, B_S, BAD, "Intel", "H370", enable_flash_pch300}, - {0x8086, 0xa305, B_S, BAD, "Intel", "Z390", enable_flash_pch300}, - {0x8086, 0xa306, B_S, BAD, "Intel", "Q370", enable_flash_pch300}, - {0x8086, 0xa308, B_S, BAD, "Intel", "B360", enable_flash_pch300}, - {0x8086, 0xa309, B_S, BAD, "Intel", "C246", enable_flash_pch300}, - {0x8086, 0xa30a, B_S, BAD, "Intel", "C242", enable_flash_pch300}, - {0x8086, 0xa30c, B_S, BAD, "Intel", "QM370", enable_flash_pch300}, - {0x8086, 0xa30d, B_S, BAD, "Intel", "HM370", enable_flash_pch300}, - {0x8086, 0xa30e, B_S, BAD, "Intel", "CM246", enable_flash_pch300}, + {0x8086, 0xa303, B_S, NT, "Intel", "H310", enable_flash_pch300}, + {0x8086, 0xa304, B_S, NT, "Intel", "H370", enable_flash_pch300}, + {0x8086, 0xa305, B_S, NT, "Intel", "Z390", enable_flash_pch300}, + {0x8086, 0xa306, B_S, NT, "Intel", "Q370", enable_flash_pch300}, + {0x8086, 0xa308, B_S, NT, "Intel", "B360", enable_flash_pch300}, + {0x8086, 0xa309, B_S, NT, "Intel", "C246", enable_flash_pch300}, + {0x8086, 0xa30a, B_S, NT, "Intel", "C242", enable_flash_pch300}, + {0x8086, 0xa30c, B_S, NT, "Intel", "QM370", enable_flash_pch300}, + {0x8086, 0xa30d, B_S, NT, "Intel", "HM370", enable_flash_pch300}, + {0x8086, 0xa30e, B_S, NT, "Intel", "CM246", enable_flash_pch300}, #endif {0}, }; diff --git a/ich_descriptors.c b/ich_descriptors.c index a757add..9653d60 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -45,6 +45,7 @@ case CHIPSET_APOLLO_LAKE: return 6; case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: return 16; case CHIPSET_100_SERIES_SUNRISE_POINT: return 10; @@ -106,7 +107,7 @@ "5 series Ibex Peak", "6 series Cougar Point", "7 series Panther Point", "8 series Lynx Point", "Baytrail", "8 series Lynx Point LP", "8 series Wellsburg", "9 series Wildcat Point", "9 series Wildcat Point LP", "100 series Sunrise Point", - "C620 series Lewisburg", "Apollo Lake", + "C620 series Lewisburg", "300 series Cannon Point", "Apollo Lake", }; if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names)) cs = 0; @@ -198,6 +199,7 @@ case CHIPSET_9_SERIES_WILDCAT_POINT_LP: case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: { uint8_t size_enc; if (idx == 0) { @@ -265,6 +267,7 @@ return freq_str[0][value]; case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: return freq_str[1][value]; case CHIPSET_APOLLO_LAKE: return freq_str[2][value]; @@ -281,6 +284,7 @@ switch (cs) { case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: has_flill1 = true; break; @@ -398,7 +402,8 @@ msg_pdbg2("\n"); msg_pdbg2("--- Details ---\n"); - if (cs == CHIPSET_100_SERIES_SUNRISE_POINT) { + if (cs == CHIPSET_100_SERIES_SUNRISE_POINT || + cs == CHIPSET_300_SERIES_CANNON_POINT) { const char *const master_names[] = { "BIOS", "ME", "GbE", "unknown", "EC", }; @@ -408,14 +413,26 @@ return; } - msg_pdbg2(" FD BIOS ME GbE Pltf Reg5 Reg6 Reg7 EC Reg9\n"); + size_t num_regions; + msg_pdbg2(" FD BIOS ME GbE Pltf Reg5 Reg6 Reg7 EC Reg9"); + if (cs == CHIPSET_100_SERIES_SUNRISE_POINT) { + num_regions = 10; + msg_pdbg2("\n"); + } else { + num_regions = 16; + msg_pdbg2(" RegA RegB RegC RegD RegE RegF\n"); + } for (i = 0; i < nm; i++) { size_t j; msg_pdbg2("%-4s", master_names[i]); - for (j = 0; j < 10; j++) + for (j = 0; j < min(num_regions, 12); j++) msg_pdbg2(" %c%c ", desc->master.mstr[i].read & (1 << j) ? 'r' : ' ', desc->master.mstr[i].write & (1 << j) ? 'w' : ' '); + for (; j < num_regions; j++) + msg_pdbg2(" %c%c ", + desc->master.mstr[i].ext_read & (1 << (j - 12)) ? 'r' : ' ', + desc->master.mstr[i].ext_write & (1 << (j - 12)) ? 'w' : ' '); msg_pdbg2("\n"); } } else if (cs == CHIPSET_C620_SERIES_LEWISBURG) { @@ -919,10 +936,15 @@ return CHIPSET_8_SERIES_LYNX_POINT; msg_pwarn("Peculiar firmware descriptor, assuming Wildcat Point compatibility.\n"); return CHIPSET_9_SERIES_WILDCAT_POINT; - } else if (content->NM == 6) { - return CHIPSET_C620_SERIES_LEWISBURG; + } else if (content->ICCRIBA < 0x34) { + if (content->NM == 6) + return CHIPSET_C620_SERIES_LEWISBURG; + else + return CHIPSET_100_SERIES_SUNRISE_POINT; } else { - return CHIPSET_100_SERIES_SUNRISE_POINT; + if (content->ICCRIBA > 0x34) + msg_pwarn("Unknown firmware descriptor, assuming 300 series compatibility.\n"); + return CHIPSET_300_SERIES_CANNON_POINT; } } @@ -938,6 +960,9 @@ const enum ich_chipset guess = guess_ich_chipset_from_content(content); switch (guess) { + case CHIPSET_300_SERIES_CANNON_POINT: + /* `freq_read` was repurposed, so can't check on it any more. */ + return guess; case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_APOLLO_LAKE: @@ -1089,6 +1114,7 @@ case CHIPSET_9_SERIES_WILDCAT_POINT_LP: case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; @@ -1123,6 +1149,7 @@ switch (cs) { case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: mmio_le_writel(control, spibar + PCH100_REG_FDOC); return mmio_le_readl(spibar + PCH100_REG_FDOD); diff --git a/ich_descriptors.h b/ich_descriptors.h index 4225286..c6bf5d8 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -170,8 +170,9 @@ * Chipset/Generation #FLREGs width (bits) * ICH8 .. Panther Point/7 5 13 * Lynx Point/8 .. Wildcat Point/9 7 15 - * Sunrise Point/100 .. 10 15 + * Sunrise Point/100 .. 200 Series 10 15 * Lewisburg/100 .. 16 15 + * Cannon Point/300 .. 16 15 */ union { uint32_t FLREGs[MAX_NUM_FLREGS]; /* Flash Descriptor Regions */ @@ -234,9 +235,10 @@ }; /* From Skylake on */ struct { - uint32_t :8, - read :12, - write :12; + uint32_t ext_read :4, + ext_write :4, + read :12, + write :12; } mstr[MAX_NUM_MASTERS]; }; }; diff --git a/ichspi.c b/ichspi.c index e1ede60..68bd5d7 100644 --- a/ichspi.c +++ b/ichspi.c @@ -395,15 +395,25 @@ pprint_reg(HSFS, FDONE, reg_val, ", "); pprint_reg(HSFS, FCERR, reg_val, ", "); pprint_reg(HSFS, AEL, reg_val, ", "); - if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT && - ich_generation != CHIPSET_C620_SERIES_LEWISBURG) { + switch (ich_generation) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: + break; + default: pprint_reg(HSFS, BERASE, reg_val, ", "); + break; } pprint_reg(HSFS, SCIP, reg_val, ", "); - if (ich_generation == CHIPSET_100_SERIES_SUNRISE_POINT || - ich_generation == CHIPSET_C620_SERIES_LEWISBURG) { + switch (ich_generation) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: pprint_reg(HSFS, PRR34_LOCKDN, reg_val, ", "); pprint_reg(HSFS, WRSDIS, reg_val, ", "); + break; + default: + break; } pprint_reg(HSFS, FDOPSS, reg_val, ", "); pprint_reg(HSFS, FDV, reg_val, ", "); @@ -414,12 +424,16 @@ { msg_pdbg("HSFC: "); pprint_reg(HSFC, FGO, reg_val, ", "); - if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT && - ich_generation != CHIPSET_C620_SERIES_LEWISBURG) { - pprint_reg(HSFC, FCYCLE, reg_val, ", "); - } else { + switch (ich_generation) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: _pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", "); pprint_reg(HSFC, WET, reg_val, ", "); + break; + default: + pprint_reg(HSFC, FCYCLE, reg_val, ", "); + break; } pprint_reg(HSFC, FDBC, reg_val, ", "); pprint_reg(HSFC, SME, reg_val, "\n"); @@ -1567,9 +1581,10 @@ static enum ich_access_protection ich9_handle_frap(uint32_t frap, int i) { const int rwperms_unknown = ARRAY_SIZE(access_names); - static const char *const region_names[6] = { + static const char *const region_names[] = { "Flash Descriptor", "BIOS", "Management Engine", "Gigabit Ethernet", "Platform Data", "Device Expansion", + "BIOS2", "unknown", "EC/BMC", }; const char *const region_name = i < ARRAY_SIZE(region_names) ? region_names[i] : "unknown"; @@ -1724,6 +1739,7 @@ switch (ich_generation) { case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: num_pr = 6; /* Includes GPR0 */ reg_pr0 = PCH100_REG_FPR0; @@ -1754,6 +1770,7 @@ case CHIPSET_C620_SERIES_LEWISBURG: num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */ break; + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: num_freg = 16; break; @@ -1848,6 +1865,7 @@ switch (ich_gen) { case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: tmp = mmio_readl(ich_spibar + PCH100_REG_DLOCK); msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp); @@ -1921,6 +1939,7 @@ case CHIPSET_ICH8: case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_BAYTRAIL: break; @@ -1952,6 +1971,7 @@ case CHIPSET_ICH8: case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: break; default: @@ -1981,8 +2001,10 @@ ich_spi_mode = ich_hwseq; } - if (ich_spi_mode == ich_auto && ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT) { - msg_pdbg("Enabling hardware sequencing by default for 100 series PCH.\n"); + if (ich_spi_mode == ich_auto && + (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT || + ich_gen == CHIPSET_300_SERIES_CANNON_POINT)) { + msg_pdbg("Enabling hardware sequencing by default for 100+ series PCH.\n"); ich_spi_mode = ich_hwseq; } diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 2c7966d..2db0f62 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -133,6 +133,7 @@ "\t- \"8\" or \"lynx\" for Intel's 8 series chipsets.\n" "\t- \"9\" or \"wildcat\" for Intel's 9 series chipsets.\n" "\t- \"100\" or \"sunrise\" for Intel's 100 series chipsets.\n" +"\t- \"300\" or \"cannon\" for Intel's 300 series chipsets.\n" "If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n" "the GbE blob that is required to initialize the GbE are also dumped to files.\n", argv[0], argv[0]); @@ -221,6 +222,9 @@ else if ((strcmp(csn, "100") == 0) || (strcmp(csn, "sunrise") == 0)) cs = CHIPSET_100_SERIES_SUNRISE_POINT; + else if ((strcmp(csn, "300") == 0) || + (strcmp(csn, "cannon") == 0)) + cs = CHIPSET_300_SERIES_CANNON_POINT; else if (strcmp(csn, "apollo") == 0) cs = CHIPSET_APOLLO_LAKE; } -- To view, visit https://review.coreboot.org/c/flashrom/+/34072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02 Gerrit-Change-Number: 34072 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in flashrom[master]: chipset_enable: Add support for discrete Cannon Lake PCHs
by Nico Huber (Code Review) Aug. 8, 2019

Aug. 8, 2019

Hello Thomas Heijligen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/flashrom/+/34071 to review the following change. Change subject: chipset_enable: Add support for discrete Cannon Lake PCHs ...................................................................... chipset_enable: Add support for discrete Cannon Lake PCHs The Cannon Lake "300 Series" PCHs [1,2] share the register layout of the Skylake "100 Series". Mark them as BAD until `ichspi.c` is adapted. [1] Intel® 300 Series and Intel® C240 Seri Chipset Family Platform Controller Hub Datasheet - Volume 1 of 2 Revison 4 (Dec 2018) Document Number 337347 [2] Intel® 300 Series Chipset Families Platform Controller Hu Datasheet - Volume 2 of 2 Revision 2? (Oct 2018) Document Number 337348 Change-Id: If0b54799d5b93169ee660409bad57ae14677340c Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipset_enable.c M programmer.h 2 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/71/34071/1 diff --git a/chipset_enable.c b/chipset_enable.c index 08feda5..4b0bab5 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -598,6 +598,7 @@ break; case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: reg_name = "BIOS_SPI_BC"; gcs = pci_read_long(dev, 0xdc); @@ -692,6 +693,7 @@ case CHIPSET_9_SERIES_WILDCAT_POINT_LP: case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: boot_straps = boot_straps_pch8_lp; break; case CHIPSET_APOLLO_LAKE: @@ -719,6 +721,7 @@ break; case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: bbs = (gcs >> 6) & 0x1; break; @@ -947,6 +950,11 @@ return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_C620_SERIES_LEWISBURG); } +static int enable_flash_pch300(struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_300_SERIES_CANNON_POINT); +} + static int enable_flash_apl(struct pci_dev *const dev, const char *const name) { return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE); @@ -2027,6 +2035,16 @@ {0x8086, 0xa2c9, B_S, NT, "Intel", "Z370", enable_flash_pch100}, {0x8086, 0xa2d2, B_S, NT, "Intel", "X299", enable_flash_pch100}, {0x8086, 0x5ae8, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, + {0x8086, 0xa303, B_S, BAD, "Intel", "H310", enable_flash_pch300}, + {0x8086, 0xa304, B_S, BAD, "Intel", "H370", enable_flash_pch300}, + {0x8086, 0xa305, B_S, BAD, "Intel", "Z390", enable_flash_pch300}, + {0x8086, 0xa306, B_S, BAD, "Intel", "Q370", enable_flash_pch300}, + {0x8086, 0xa308, B_S, BAD, "Intel", "B360", enable_flash_pch300}, + {0x8086, 0xa309, B_S, BAD, "Intel", "C246", enable_flash_pch300}, + {0x8086, 0xa30a, B_S, BAD, "Intel", "C242", enable_flash_pch300}, + {0x8086, 0xa30c, B_S, BAD, "Intel", "QM370", enable_flash_pch300}, + {0x8086, 0xa30d, B_S, BAD, "Intel", "HM370", enable_flash_pch300}, + {0x8086, 0xa30e, B_S, BAD, "Intel", "CM246", enable_flash_pch300}, #endif {0}, }; diff --git a/programmer.h b/programmer.h index f4e8b46..4a51243 100644 --- a/programmer.h +++ b/programmer.h @@ -626,6 +626,7 @@ CHIPSET_9_SERIES_WILDCAT_POINT_LP, CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) variants */ CHIPSET_C620_SERIES_LEWISBURG, + CHIPSET_300_SERIES_CANNON_POINT, CHIPSET_APOLLO_LAKE, }; -- To view, visit https://review.coreboot.org/c/flashrom/+/34071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If0b54799d5b93169ee660409bad57ae14677340c Gerrit-Change-Number: 34071 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips: Split MT25Q from N25Q
by Jacob Creedon (Code Review) Aug. 5, 2019

Aug. 5, 2019

Jacob Creedon has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34488 ) Change subject: flashchips: Split MT25Q from N25Q ...................................................................... flashchips: Split MT25Q from N25Q The MT25Q is the successor to the N25Q from Micron/Numonyx/ST. The MT25Q is almost entirely backwards compatible with the N25Q series, however, the MT25Q has additional subsector erase commands available, and there are differences in stacked devices in the higher capacity variants. The N25Q devices are left with "Micron/Numonyx/ST" as the vendor and MT25Q devices are set with "Micron" as the vendor. Signed-off-by: Jacob Creedon <jcreedon(a)google.com> Change-Id: I9d79978544b19cf9acd5f3ea6196cf6f3b3435ef --- M flashchips.c 1 file changed, 82 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/88/34488/1 diff --git a/flashchips.c b/flashchips.c index 166af6a..e6116ae 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10544,8 +10544,88 @@ }, { + .vendor = "Micron/Numonyx/ST", + .name = "N25Q256..3E", /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q256__3E, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32768 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Micron/Numonyx/ST", + .name = "N25Q512..3E", /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q512__3E, + .total_size = 65536, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 16384} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 16384} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 1024} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 1024} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {65536 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { .vendor = "Micron", - .name = "N25Q256..3E/MT25QL256", /* ..3E/L = 3V, uniform 64KB/4KB blocks/sectors */ + .name = "MT25QL256", /* L = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, .model_id = ST_N25Q256__3E, @@ -10585,7 +10665,7 @@ { .vendor = "Micron", - .name = "N25Q512..3E/MT25QL512", /* ..3E/L = 3V, uniform 64KB/4KB blocks/sectors */ + .name = "MT25QL512", /* L = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, .model_id = ST_N25Q512__3E, -- To view, visit https://review.coreboot.org/c/flashrom/+/34488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I9d79978544b19cf9acd5f3ea6196cf6f3b3435ef Gerrit-Change-Number: 34488 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Creedon <jcreedon(a)google.com> Gerrit-MessageType: newchange

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