December 2018 - flashrom-gerrit

Change in ...flashrom[master]: dediprog: Use 4BA page program without 0x12
by David Hendricks (Code Review) Aug. 25, 2020

Aug. 25, 2020

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/30521 Change subject: dediprog: Use 4BA page program without 0x12 ...................................................................... dediprog: Use 4BA page program without 0x12 It's not clear exactly what the difference is between WRITE_MODE_4B_ADDR_256B_PAGE_PGM with and without _0x12 from the SF600 command spec, but the former seems to work more reliably. Tested using an SF600 (FW v7.2.21), IS25LP256D, W25Q256JV, and MX25L25735. Change-Id: I3cb37ec8838f5bb02948ed52b4a2906fa033cf83 Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- M dediprog.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/21/30521/1 diff --git a/dediprog.c b/dediprog.c index 2a190d2..303f1d5 100644 --- a/dediprog.c +++ b/dediprog.c @@ -398,7 +398,8 @@ } } else if (dedi_spi_cmd == WRITE_MODE_PAGE_PGM) { if (flash->chip->feature_bits & FEATURE_4BA_WRITE) { - data_packet[3] = WRITE_MODE_4B_ADDR_256B_PAGE_PGM_0x12; +// data_packet[3] = WRITE_MODE_4B_ADDR_256B_PAGE_PGM_0x12; + data_packet[3] = WRITE_MODE_4B_ADDR_256B_PAGE_PGM; data_packet[4] = JEDEC_BYTE_PROGRAM_4BA; use_4ba = true; } else if (flash->in_4ba_mode) { -- To view, visit https://review.coreboot.org/c/flashrom/+/30521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3cb37ec8838f5bb02948ed52b4a2906fa033cf83 Gerrit-Change-Number: 30521 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...flashrom[master]: dediprog: Break apart large (>=32MiB) transfers
by David Hendricks (Code Review) June 20, 2019

June 20, 2019

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/30520 Change subject: dediprog: Break apart large (>=32MiB) transfers ...................................................................... dediprog: Break apart large (>=32MiB) transfers The 2-byte length defined in the command spec appears to be 1-based, that is to say that we can transfer 65536 - 1 data packets of 512 bytes in one bulk read request, just shy of 32MiB. Attempting to read >=32MiB at once will result in bulk read failure (with "SPI bulk read failed!" messages). This patch breaks the transfer at 32MiB - 512 bytes to avoid that. Tested using an SF600 (FW v7.2.21), IS25LP256D, W25Q256JV, and MX25L25735. Change-Id: Ia42253137719607c1525581049239cc9e88880a3 Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- M dediprog.c 1 file changed, 23 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/20/30520/1 diff --git a/dediprog.c b/dediprog.c index 7738459..2a190d2 100644 --- a/dediprog.c +++ b/dediprog.c @@ -557,6 +557,7 @@ const unsigned int chunksize = 0x200; unsigned int residue = start % chunksize ? min(len, chunksize - start % chunksize) : 0; unsigned int bulklen; + uint32_t max_xfer = 0x2000000 - chunksize; dediprog_set_leds(LED_BUSY); @@ -570,18 +571,31 @@ /* Round down. */ bulklen = (len - residue) / chunksize * chunksize; - ret = dediprog_spi_bulk_read(flash, buf + residue, start + residue, bulklen); - if (ret) - goto err; - len -= residue + bulklen; - if (len != 0) { - msg_pdbg("Slow read for partial block from 0x%x, length 0x%x\n", - start, len); - ret = spi_read_chunked(flash, buf + residue + bulklen, - start + residue + bulklen, len, 16); + /* Break apart large transfers (32MB - chunksize) to avoid "SPI bulk + * read failed!" errors */ + while (bulklen > 0) { + unsigned int xfer_size = min(bulklen, max_xfer); + ret = dediprog_spi_bulk_read(flash, buf + residue, start + residue, xfer_size); if (ret) goto err; + + len -= residue + xfer_size; + if (len == chunksize) { + ret = dediprog_spi_bulk_read(flash, + buf + residue + xfer_size, + start + residue + xfer_size, chunksize); + len -= chunksize; + bulklen -= chunksize; + } else if (len != 0) { + msg_pdbg("Slow read for partial block from 0x%x, length 0x%x\n", + start, len); + ret = spi_read_chunked(flash, buf + residue + xfer_size, + start + residue + xfer_size, len, 16); + if (ret) + goto err; + } + bulklen -= xfer_size; } dediprog_set_leds(LED_PASS); -- To view, visit https://review.coreboot.org/c/flashrom/+/30520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia42253137719607c1525581049239cc9e88880a3 Gerrit-Change-Number: 30520 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...flashrom[master]: WIP: flashchips: Use 4BA for W25Q256JV
by David Hendricks (Code Review) Dec. 30, 2018

Dec. 30, 2018

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/30522 Change subject: WIP: flashchips: Use 4BA for W25Q256JV ...................................................................... WIP: flashchips: Use 4BA for W25Q256JV For some reason W25Q256JV must use native 4BA instructions to work with 4BA addresses on Dediprog SF600 programmers. This just makes the W25Q256JV work with the SF600 and should not be committed. Marking as WIP for now. Change-Id: I8359dd665a9dfa2eba520d03fcddc2654b598fda Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- M flashchips.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/22/30522/1 diff --git a/flashchips.c b/flashchips.c index d85ea74..2c3356b 100644 --- a/flashchips.c +++ b/flashchips.c @@ -15759,7 +15759,8 @@ /* supports SFDP */ /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA, +// .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_NATIVE, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, -- To view, visit https://review.coreboot.org/c/flashrom/+/30522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8359dd665a9dfa2eba520d03fcddc2654b598fda Gerrit-Change-Number: 30522 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...flashrom[master]: Case change of a letter to be able to resubmit patchset due to CI fai...
by Miklós Márton (Code Review) Dec. 27, 2018

Dec. 27, 2018

Miklós Márton has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/30459 Change subject: Case change of a letter to be able to resubmit patchset due to CI failure ...................................................................... Case change of a letter to be able to resubmit patchset due to CI failure Change-Id: I8cb2d93be9d38ae352a83ac909f90ca17fa6ffd4 --- M ni845x_spi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/59/30459/1 diff --git a/ni845x_spi.c b/ni845x_spi.c index ce2f439..7d67b00 100644 --- a/ni845x_spi.c +++ b/ni845x_spi.c @@ -35,7 +35,7 @@ static const struct spi_master spi_programmer_ni845x; -static unsigned char CS_number = 0; // use Chip select 0 as default +static unsigned char CS_number = 0; // use chip select 0 as default static enum USB845x_type device_pid = Unknown_NI845X_Device; static uInt32 device_handle = 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/30459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8cb2d93be9d38ae352a83ac909f90ca17fa6ffd4 Gerrit-Change-Number: 30459 Gerrit-PatchSet: 1 Gerrit-Owner: Miklós Márton <martonmiklosqdev(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...flashrom[master]: manibuilder: Add list of tags used for the 1.0.x branch
by Nico Huber (Code Review) Dec. 24, 2018

Dec. 24, 2018

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/30418 to look at the new patch set (#2). Change subject: manibuilder: Add list of tags used for the 1.0.x branch ...................................................................... manibuilder: Add list of tags used for the 1.0.x branch Also add two new make targets `1.0.x` and `show-1.0.x`. Change-Id: I2bc2e79729016a8f9908f316b051deeb73dc096f Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/manibuilder/Makefile.targets 1 file changed, 55 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/18/30418/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/30418 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2bc2e79729016a8f9908f316b051deeb73dc096f Gerrit-Change-Number: 30418 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...flashrom[master]: Add Manibuilder
by Nico Huber (Code Review) Dec. 24, 2018

Dec. 24, 2018

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/23005 ) Change subject: Add Manibuilder ...................................................................... Patch Set 2: In case somebody wants to play with this too... it's documented a little now. -- To view, visit https://review.coreboot.org/c/flashrom/+/23005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I60863a5c7d70dde71486fccb66cb59b30ba4d982 Gerrit-Change-Number: 23005 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 24 Dec 2018 14:18:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...flashrom[master]: Add list of tags used for the 1.0.x release branch
by Nico Huber (Code Review) Dec. 24, 2018

Dec. 24, 2018

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/30418 Change subject: Add list of tags used for the 1.0.x release branch ...................................................................... Add list of tags used for the 1.0.x release branch Also add two new make targets `1.0.x` and `show-1.0.x`. Change-Id: I2bc2e79729016a8f9908f316b051deeb73dc096f Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/manibuilder/Makefile.targets 1 file changed, 55 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/18/30418/1 diff --git a/util/manibuilder/Makefile.targets b/util/manibuilder/Makefile.targets index b1aee29..044b0a4 100644 --- a/util/manibuilder/Makefile.targets +++ b/util/manibuilder/Makefile.targets @@ -65,12 +65,62 @@ # also run all native tests by default DEFAULT_TAGS += $(filter-out $(DEFAULT_TAGS),$(NATIVE_TAGS)) +# original 1.0.x tags +10X_TAGS := \ + anita\:amd64 \ + anita\:i386 \ + djgpp\:6.1.0 \ + alpine\:amd64-v3.6 \ + alpine\:amd64-v3.7 \ + alpine\:i386-v3.6 \ + alpine\:i386-v3.7 \ + centos\:7.2-amd64-clean \ + centos\:7.3-aarch64-clean \ + centos\:7.3-amd64-clean \ + debian-debootstrap\:amd64-sid \ + debian-debootstrap\:amd64-stretch \ + debian-debootstrap\:armhf-stretch \ + debian-debootstrap\:i386-sid \ + debian-debootstrap\:i386-stretch \ + debian-debootstrap\:mips-stretch \ + debian-debootstrap\:mipsel-stretch \ + debian-debootstrap\:powerpc-sid \ + debian-debootstrap\:ppc64el-stretch \ + fedora\:24-x86_64 \ + fedora\:25-aarch64 \ + fedora\:25-ppc64le \ + fedora\:25-x86_64 \ + ubuntu-debootstrap\:amd64-xenial \ + ubuntu-debootstrap\:amd64-zesty \ + ubuntu-debootstrap\:arm64-xenial \ + ubuntu-debootstrap\:i386-xenial \ + ubuntu-debootstrap\:i386-zesty \ + +# additional tags added after initial release +10X_TAGS += \ + alpine\:aarch64-v3.8 \ + alpine\:armhf-v3.8 \ + alpine\:amd64-v3.8 \ + alpine\:i386-v3.8 \ + debian-debootstrap\:amd64-buster \ + debian-debootstrap\:arm64-buster \ + debian-debootstrap\:i386-buster \ + ubuntu-debootstrap\:amd64-bionic \ + ubuntu-debootstrap\:arm64-bionic \ + ubuntu-debootstrap\:i386-bionic \ + +# can only run what is still maintained +10X_TAGS := $(filter $(10X_TAGS),$(ALL_TAGS)) + default: $(DEFAULT_TAGS) native: $(NATIVE_TAGS) all: $(ALL_TAGS) +1.0.x: export TEST_REVISION=refs/heads/1.0.x +1.0.x: $(10X_TAGS) + show-default: @printf "%s\n" $(DEFAULT_TAGS) @@ -80,6 +130,9 @@ show-all: @printf "%s\n" $(ALL_TAGS) -.PHONY: default native all -.PHONY: show-default show-native show-all +show-1.0.x: + @printf "%s\n" $(10X_TAGS) + +.PHONY: default native all 1.0.x +.PHONY: show-default show-native show-all show-1.0.x .PHONY: $(ALL_TAGS) -- To view, visit https://review.coreboot.org/c/flashrom/+/30418 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2bc2e79729016a8f9908f316b051deeb73dc096f Gerrit-Change-Number: 30418 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...flashrom[master]: Fix -Wsign-compare trouble
by Nico Huber (Code Review) Dec. 23, 2018

Dec. 23, 2018

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/30409 to look at the new patch set (#2). Change subject: Fix -Wsign-compare trouble ...................................................................... Fix -Wsign-compare trouble Mostly by changing to `unsigned` types where applicable, sometimes `signed` types, and casting as a last resort. Change-Id: I08895543ffb7a48058bcf91ef6500ca113f2d305 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M 82802ab.c M at45db.c M bitbang_spi.c M board_enable.c M buspirate_spi.c M cbtable.c M cli_classic.c M dediprog.c M dmi.c M dummyflasher.c M en29lv640b.c M flash.h M flashrom.c M fmap.c M helpers.c M ich_descriptors.c M ichspi.c M it85spi.c M it87spi.c M jedec.c M layout.c M pickit2_spi.c M print.c M programmer.h M sb600spi.c M serial.c M serprog.c M sst28sf040.c M sst_fwhub.c M usbblaster_spi.c M wbsio_spi.c 31 files changed, 115 insertions(+), 107 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/09/30409/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/30409 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I08895543ffb7a48058bcf91ef6500ca113f2d305 Gerrit-Change-Number: 30409 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...flashrom[master]: Fix -Wunused-parameter issues
by Nico Huber (Code Review) Dec. 23, 2018

Dec. 23, 2018

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/30410 Change subject: Fix -Wunused-parameter issues ...................................................................... Fix -Wunused-parameter issues Issue statements with the parameters casted to `void`. Alternatively we could use __attribute__ ((unused)). Change-Id: If831398c91e9f49bd5216a03ed4caaa2a7ab02bd Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M 82802ab.c M atavia.c M buspirate_spi.c M cbtable.c M ch341a_spi.c M chipset_enable.c M dediprog.c M developerbox_spi.c M digilent_spi.c M dmi.c M drkaiser.c M dummyflasher.c M ft2232_spi.c M gfxnvidia.c M hwaccess.c M internal.c M it8212.c M it85spi.c M it87spi.c M jedec.c M libflashrom.c M linux_mtd.c M linux_spi.c M nic3com.c M nicintel.c M nicintel_eeprom.c M nicintel_spi.c M nicrealtek.c M pcidev.c M pickit2_spi.c M pony_spi.c M programmer.c M rayer_spi.c M satamv.c M satasii.c M sb600spi.c M serial.c M serprog.c M spi25.c M sst28sf040.c M sst49lfxxxc.c M udelay.c M usbblaster_spi.c M usbdev.c M w39.c M wbsio_spi.c 46 files changed, 258 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/10/30410/1 diff --git a/82802ab.c b/82802ab.c index 281b66e..6963ed0 100644 --- a/82802ab.c +++ b/82802ab.c @@ -104,6 +104,8 @@ int erase_block_82802ab(struct flashctx *flash, unsigned int page, unsigned int pagesize) { + (void)pagesize; + chipaddr bios = flash->virtual_memory; uint8_t status; diff --git a/atavia.c b/atavia.c index 80bba58..8fdaee1 100644 --- a/atavia.c +++ b/atavia.c @@ -116,6 +116,8 @@ void *atavia_map(const char *descr, uintptr_t phys_addr, size_t len) { + (void)descr; + (void)len; return (atavia_offset != 0) ? atavia_offset : (void *)phys_addr; } @@ -167,6 +169,8 @@ static void atavia_chip_writeb(const struct flashctx *flash, uint8_t val, const chipaddr addr) { + (void)flash; + msg_pspew("%s: 0x%02x to 0x%*" PRIxPTR ".\n", __func__, val, PRIxPTR_WIDTH, addr); pci_write_long(dev, BROM_ADDR, (addr & ~3)); pci_write_long(dev, BROM_DATA, val << BYTE_OFFSET(addr)); @@ -179,6 +183,8 @@ static uint8_t atavia_chip_readb(const struct flashctx *flash, const chipaddr addr) { + (void)flash; + pci_write_long(dev, BROM_ADDR, (addr & ~3)); pci_write_byte(dev, BROM_ACCESS, BROM_TRIGGER | ENABLE_BYTE(addr)); diff --git a/buspirate_spi.c b/buspirate_spi.c index d64f7d7..8447ba2 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -168,6 +168,8 @@ static int buspirate_spi_shutdown(void *data) { + (void)data; + int ret = 0, ret2 = 0; /* No need to allocate a buffer here, we know that bp_commbuf is at least DEFAULT_BUFSIZE big. */ @@ -576,6 +578,8 @@ static int buspirate_spi_send_command_v1(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { + (void)flash; + unsigned int i = 0; int ret = 0; @@ -629,6 +633,8 @@ static int buspirate_spi_send_command_v2(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { + (void)flash; + int i = 0, ret = 0; if (writecnt > 4096 || readcnt > 4096 || (readcnt + writecnt) > 4096) diff --git a/cbtable.c b/cbtable.c index bdf53ce..77060c6 100644 --- a/cbtable.c +++ b/cbtable.c @@ -194,7 +194,7 @@ return NULL; } -static void find_mainboard(struct lb_record *ptr, unsigned long addr) +static void find_mainboard(struct lb_record *ptr) { struct lb_mainboard *rec; int max_size; @@ -219,18 +219,17 @@ return (struct lb_record *)(((char *)rec) + rec->size); } -static void search_lb_records(struct lb_record *rec, struct lb_record *last, unsigned long addr) +static void search_lb_records(struct lb_record *rec, struct lb_record *last) { struct lb_record *next; int count; count = 0; - for (next = next_record(rec); (rec < last) && (next <= last); - rec = next, addr += rec->size) { + for (next = next_record(rec); (rec < last) && (next <= last); rec = next) { next = next_record(rec); count++; if (rec->tag == LB_TAG_MAINBOARD) { - find_mainboard(rec, addr); + find_mainboard(rec); break; } } @@ -241,7 +240,7 @@ int cb_parse_table(const char **vendor, const char **model) { uint8_t *table_area; - unsigned long addr, start; + unsigned long start; struct lb_header *lb_table; struct lb_record *rec, *last; @@ -284,7 +283,6 @@ return -1; } - addr = ((char *)lb_table) - ((char *)table_area) + start; msg_pinfo("coreboot table found at 0x%lx.\n", (unsigned long)lb_table - (unsigned long)table_area + start); rec = (struct lb_record *)(((char *)lb_table) + lb_table->header_bytes); @@ -293,7 +291,7 @@ lb_table->header_bytes, lb_table->header_checksum, lb_table->table_bytes, lb_table->table_checksum, lb_table->table_entries); - search_lb_records(rec, last, addr + lb_table->header_bytes); + search_lb_records(rec, last); *vendor = cb_vendor; *model = cb_model; return 0; diff --git a/ch341a_spi.c b/ch341a_spi.c index 83d5ccf..e5e2497 100644 --- a/ch341a_spi.c +++ b/ch341a_spi.c @@ -337,6 +337,8 @@ static int ch341a_spi_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { + (void)flash; + if (handle == NULL) return -1; @@ -401,6 +403,8 @@ static int ch341a_spi_shutdown(void *data) { + (void)data; + if (handle == NULL) return -1; diff --git a/chipset_enable.c b/chipset_enable.c index 4d624a3..122e5e5 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -41,6 +41,8 @@ static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) { + (void)name; + uint8_t tmp; /* @@ -56,6 +58,8 @@ static int enable_flash_rdc_r8610(struct pci_dev *dev, const char *name) { + (void)name; + uint8_t tmp; /* enable ROMCS for writes */ @@ -82,6 +86,8 @@ static int enable_flash_sis85c496(struct pci_dev *dev, const char *name) { + (void)name; + uint8_t tmp; tmp = pci_read_byte(dev, 0xd0); @@ -564,21 +570,25 @@ static int enable_flash_ich0(struct pci_dev *dev, const char *name) { + (void)name; return enable_flash_ich_fwh(dev, CHIPSET_ICH, 0x4e); } static int enable_flash_ich2345(struct pci_dev *dev, const char *name) { + (void)name; return enable_flash_ich_fwh(dev, CHIPSET_ICH2345, 0x4e); } static int enable_flash_ich6(struct pci_dev *dev, const char *name) { + (void)name; return enable_flash_ich_fwh(dev, CHIPSET_ICH6, 0xdc); } static int enable_flash_poulsbo(struct pci_dev *dev, const char *name) { + (void)name; return enable_flash_ich_fwh(dev, CHIPSET_POULSBO, 0xd8); } @@ -746,79 +756,93 @@ static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name) { + (void)name; return enable_flash_ich_spi(dev, CHIPSET_TUNNEL_CREEK, 0xd8); } static int enable_flash_s12x0(struct pci_dev *dev, const char *name) { + (void)name; return enable_flash_ich_spi(dev, CHIPSET_CENTERTON, 0xd8); } static int enable_flash_ich7(struct pci_dev *dev, const char *name) { + (void)name; return enable_flash_ich_spi(dev, CHIPSET_ICH7, 0xdc); } static int enable_flash_ich8(struct pci_dev *dev, const char *name) { + (void)name; return enable_flash_ich_spi(dev, CHIPSET_ICH8, 0xdc); } static int enable_flash_ich9(struct pci_dev *dev, const char *name) { + (void)name; return enable_flash_ich_spi(dev, CHIPSET_ICH9, 0xdc); } static int enable_flash_ich10(struct pci_dev *dev, const char *name) { + (void)name; return enable_flash_ich_spi(dev, CHIPSET_ICH10, 0xdc); } /* Ibex Peak aka. 5 series & 3400 series */ static int enable_flash_pch5(struct pci_dev *dev, const char *name) { + (void)name; return enable_flash_ich_spi(dev, CHIPSET_5_SERIES_IBEX_PEAK, 0xdc); } /* Cougar Point aka. 6 series & c200 series */ static int enable_flash_pch6(struct pci_dev *dev, const char *name) { + (void)name; return enable_flash_ich_spi(dev, CHIPSET_6_SERIES_COUGAR_POINT, 0xdc); } /* Panther Point aka. 7 series */ static int enable_flash_pch7(struct pci_dev *dev, const char *name) { + (void)name; return enable_flash_ich_spi(dev, CHIPSET_7_SERIES_PANTHER_POINT, 0xdc); } /* Lynx Point aka. 8 series */ static int enable_flash_pch8(struct pci_dev *dev, const char *name) { + (void)name; return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT, 0xdc); } /* Lynx Point LP aka. 8 series low-power */ static int enable_flash_pch8_lp(struct pci_dev *dev, const char *name) { + (void)name; return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT_LP, 0xdc); } /* Wellsburg (for Haswell-EP Xeons) */ static int enable_flash_pch8_wb(struct pci_dev *dev, const char *name) { + (void)name; return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_WELLSBURG, 0xdc); } /* Wildcat Point */ static int enable_flash_pch9(struct pci_dev *dev, const char *name) { + (void)name; return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc); } /* Wildcat Point LP */ static int enable_flash_pch9_lp(struct pci_dev *dev, const char *name) { + (void)name; return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT_LP, 0xdc); } @@ -831,6 +855,8 @@ static int enable_flash_pch100_or_c620(struct pci_dev *const dev, const char *const name, const enum ich_chipset pch_generation) { + (void)name; + int ret = ERROR_FATAL; /* @@ -908,6 +934,8 @@ */ static int enable_flash_silvermont(struct pci_dev *dev, const char *name) { + (void)name; + enum ich_chipset ich_generation = CHIPSET_BAYTRAIL; /* Get physical address of Root Complex Register Block */ @@ -948,6 +976,8 @@ static int via_no_byte_merge(struct pci_dev *dev, const char *name) { + (void)name; + uint8_t val; val = pci_read_byte(dev, 0x71); @@ -1052,11 +1082,14 @@ static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) { + (void)name; return via_init_spi(pci_read_long(dev, 0xbc) << 8); } static int enable_flash_cs5530(struct pci_dev *dev, const char *name) { + (void)name; + uint8_t reg8; #define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */ @@ -1121,6 +1154,9 @@ */ static int enable_flash_cs5536(struct pci_dev *dev, const char *name) { + (void)dev; + (void)name; + #define MSR_RCONF_DEFAULT 0x1808 #define MSR_NORF_CTL 0x51400018 @@ -1231,6 +1267,8 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name) { + (void)name; + uint32_t prot; uint8_t reg; int ret; @@ -1406,6 +1444,9 @@ static int enable_flash_osb4(struct pci_dev *dev, const char *name) { + (void)dev; + (void)name; + uint8_t tmp; internal_buses_supported = BUS_PARALLEL; @@ -1424,6 +1465,8 @@ /* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */ static int enable_flash_sb400(struct pci_dev *dev, const char *name) { + (void)name; + uint8_t tmp; struct pci_dev *smbusdev; @@ -1533,6 +1576,8 @@ static int enable_flash_ht1000(struct pci_dev *dev, const char *name) { + (void)name; + uint8_t val; /* Set the 4MB enable bit. */ @@ -1556,6 +1601,9 @@ */ static int get_flashbase_sc520(struct pci_dev *dev, const char *name) { + (void)dev; + (void)name; + int i, bootcs_found = 0; uint32_t parx = 0; void *mmcr; diff --git a/dediprog.c b/dediprog.c index 9d0dd2e..ee766ae 100644 --- a/dediprog.c +++ b/dediprog.c @@ -402,6 +402,8 @@ */ static int dediprog_spi_bulk_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) { + (void)flash; + int err = 1; /* chunksize must be 512, other sizes will NOT work at all. */ @@ -550,6 +552,8 @@ static int dediprog_spi_bulk_write(struct flashctx *flash, const uint8_t *buf, unsigned int chunksize, unsigned int start, unsigned int len, uint8_t dedi_spi_cmd) { + (void)flash; + /* USB transfer size must be 512, other sizes will NOT work at all. * chunksize is the real data size per USB bulk transfer. The remaining * space in a USB bulk transfer must be filled with 0xff padding. @@ -944,6 +948,8 @@ static int dediprog_shutdown(void *data) { + (void)data; + dediprog_devicetype = DEV_UNKNOWN; /* URB 28. Command Set SPI Voltage to 0. */ diff --git a/developerbox_spi.c b/developerbox_spi.c index 4ad966e..93747cb 100644 --- a/developerbox_spi.c +++ b/developerbox_spi.c @@ -131,6 +131,8 @@ static int developerbox_spi_shutdown(void *data) { + (void)data; + libusb_close(cp210x_handle); libusb_exit(usb_ctx); diff --git a/digilent_spi.c b/digilent_spi.c index d42c90f..f80fe42 100644 --- a/digilent_spi.c +++ b/digilent_spi.c @@ -260,6 +260,8 @@ static int digilent_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { + (void)flash; + int ret; int len = writecnt + readcnt; int tx_len = 0; @@ -327,6 +329,8 @@ static int digilent_spi_shutdown(void *data) { + (void)data; + if (reset_board) gpio_set_dir(0); diff --git a/dmi.c b/dmi.c index 5bd0e16..ad46704 100644 --- a/dmi.c +++ b/dmi.c @@ -377,6 +377,8 @@ static int dmi_shutdown(void *data) { + (void)data; + unsigned int i; for (i = 0; i < ARRAY_SIZE(dmi_strings); i++) { free(dmi_strings[i].value); diff --git a/drkaiser.c b/drkaiser.c index ac49df3..734466d 100644 --- a/drkaiser.c +++ b/drkaiser.c @@ -85,11 +85,13 @@ static void drkaiser_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) { + (void)flash; pci_mmio_writeb(val, drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK)); } static uint8_t drkaiser_chip_readb(const struct flashctx *flash, const chipaddr addr) { + (void)flash; return pci_mmio_readb(drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK)); } diff --git a/dummyflasher.c b/dummyflasher.c index fdb632d..75897eb 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -132,6 +132,8 @@ static int dummy_shutdown(void *data) { + (void)data; + msg_pspew("%s\n", __func__); #if EMULATE_CHIP if (emu_chip != EMULATE_NONE) { @@ -414,21 +416,26 @@ static void dummy_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) { + (void)flash; msg_pspew("%s: addr=0x%" PRIxPTR ", val=0x%02x\n", __func__, addr, val); } static void dummy_chip_writew(const struct flashctx *flash, uint16_t val, chipaddr addr) { + (void)flash; msg_pspew("%s: addr=0x%" PRIxPTR ", val=0x%04x\n", __func__, addr, val); } static void dummy_chip_writel(const struct flashctx *flash, uint32_t val, chipaddr addr) { + (void)flash; msg_pspew("%s: addr=0x%" PRIxPTR ", val=0x%08x\n", __func__, addr, val); } static void dummy_chip_writen(const struct flashctx *flash, const uint8_t *buf, chipaddr addr, size_t len) { + (void)flash; + size_t i; msg_pspew("%s: addr=0x%" PRIxPTR ", len=0x%zx, writing data (hex):", __func__, addr, len); for (i = 0; i < len; i++) { @@ -440,24 +447,28 @@ static uint8_t dummy_chip_readb(const struct flashctx *flash, const chipaddr addr) { + (void)flash; msg_pspew("%s: addr=0x%" PRIxPTR ", returning 0xff\n", __func__, addr); return 0xff; } static uint16_t dummy_chip_readw(const struct flashctx *flash, const chipaddr addr) { + (void)flash; msg_pspew("%s: addr=0x%" PRIxPTR ", returning 0xffff\n", __func__, addr); return 0xffff; } static uint32_t dummy_chip_readl(const struct flashctx *flash, const chipaddr addr) { + (void)flash; msg_pspew("%s: addr=0x%" PRIxPTR ", returning 0xffffffff\n", __func__, addr); return 0xffffffff; } static void dummy_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len) { + (void)flash; msg_pspew("%s: addr=0x%" PRIxPTR ", len=0x%zx, returning array of 0xff\n", __func__, addr, len); memset(buf, 0xff, len); return; @@ -790,6 +801,8 @@ const unsigned char *writearr, unsigned char *readarr) { + (void)flash; + unsigned int i; msg_pspew("%s:", __func__); diff --git a/ft2232_spi.c b/ft2232_spi.c index 95584aa..9ca894c 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -449,6 +449,8 @@ const unsigned char *writearr, unsigned char *readarr) { + (void)flash; + struct ftdi_context *ftdic = &ftdic_context; static unsigned char *buf = NULL; /* failed is special. We use bitwise ops, but it is essentially bool. */ diff --git a/gfxnvidia.c b/gfxnvidia.c index c6d752e..c683b4f 100644 --- a/gfxnvidia.c +++ b/gfxnvidia.c @@ -111,11 +111,15 @@ static void gfxnvidia_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) { + (void)flash; + pci_mmio_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); } static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash, const chipaddr addr) { + (void)flash; + return pci_mmio_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); } diff --git a/hwaccess.c b/hwaccess.c index acb99f8..2968af2 100644 --- a/hwaccess.c +++ b/hwaccess.c @@ -91,6 +91,8 @@ #if IS_X86 && !(defined(__DJGPP__) || defined(__LIBPAYLOAD__)) static int release_io_perms(void *p) { + (void)p; + #if defined (__sun) sysi86(SI86V86, V86SC_IOPL, 0); #elif USE_DEV_IO diff --git a/internal.c b/internal.c index 1d6cff6..c1e85e6 100644 --- a/internal.c +++ b/internal.c @@ -334,42 +334,48 @@ static void internal_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) { + (void)flash; mmio_writeb(val, (void *) addr); } static void internal_chip_writew(const struct flashctx *flash, uint16_t val, chipaddr addr) { + (void)flash; mmio_writew(val, (void *) addr); } static void internal_chip_writel(const struct flashctx *flash, uint32_t val, chipaddr addr) { + (void)flash; mmio_writel(val, (void *) addr); } static uint8_t internal_chip_readb(const struct flashctx *flash, const chipaddr addr) { + (void)flash; return mmio_readb((void *) addr); } static uint16_t internal_chip_readw(const struct flashctx *flash, const chipaddr addr) { + (void)flash; return mmio_readw((void *) addr); } static uint32_t internal_chip_readl(const struct flashctx *flash, const chipaddr addr) { + (void)flash; return mmio_readl((void *) addr); } static void internal_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len) { + (void)flash; mmio_readn((void *)addr, buf, len); - return; } diff --git a/it8212.c b/it8212.c index 70b1d9d..6518548 100644 --- a/it8212.c +++ b/it8212.c @@ -73,10 +73,12 @@ static void it8212_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) { + (void)flash; pci_mmio_writeb(val, it8212_bar + (addr & IT8212_MEMMAP_MASK)); } static uint8_t it8212_chip_readb(const struct flashctx *flash, const chipaddr addr) { + (void)flash; return pci_mmio_readb(it8212_bar + (addr & IT8212_MEMMAP_MASK)); } diff --git a/it85spi.c b/it85spi.c index 5a6502b..afa5cbd 100644 --- a/it85spi.c +++ b/it85spi.c @@ -217,6 +217,7 @@ static int it85xx_shutdown(void *data) { + (void)data; msg_pdbg("%s():%d\n", __func__, __LINE__); it85xx_exit_scratch_rom(); @@ -328,6 +329,8 @@ const unsigned char *writearr, unsigned char *readarr) { + (void)flash; + unsigned int i; it85xx_enter_scratch_rom(); diff --git a/it87spi.c b/it87spi.c index 78c2b68..e07e8b9 100644 --- a/it87spi.c +++ b/it87spi.c @@ -281,6 +281,8 @@ const unsigned char *writearr, unsigned char *readarr) { + (void)flash; + uint8_t busy, writeenc; do { diff --git a/jedec.c b/jedec.c index ef48206..f03e7fa 100644 --- a/jedec.c +++ b/jedec.c @@ -281,8 +281,7 @@ return 1; } -static int erase_sector_jedec_common(struct flashctx *flash, unsigned int page, - unsigned int pagesize, unsigned int mask) +static int erase_sector_jedec_common(struct flashctx *flash, unsigned int page, unsigned int mask) { chipaddr bios = flash->virtual_memory; bool shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED); @@ -313,8 +312,7 @@ return 0; } -static int erase_block_jedec_common(struct flashctx *flash, unsigned int block, - unsigned int blocksize, unsigned int mask) +static int erase_block_jedec_common(struct flashctx *flash, unsigned int block, unsigned int mask) { chipaddr bios = flash->virtual_memory; bool shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED); @@ -537,19 +535,23 @@ int erase_sector_jedec(struct flashctx *flash, unsigned int page, unsigned int size) { + (void)size; + unsigned int mask; mask = getaddrmask(flash->chip); - return erase_sector_jedec_common(flash, page, size, mask); + return erase_sector_jedec_common(flash, page, mask); } int erase_block_jedec(struct flashctx *flash, unsigned int page, unsigned int size) { + (void)size; + unsigned int mask; mask = getaddrmask(flash->chip); - return erase_block_jedec_common(flash, page, size, mask); + return erase_block_jedec_common(flash, page, mask); } int erase_chip_jedec(struct flashctx *flash) diff --git a/libflashrom.c b/libflashrom.c index f90a22c..de71899 100644 --- a/libflashrom.c +++ b/libflashrom.c @@ -130,6 +130,8 @@ int flashrom_programmer_init(struct flashrom_programmer **const flashprog, const char *const prog_name, const char *const prog_param) { + (void)flashprog; /* until we make use of it */ + unsigned prog; for (prog = 0; prog < PROGRAMMER_INVALID; prog++) { @@ -152,6 +154,7 @@ */ int flashrom_programmer_shutdown(struct flashrom_programmer *const flashprog) { + (void)flashprog; /* until we make use of it */ return programmer_shutdown(); } @@ -188,6 +191,8 @@ const struct flashrom_programmer *const flashprog, const char *const chip_name) { + (void)flashprog; /* until we make use of it */ + int i, ret = 2; struct flashrom_flashctx second_flashctx = { 0, }; @@ -383,8 +388,7 @@ #endif } -static int flashrom_layout_parse_fmap(struct flashrom_layout **layout, - struct flashctx *const flashctx, const struct fmap *const fmap) +static int flashrom_layout_parse_fmap(struct flashrom_layout **layout, const struct fmap *const fmap) { int i; struct flashrom_layout *l = get_global_layout(); @@ -445,7 +449,7 @@ } msg_gdbg("Adding fmap layout to global layout.\n"); - if (flashrom_layout_parse_fmap(layout, flashctx, fmap)) { + if (flashrom_layout_parse_fmap(layout, fmap)) { msg_gerr("Failed to add fmap regions to layout.\n"); ret = 1; } @@ -472,6 +476,8 @@ int flashrom_layout_read_fmap_from_buffer(struct flashrom_layout **const layout, struct flashctx *const flashctx, const uint8_t *const buf, size_t size) { + (void)flashctx; + #ifndef __FLASHROM_LITTLE_ENDIAN__ return 3; #else @@ -488,7 +494,7 @@ } msg_gdbg("Adding fmap layout to global layout.\n"); - if (flashrom_layout_parse_fmap(layout, flashctx, fmap)) { + if (flashrom_layout_parse_fmap(layout, fmap)) { msg_gerr("Failed to add fmap regions to layout.\n"); goto _free_ret; } diff --git a/linux_mtd.c b/linux_mtd.c index ae8bef2..0ee8e0f 100644 --- a/linux_mtd.c +++ b/linux_mtd.c @@ -259,6 +259,8 @@ static int linux_mtd_erase(struct flashctx *flash, unsigned int start, unsigned int len) { + (void)flash; + uint32_t u; if (mtd_no_erase) { @@ -349,6 +351,8 @@ static int linux_mtd_shutdown(void *data) { + (void)data; + if (dev_fp != NULL) { fclose(dev_fp); dev_fp = NULL; diff --git a/linux_spi.c b/linux_spi.c index 711ab4a..b308c99 100644 --- a/linux_spi.c +++ b/linux_spi.c @@ -173,6 +173,8 @@ static int linux_spi_shutdown(void *data) { + (void)data; + if (fd != -1) { close(fd); fd = -1; @@ -185,6 +187,8 @@ const unsigned char *txbuf, unsigned char *rxbuf) { + (void)flash; + int iocontrol_code; struct spi_ioc_transfer msg[2] = { { diff --git a/nic3com.c b/nic3com.c index b7b967a..cd6ffed 100644 --- a/nic3com.c +++ b/nic3com.c @@ -70,6 +70,8 @@ static int nic3com_shutdown(void *data) { + (void)data; + /* 3COM 3C90xB cards need a special fixup. */ if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005 || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) { @@ -128,6 +130,8 @@ static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) { + (void)flash; + OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); OUTB(val, io_base_addr + BIOS_ROM_DATA); } @@ -135,6 +139,8 @@ static uint8_t nic3com_chip_readb(const struct flashctx *flash, const chipaddr addr) { + (void)flash; + OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); return INB(io_base_addr + BIOS_ROM_DATA); } diff --git a/nicintel.c b/nicintel.c index a4424e7..0ea961b 100644 --- a/nicintel.c +++ b/nicintel.c @@ -107,11 +107,13 @@ static void nicintel_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) { + (void)flash; pci_mmio_writeb(val, nicintel_bar + (addr & NICINTEL_MEMMAP_MASK)); } static uint8_t nicintel_chip_readb(const struct flashctx *flash, const chipaddr addr) { + (void)flash; return pci_mmio_readb(nicintel_bar + (addr & NICINTEL_MEMMAP_MASK)); } diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c index 4e01fcb..536cf18 100644 --- a/nicintel_eeprom.c +++ b/nicintel_eeprom.c @@ -174,6 +174,8 @@ static int nicintel_ee_read(struct flashctx *flash, uint8_t *buf, unsigned int addr, unsigned int len) { + (void)flash; + uint16_t data; /* The NIC interface always reads 16 b words so we need to convert the address and handle odd address @@ -222,6 +224,8 @@ static int nicintel_ee_write_i210(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) { + (void)flash; + done_i20_write = true; if (addr & 1) { @@ -356,6 +360,8 @@ static int nicintel_ee_write_82580(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) { + (void)flash; + if (nicintel_ee_req()) return -1; @@ -414,6 +420,8 @@ static int nicintel_ee_shutdown_i210(void *arg) { + (void)arg; + if (!done_i20_write) return 0; diff --git a/nicintel_spi.c b/nicintel_spi.c index f31a2f9..6c4ea32 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -180,6 +180,8 @@ static int nicintel_spi_shutdown(void *data) { + (void)data; + uint32_t tmp; /* Disable writes manually. See the comment about EECD in nicintel_spi_init() for details. */ diff --git a/nicrealtek.c b/nicrealtek.c index 5454b63..0b5f4e8 100644 --- a/nicrealtek.c +++ b/nicrealtek.c @@ -50,6 +50,7 @@ static int nicrealtek_shutdown(void *data) { + (void)data; /* FIXME: We forgot to disable software access again. */ return 0; } @@ -93,6 +94,8 @@ static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) { + (void)flash; + /* Output addr and data, set WE to 0, set OE to 1, set CS to 0, * enable software access. */ @@ -107,6 +110,8 @@ static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr) { + (void)flash; + uint8_t val; /* FIXME: Can we skip reading the old data and simply use 0? */ diff --git a/pcidev.c b/pcidev.c index f5ad819..34a50c3 100644 --- a/pcidev.c +++ b/pcidev.c @@ -150,6 +150,8 @@ static int pcidev_shutdown(void *data) { + (void)data; + if (pacc == NULL) { msg_perr("%s: Tried to cleanup an invalid PCI context!\n" "Please report a bug at flashrom(a)flashrom.org\n", __func__); diff --git a/pickit2_spi.c b/pickit2_spi.c index fe638a1..cb103cc 100644 --- a/pickit2_spi.c +++ b/pickit2_spi.c @@ -214,6 +214,7 @@ static int pickit2_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { + (void)flash; /* Maximum number of bytes per transaction (including command overhead) is 64. Lets play it safe * and always assume the worst case scenario of 20 bytes command overhead. @@ -362,6 +363,8 @@ static int pickit2_shutdown(void *data) { + (void)data; + /* Set all pins to float and turn voltages off */ uint8_t command[CMD_LENGTH] = { CMD_EXEC_SCRIPT, diff --git a/pony_spi.c b/pony_spi.c index 39a468b..b6f72f7 100644 --- a/pony_spi.c +++ b/pony_spi.c @@ -101,6 +101,8 @@ static int pony_spi_shutdown(void *data) { + (void)data; + /* Shut down serial port communication */ int ret = serialport_shutdown(NULL); if (ret) diff --git a/programmer.c b/programmer.c index f4b4384..891dcc7 100644 --- a/programmer.c +++ b/programmer.c @@ -26,6 +26,9 @@ /* Fallback map() for programmers which don't need special handling */ void *fallback_map(const char *descr, uintptr_t phys_addr, size_t len) { + (void)descr; + (void)phys_addr; + (void)len; /* FIXME: Should return phys_addr. */ return NULL; } @@ -33,11 +36,16 @@ /* No-op/fallback unmap() for programmers which don't need special handling */ void fallback_unmap(void *virt_addr, size_t len) { + (void)virt_addr; + (void)len; } /* No-op chip_writeb() for parallel style drivers not supporting writes */ void noop_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) { + (void)flash; + (void)val; + (void)addr; } /* Little-endian fallback for drivers not supporting 16 bit accesses */ diff --git a/rayer_spi.c b/rayer_spi.c index 4f8e1d6..2c52ab2 100644 --- a/rayer_spi.c +++ b/rayer_spi.c @@ -238,27 +238,39 @@ return 0; } -static void byteblaster_preinit(const void *data){ +static void byteblaster_preinit(const void *data) +{ + (void)data; + msg_pdbg("byteblaster_preinit\n"); /* Assert #EN signal. */ OUTB(2, lpt_iobase + 2 ); } -static int byteblaster_shutdown(void *data){ +static int byteblaster_shutdown(void *data) +{ + (void)data; + msg_pdbg("byteblaster_shutdown\n"); /* De-Assert #EN signal. */ OUTB(0, lpt_iobase + 2 ); return 0; } -static void stk200_preinit(const void *data) { +static void stk200_preinit(const void *data) +{ + (void)data; + msg_pdbg("stk200_init\n"); /* Assert #EN signals, set LED signal. */ lpt_outbyte = (1 << 6) ; OUTB(lpt_outbyte, lpt_iobase); } -static int stk200_shutdown(void *data) { +static int stk200_shutdown(void *data) +{ + (void)data; + msg_pdbg("stk200_shutdown\n"); /* Assert #EN signals, clear LED signal. */ lpt_outbyte = (1 << 2) | (1 << 3); @@ -266,14 +278,20 @@ return 0; } -static void dlc5_preinit(const void *data) { +static void dlc5_preinit(const void *data) +{ + (void)data; + msg_pdbg("dlc5_preinit\n"); /* Assert pin 6 to receive MISO. */ lpt_outbyte |= (1<<4); OUTB(lpt_outbyte, lpt_iobase); } -static int dlc5_shutdown(void *data) { +static int dlc5_shutdown(void *data) +{ + (void)data; + msg_pdbg("dlc5_shutdown\n"); /* De-assert pin 6 to force MISO low. */ lpt_outbyte &= ~(1<<4); diff --git a/satamv.c b/satamv.c index 1d3734a..3d10375 100644 --- a/satamv.c +++ b/satamv.c @@ -178,6 +178,7 @@ static void satamv_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) { + (void)flash; satamv_indirect_chip_writeb(val, addr); } @@ -185,6 +186,7 @@ static uint8_t satamv_chip_readb(const struct flashctx *flash, const chipaddr addr) { + (void)flash; return satamv_indirect_chip_readb(addr); } diff --git a/satasii.c b/satasii.c index 8a0938d..dba63cb 100644 --- a/satasii.c +++ b/satasii.c @@ -107,6 +107,8 @@ static void satasii_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) { + (void)flash; + uint32_t data_reg; uint32_t ctrl_reg = satasii_wait_done(); @@ -123,6 +125,8 @@ static uint8_t satasii_chip_readb(const struct flashctx *flash, const chipaddr addr) { + (void)flash; + uint32_t ctrl_reg = satasii_wait_done(); /* Mask out unused/reserved bits, set reads and start transaction. */ diff --git a/sb600spi.c b/sb600spi.c index 63a72f1..0c671ab 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -363,7 +363,7 @@ { "800 kHz", 0x07 }, }; -static int set_speed(struct pci_dev *dev, const struct spispeed *spispeed) +static int set_speed(const struct spispeed *spispeed) { bool success = false; uint8_t speed = spispeed->speed; @@ -386,7 +386,7 @@ return 0; } -static int set_mode(struct pci_dev *dev, uint8_t read_mode) +static int set_mode(uint8_t read_mode) { uint32_t tmp = mmio_readl(sb600_spibar + 0x00); tmp &= ~(0x6 << 28 | 0x1 << 18); /* Clear mode bits */ @@ -397,7 +397,7 @@ return 0; } -static int handle_speed(struct pci_dev *dev) +static int handle_speed(void) { uint32_t tmp; uint8_t spispeed_idx = 3; /* Default to 16.5 MHz */ @@ -447,7 +447,7 @@ msg_pdbg("SpiReadMode=%s (%i)\n", spireadmodes[read_mode], read_mode); if (read_mode != 6) { read_mode = 6; /* Default to "Normal (up to 66 MHz)" */ - if (set_mode(dev, read_mode) != 0) { + if (set_mode(read_mode) != 0) { msg_perr("Setting read mode to \"%s\" failed.\n", spireadmodes[read_mode]); return 1; } @@ -486,7 +486,7 @@ tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; msg_pdbg("NormSpeed is %s\n", spispeeds[tmp].name); } - return set_speed(dev, &spispeeds[spispeed_idx]); + return set_speed(&spispeeds[spispeed_idx]); } static int handle_imc(struct pci_dev *dev) @@ -698,7 +698,7 @@ return 0; } - if (handle_speed(dev) != 0) + if (handle_speed() != 0) return ERROR_FATAL; if (handle_imc(dev) != 0) diff --git a/serial.c b/serial.c index 3a99dbf..e9cfaf2 100644 --- a/serial.c +++ b/serial.c @@ -372,6 +372,7 @@ int serialport_shutdown(void *data) { + (void)data; #if IS_WINDOWS CloseHandle(sp_fd); #else diff --git a/serprog.c b/serprog.c index bef514a..b4b31e4 100644 --- a/serprog.c +++ b/serprog.c @@ -755,6 +755,8 @@ static int serprog_shutdown(void *data) { + (void)data; + if ((sp_opbuf_usage) || (sp_max_write_n && sp_write_n_bytes)) if (sp_execute_opbuf() != 0) msg_pwarn("Could not flush command buffer.\n"); @@ -786,6 +788,8 @@ static void serprog_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) { + (void)flash; + msg_pspew("%s\n", __func__); if (sp_max_write_n) { if ((sp_prev_was_write) @@ -818,6 +822,8 @@ static uint8_t serprog_chip_readb(const struct flashctx *flash, const chipaddr addr) { + (void)flash; + unsigned char c; unsigned char buf[3]; /* Will stream the read operation - eg. add it to the stream buffer, * @@ -863,6 +869,8 @@ static void serprog_chip_readn(const struct flashctx *flash, uint8_t * buf, const chipaddr addr, size_t len) { + (void)flash; + size_t lenm = len; chipaddr addrm = addr; while ((sp_max_read_n != 0) && (lenm > sp_max_read_n)) { @@ -900,6 +908,8 @@ const unsigned char *writearr, unsigned char *readarr) { + (void)flash; + unsigned char *parmbuf; int ret; msg_pspew("%s, writecnt=%i, readcnt=%i\n", __func__, writecnt, readcnt); diff --git a/spi25.c b/spi25.c index 8b6c462..77effeb 100644 --- a/spi25.c +++ b/spi25.c @@ -476,6 +476,7 @@ int spi_block_erase_52(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { + (void)blocklen; /* This usually takes 100-4000ms, so wait in 100ms steps. */ return spi_write_cmd(flash, 0x52, false, addr, NULL, 0, 100 * 1000); } @@ -485,6 +486,7 @@ */ int spi_block_erase_c4(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { + (void)blocklen; /* This usually takes 240-480s, so wait in 500ms steps. */ return spi_write_cmd(flash, 0xc4, false, addr, NULL, 0, 500 * 1000); } @@ -497,6 +499,7 @@ int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { + (void)blocklen; /* This usually takes 100-4000ms, so wait in 100ms steps. */ return spi_write_cmd(flash, 0xd8, false, addr, NULL, 0, 100 * 1000); } @@ -507,6 +510,7 @@ int spi_block_erase_d7(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { + (void)blocklen; /* This usually takes 100-4000ms, so wait in 100ms steps. */ return spi_write_cmd(flash, 0xd7, false, addr, NULL, 0, 100 * 1000); } @@ -514,6 +518,7 @@ /* Page erase (usually 256B blocks) */ int spi_block_erase_db(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { + (void)blocklen; /* This takes up to 20ms usually (on worn out devices up to the 0.5s range), so wait in 1ms steps. */ return spi_write_cmd(flash, 0xdb, false, addr, NULL, 0, 1 * 1000); @@ -523,18 +528,21 @@ int spi_block_erase_20(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { + (void)blocklen; /* This usually takes 15-800ms, so wait in 10ms steps. */ return spi_write_cmd(flash, 0x20, false, addr, NULL, 0, 10 * 1000); } int spi_block_erase_50(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { + (void)blocklen; /* This usually takes 10ms, so wait in 1ms steps. */ return spi_write_cmd(flash, 0x50, false, addr, NULL, 0, 1 * 1000); } int spi_block_erase_81(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { + (void)blocklen; /* This usually takes 8ms, so wait in 1ms steps. */ return spi_write_cmd(flash, 0x81, false, addr, NULL, 0, 1 * 1000); } @@ -574,6 +582,7 @@ /* Erase 4 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) */ int spi_block_erase_21(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { + (void)blocklen; /* This usually takes 15-800ms, so wait in 10ms steps. */ return spi_write_cmd(flash, 0x21, true, addr, NULL, 0, 10 * 1000); } @@ -581,6 +590,7 @@ /* Erase 32 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) */ int spi_block_erase_5c(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { + (void)blocklen; /* This usually takes 100-4000ms, so wait in 100ms steps. */ return spi_write_cmd(flash, 0x5c, true, addr, NULL, 0, 100 * 1000); } @@ -588,6 +598,7 @@ /* Erase 64 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) */ int spi_block_erase_dc(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { + (void)blocklen; /* This usually takes 100-4000ms, so wait in 100ms steps. */ return spi_write_cmd(flash, 0xdc, true, addr, NULL, 0, 100 * 1000); } diff --git a/sst28sf040.c b/sst28sf040.c index 3da25f1..22c33a7 100644 --- a/sst28sf040.c +++ b/sst28sf040.c @@ -59,6 +59,8 @@ int erase_sector_28sf040(struct flashctx *flash, unsigned int address, unsigned int sector_size) { + (void)sector_size; + chipaddr bios = flash->virtual_memory; /* This command sequence is very similar to erase_block_82802ab. */ diff --git a/sst49lfxxxc.c b/sst49lfxxxc.c index a69ab75..2749eff 100644 --- a/sst49lfxxxc.c +++ b/sst49lfxxxc.c @@ -22,6 +22,8 @@ int erase_sector_49lfxxxc(struct flashctx *flash, unsigned int address, unsigned int sector_size) { + (void)sector_size; + uint8_t status; chipaddr bios = flash->virtual_memory; diff --git a/udelay.c b/udelay.c index c3f14f3..267755f 100644 --- a/udelay.c +++ b/udelay.c @@ -70,7 +70,7 @@ } #else -static inline void clock_usec_delay(int usecs) {} +static inline void clock_usec_delay(int usecs) { (void)usecs; } static inline int clock_check_res(void) { return 0; } #endif /* HAVE_CLOCK_GETTIME == 1 */ diff --git a/usbblaster_spi.c b/usbblaster_spi.c index e5f66ce..6a4cd5e 100644 --- a/usbblaster_spi.c +++ b/usbblaster_spi.c @@ -182,6 +182,8 @@ static int usbblaster_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { + (void)flash; + uint8_t cmd; int ret = 0; diff --git a/usbdev.c b/usbdev.c index d793b65..13f3b02 100644 --- a/usbdev.c +++ b/usbdev.c @@ -116,6 +116,8 @@ static bool filter_by_number(struct libusb_device_descriptor *desc, struct libusb_device_handle *handle, void *ctx) { + (void)desc; + /* This filter never triggers once it has allowed the device to be opened */ if (handle != NULL) return false; diff --git a/w39.c b/w39.c index f58c495..a7d48d6 100644 --- a/w39.c +++ b/w39.c @@ -224,6 +224,8 @@ int printlock_w39v080fa_dual(struct flashctx *flash) { + (void)flash; + msg_cinfo("Block locking for W39V080FA in dual mode is " "undocumented.\n"); /* Better safe than sorry. */ diff --git a/wbsio_spi.c b/wbsio_spi.c index aed80b5..f107653 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -116,6 +116,8 @@ const unsigned char *writearr, unsigned char *readarr) { + (void)flash; + unsigned int i; uint8_t mode = 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/30410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If831398c91e9f49bd5216a03ed4caaa2a7ab02bd Gerrit-Change-Number: 30410 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...flashrom[master]: Makefile: Enable -Wextra
by Nico Huber (Code Review) Dec. 23, 2018

Dec. 23, 2018

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/30411 Change subject: Makefile: Enable -Wextra ...................................................................... Makefile: Enable -Wextra Change-Id: Id2ece264c2d483e34019985dd3a7631c4889abe6 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/11/30411/1 diff --git a/Makefile b/Makefile index 1ff578c..cf6901f 100644 --- a/Makefile +++ b/Makefile @@ -30,7 +30,7 @@ DIFF = diff PREFIX ?= /usr/local MANDIR ?= $(PREFIX)/share/man -CFLAGS ?= -Os -Wall -Wshadow +CFLAGS ?= -Os -Wall -Wextra -Wshadow EXPORTDIR ?= . RANLIB ?= ranlib PKG_CONFIG ?= pkg-config -- To view, visit https://review.coreboot.org/c/flashrom/+/30411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id2ece264c2d483e34019985dd3a7631c4889abe6 Gerrit-Change-Number: 30411 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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