[coreboot - Bug #478] (New) X200 booting takes a long time
Issue #478 has been reported by Robert Gruber. ---------------------------------------- Bug #478: X200 booting takes a long time https://ticket.coreboot.org/issues/478 * Author: Robert Gruber * Status: New * Priority: Normal * Target version: none * Start date: 2023-04-04 * Affected versions: 4.15, 4.16, 4.17, 4.18, 4.19, master * Needs backport to: master ---------------------------------------- dmesg: TSC found unstable after boot, most likely due to broken BIOS. Use 'tsc=unstable'. After a period of time the boot finished by auto-switching to hpet. Setting kernel parameter directly to clocksource=hpet the system is booting fast. Why is the faster clocksource tsc not working and tells coreboot is broken ? -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account
Issue #478 has been updated by Paul Menzel. Subject changed from X200 booting takes a long time to X200 booting Linux takes a long time with TSC (`clocksource=hpet` works) Related links updated ---------------------------------------- Bug #478: X200 booting Linux takes a long time with TSC (`clocksource=hpet` works) https://ticket.coreboot.org/issues/478#change-1460 * Author: Robert Gruber * Status: New * Priority: Normal * Target version: none * Start date: 2023-04-04 * Affected versions: 4.15, 4.16, 4.17, 4.18, 4.19, master * Needs backport to: master * Related links: Thank you for reporting this issue. Does booting with `'tsc=unstable` also work? Please the coreboot log messages for example by running `cbmem -1`. ---------------------------------------- dmesg: TSC found unstable after boot, most likely due to broken BIOS. Use 'tsc=unstable'. After a period of time the boot finished by auto-switching to hpet. Setting kernel parameter directly to clocksource=hpet the system is booting fast. Why is the faster clocksource tsc not working and tells coreboot is broken ? -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account
Issue #478 has been updated by Robert Gruber. File cbmem.log added Robert Gruber wrote:
dmesg: TSC found unstable after boot, most likely due to broken BIOS. Use 'tsc=unstable'. After a period of time the boot finished by auto-switching to hpet. Setting kernel parameter directly to clocksource=hpet the system is booting fast.
Why is the faster clocksource tsc not working and tells coreboot is broken ?
Thank you for editing my description! tsc=unstable also works. ---------------------------------------- Bug #478: X200 booting Linux takes a long time with TSC (`clocksource=hpet` works) https://ticket.coreboot.org/issues/478#change-1461 * Author: Robert Gruber * Status: New * Priority: Normal * Target version: none * Start date: 2023-04-04 * Affected versions: 4.15, 4.16, 4.17, 4.18, 4.19, master * Needs backport to: master * Related links: Thank you for reporting this issue. Does booting with `'tsc=unstable` also work? Please the coreboot log messages for example by running `cbmem -1`. ---------------------------------------- dmesg: TSC found unstable after boot, most likely due to broken BIOS. Use 'tsc=unstable'. After a period of time the boot finished by auto-switching to hpet. Setting kernel parameter directly to clocksource=hpet the system is booting fast. Why is the faster clocksource tsc not working and tells coreboot is broken ? ---Files-------------------------------- cbmem.log (38.6 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account
Issue #478 has been updated by Robert Gruber. Target version changed from none to master ---------------------------------------- Bug #478: X200 booting Linux takes a long time with TSC (`clocksource=hpet` works) https://ticket.coreboot.org/issues/478#change-1462 * Author: Robert Gruber * Status: New * Priority: Normal * Target version: master * Start date: 2023-04-04 * Affected versions: 4.15, 4.16, 4.17, 4.18, 4.19, master * Needs backport to: master * Related links: Thank you for reporting this issue. Does booting with `'tsc=unstable` also work? Please the coreboot log messages for example by running `cbmem -1`. ---------------------------------------- dmesg: TSC found unstable after boot, most likely due to broken BIOS. Use 'tsc=unstable'. After a period of time the boot finished by auto-switching to hpet. Setting kernel parameter directly to clocksource=hpet the system is booting fast. Why is the faster clocksource tsc not working and tells coreboot is broken ? ---Files-------------------------------- cbmem.log (38.6 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account
Issue #478 has been updated by Bill XIE. Robert Gruber wrote:
dmesg: TSC found unstable after boot, most likely due to broken BIOS. Use 'tsc=unstable'. After a period of time the boot finished by auto-switching to hpet. Setting kernel parameter directly to clocksource=hpet the system is booting fast.
Why is the faster clocksource tsc not working and tells coreboot is broken ?
As stated in https://www.chromium.org/chromium-os/how-tos-and-troubleshooting/tsc-resynch... , there are 4 types of TSC, while a core 2 cpu only has Constant TSC, which may change on C state transitions. Newer cpu like Ivy Bridge have nonstop_tsc and tsc_deadline. They can keep using tsc as clock source. Does this issue remain on an x200 running vendor firmware? ---------------------------------------- Bug #478: X200 booting Linux takes a long time with TSC (`clocksource=hpet` works) https://ticket.coreboot.org/issues/478#change-1467 * Author: Robert Gruber * Status: New * Priority: Normal * Target version: master * Start date: 2023-04-04 * Affected versions: 4.15, 4.16, 4.17, 4.18, 4.19, master * Needs backport to: master * Related links: Thank you for reporting this issue. Does booting with `'tsc=unstable` also work? Please the coreboot log messages for example by running `cbmem -1`. ---------------------------------------- dmesg: TSC found unstable after boot, most likely due to broken BIOS. Use 'tsc=unstable'. After a period of time the boot finished by auto-switching to hpet. Setting kernel parameter directly to clocksource=hpet the system is booting fast. Why is the faster clocksource tsc not working and tells coreboot is broken ? ---Files-------------------------------- cbmem.log (38.6 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account
Issue #478 has been updated by Robert Gruber. Affected OS set to xubuntu 22.04 LTS, Trisquel 11.0 ---------------------------------------- Bug #478: X200 booting Linux takes a long time with TSC (`clocksource=hpet` works) https://ticket.coreboot.org/issues/478#change-1468 * Author: Robert Gruber * Status: New * Priority: Normal * Target version: master * Start date: 2023-04-04 * Affected versions: 4.15, 4.16, 4.17, 4.18, 4.19, master * Needs backport to: master * Related links: Thank you for reporting this issue. Does booting with `'tsc=unstable` also work? Please the coreboot log messages for example by running `cbmem -1`. * Affected OS: xubuntu 22.04 LTS, Trisquel 11.0 ---------------------------------------- dmesg: TSC found unstable after boot, most likely due to broken BIOS. Use 'tsc=unstable'. After a period of time the boot finished by auto-switching to hpet. Setting kernel parameter directly to clocksource=hpet the system is booting fast. Why is the faster clocksource tsc not working and tells coreboot is broken ? ---Files-------------------------------- cbmem.log (38.6 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account
Issue #478 has been updated by Robert Gruber. Bill XIE wrote in #note-4:
Robert Gruber wrote:
dmesg: TSC found unstable after boot, most likely due to broken BIOS. Use 'tsc=unstable'. After a period of time the boot finished by auto-switching to hpet. Setting kernel parameter directly to clocksource=hpet the system is booting fast.
Why is the faster clocksource tsc not working and tells coreboot is broken ?
As stated in https://www.chromium.org/chromium-os/how-tos-and-troubleshooting/tsc-resynch... , there are 4 types of TSC, while a core 2 cpu only has Constant TSC, which may change on C state transitions.
Newer cpu like Ivy Bridge have nonstop_tsc and tsc_deadline in addition to constant_tsc. They can keep using tsc as clock source.
Does this issue remain on an x200 running vendor firmware?
Only coreboot is affected. On vendor firmware the system boots with kernel defaults and clocksource=hpet fast. ---------------------------------------- Bug #478: X200 booting Linux takes a long time with TSC (`clocksource=hpet` works) https://ticket.coreboot.org/issues/478#change-1469 * Author: Robert Gruber * Status: New * Priority: Normal * Target version: master * Start date: 2023-04-04 * Affected versions: 4.15, 4.16, 4.17, 4.18, 4.19, master * Needs backport to: master * Related links: Thank you for reporting this issue. Does booting with `'tsc=unstable` also work? Please the coreboot log messages for example by running `cbmem -1`. * Affected OS: xubuntu 22.04 LTS, Trisquel 11.0 ---------------------------------------- dmesg: TSC found unstable after boot, most likely due to broken BIOS. Use 'tsc=unstable'. After a period of time the boot finished by auto-switching to hpet. Setting kernel parameter directly to clocksource=hpet the system is booting fast. Why is the faster clocksource tsc not working and tells coreboot is broken ? ---Files-------------------------------- cbmem.log (38.6 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account
Issue #478 has been updated by Nico Huber. Can you provide a dmesg log? or even better, one with coreboot and one with vendor. It's probably just a flag somewhere that's telling Linux to use TSC. But that's easiest debugged in the OS. ---------------------------------------- Bug #478: X200 booting Linux takes a long time with TSC (`clocksource=hpet` works) https://ticket.coreboot.org/issues/478#change-1470 * Author: Robert Gruber * Status: New * Priority: Normal * Target version: master * Start date: 2023-04-04 * Affected versions: 4.15, 4.16, 4.17, 4.18, 4.19, master * Needs backport to: master * Related links: Thank you for reporting this issue. Does booting with `'tsc=unstable` also work? Please the coreboot log messages for example by running `cbmem -1`. * Affected OS: xubuntu 22.04 LTS, Trisquel 11.0 ---------------------------------------- dmesg: TSC found unstable after boot, most likely due to broken BIOS. Use 'tsc=unstable'. After a period of time the boot finished by auto-switching to hpet. Setting kernel parameter directly to clocksource=hpet the system is booting fast. Why is the faster clocksource tsc not working and tells coreboot is broken ? ---Files-------------------------------- cbmem.log (38.6 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account
Issue #478 has been updated by Robert Gruber. Paul Menzel wrote in #note-15:
$ sudo i2cdump -y 7 0x69 s
Is the output of i2cget still needed because of the deprecated i2cdump ? If yes, how do I get the required data with i2cget ? Output from i2cget: $ sudo i2cget -y 0 0x69 s Error: Data address invalid! Usage: i2cget [-f] [-y] [-a] I2CBUS CHIP-ADDRESS [DATA-ADDRESS [MODE [LENGTH]]] I2CBUS is an integer or an I2C bus name ADDRESS is an integer (0x08 - 0x77, or 0x00 - 0x7f if -a is given) MODE is one of: b (read byte data, default) w (read word data) c (write byte/read byte) s (read SMBus block data) i (read I2C block data) Append p for SMBus PEC LENGTH is the I2C block data length (between 1 and 32, default 32) ---------------------------------------- Bug #478: X200 booting Linux takes a long time with TSC (`clocksource=hpet` works) https://ticket.coreboot.org/issues/478#change-1526 * Author: Robert Gruber * Status: New * Priority: Normal * Target version: master * Start date: 2023-04-04 * Affected versions: 4.15, 4.16, 4.17, 4.18, 4.19, master * Needs backport to: master * Related links: Thank you for reporting this issue. Does booting with `'tsc=unstable` also work? Please the coreboot log messages for example by running `cbmem -1`. * Affected OS: xubuntu 22.04 LTS, Trisquel 11.0 ---------------------------------------- dmesg: TSC found unstable after boot, most likely due to broken BIOS. Use 'tsc=unstable'. After a period of time the boot finished by auto-switching to hpet. Setting kernel parameter directly to clocksource=hpet the system is booting fast. Why is the faster clocksource tsc not working and tells coreboot is broken ? ---Files-------------------------------- cbmem.log (38.6 KB) dmesg_slow.log (63.5 KB) dmesg_fast_with_clocksource_hpet.log (63.8 KB) dmesg-x200-vendor-kali.log (72.3 KB) dmesg-x200-cb-kali.log (63.9 KB) dmesg-x200-cb-kali-2.log (61.4 KB) dmesg_vendor_x200t_fast.log (85.8 KB) dmesg_vendor_x200t_fast_without_clocksource_parameter.log (85.8 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account
participants (4)
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Bill XIE -
Nico Huber
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Paul Menzel
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Robert Gruber