[LinuxBIOS] #87: flashrom issues on m57sli-s4
#87: flashrom issues on m57sli-s4 ---------------------------------+------------------------------------------ Reporter: ward | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: code | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ There is a problem with flashrom; it won't work reliably when the machine is booted under LinuxBIOS on the m57sli-s4. This is what I used to see: It works maybe 1 out of 10 times - it always works when booted with the proprietary BIOS. I can tell while it's flashing if it is good or not good: the speed of the flashing is moderately fast for a good flash. For a bad flash, it is either too fast, too slow, or it varies a lot during the flash. This is what I'm seeing today (with the latest rev of flashrom, 2744): Flashrom jumps from page 15 to page 224 while flashing, and then fails to verify. I've tried with several different chis (all of the same type though). {{{ # ./flashrom -vvvv -w /home/ward/Desktop/buildrom/buildrom-devel/deploy /gigabyte-m57sli.rom -V Calibrating delay loop... 537M loops per second. ok Found canidate at: 00000530-00000e2c Found LinuxBIOS table at: 00000530 lb_table found at address 0xb7e40530 LinuxBIOS header(24) checksum: e2db table(2300) checksum: 826c entries: 14 vendor id: GIGABYTE part id: m57sli Found chipset "NVIDIA MCP55": Enabling flash write... OK. Probing for Am29F040B, 512 KB probe_29f040b: id1 0xff, id2 0xff Probing for Am29F016D, 2048 KB probe_29f040b: id1 0xff, id2 0xff Probing for AE49F2008, 256 KB probe_jedec: id1 0xbf, id2 0x5b Probing for At29C040A, 512 KB probe_jedec: id1 0xbf, id2 0x5b Probing for At29C020, 256 KB probe_jedec: id1 0xbf, id2 0x5b Probing for Mx29f002, 256 KB probe_29f002: id1 0xbf, id2 0x5b Probing for SST29EE020A, 256 KB probe_jedec: id1 0xbf, id2 0x5b Probing for SST28SF040A, 512 KB probe_28sf040: id1 0xff, id2 0xff Probing for SST39SF010A, 128 KB probe_jedec: id1 0xbf, id2 0x5b Probing for SST39SF020A, 256 KB probe_jedec: id1 0xbf, id2 0x5b Probing for SST39SF040, 512 KB probe_jedec: id1 0xbf, id2 0x5b Probing for SST39VF020, 256 KB probe_jedec: id1 0xbf, id2 0x5b Probing for SST49LF040B, 512 KB probe_jedec: id1 0xbf, id2 0x5b Probing for SST49LF040, 512 KB probe_jedec: id1 0xbf, id2 0x5b Probing for SST49LF020A, 256 KB probe_jedec: id1 0xbf, id2 0x5b Probing for SST49LF080A, 1024 KB probe_jedec: id1 0xbf, id2 0x5b SST49LF080A found at physical address: 0xfff00000 Flash part is SST49LF080A (1024 KB) LinuxBIOS last image size (not rom size) is 1048576 bytes. MANUFACTURER: GIGABYTE MAINBOARD ID: m57sli This firmware image matches this motherboard. Programming Page: 0255 at address: 0x000ff000 Verifying flash address: 0x00000000 - FAILED }}} I should note that I'm using a bios savior to swap flash chips, and that the socket has been soldered onto the board manually. But under the proprietary bios there is never a problem, so... -- Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/87> LinuxBIOS <http://www.linuxbios.org/>
#87: flashrom issues on m57sli-s4 -------------------------+-------------------------------------------------- Reporter: ward | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: flashrom | Version: v2 Resolution: | Keywords: Dependencies: | Patchstatus: there is no patch -------------------------+-------------------------------------------------- Changes (by ward): * component: code => flashrom -- Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/87#comment:1> LinuxBIOS <http://www.linuxbios.org/>
#87: flashrom issues on m57sli-s4 -------------------------+-------------------------------------------------- Reporter: ward | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: flashrom | Version: v2 Resolution: | Keywords: Dependencies: | Patchstatus: there is no patch -------------------------+-------------------------------------------------- Comment (by hailfinger): Two possible reasons: * Differing LPC bus frequency.[[BR]] * Differing GPIO configuration, which may result in uninitialized #WP and/or #WE on the flash chip. You may want to verify both settings with an oscilloscope or any other tool you have handy. In case you want to verify correct settings from the software side, you have to make sure BIOS shadowing is disabled, then run a few timing trials of flash readout both under LB and proprietary. The speed should not differ. For GPIO configuration, check superiotool output differences and MCP55 GPIO registers (the latter may require a NDA to get a map of meanings). -- Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/87#comment:2> LinuxBIOS <http://www.linuxbios.org/>
#87: flashrom issues on m57sli-s4 -------------------------+-------------------------------------------------- Reporter: ward | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: flashrom | Version: v2 Resolution: | Keywords: Dependencies: | Patchstatus: there is no patch -------------------------+-------------------------------------------------- Comment (by hailfinger): For timing tests of flash readout, make sure CPU frequency scaling and power management are disabled. Then run time flashrom -V --read test.rom; md5sum test.rom on an idle system a few times in a row. If the "delay loops per second" value varies a lot, either the system is under load or CPU frequency scaling is active. If the md5sum is not constant, something fishy is going on. The real/user/sys time needed for the command is what I'm interested in. The delay loop value is useless for LPC bus frequency measurement. -- Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/87#comment:3> LinuxBIOS <http://www.linuxbios.org/>
#87: flashrom issues on m57sli-s4 -------------------------+-------------------------------------------------- Reporter: ward | Owner: hailfinger Type: defect | Status: new Priority: major | Milestone: Component: flashrom | Version: v2 Resolution: | Keywords: Dependencies: | Patchstatus: there is no patch -------------------------+-------------------------------------------------- Changes (by hailfinger): * owner: somebody => hailfinger Comment: I need superiotool output for a board with parallel flash running under LB. NOW. AFAICS the flash configuration is totally botched on LB with floating GPIOs, wrong timing etc. I have a patch pending which will solve the flashing problem on all M57SLI boards, but I refuse to send it to the list before I have superiotool output to verify. -- Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/87#comment:4> LinuxBIOS <http://www.linuxbios.org/>
Hi Carl-Daniel, On Thu, Nov 08, 2007 at 02:05:16PM -0000, LinuxBIOS wrote:
#87: flashrom issues on m57sli-s4 -------------------------+-------------------------------------------------- Reporter: ward | Owner: hailfinger Type: defect | Status: new Priority: major | Milestone: Component: flashrom | Version: v2 Resolution: | Keywords: Dependencies: | Patchstatus: there is no patch -------------------------+-------------------------------------------------- Changes (by hailfinger):
* owner: somebody => hailfinger
Comment:
I need superiotool output for a board with parallel flash running under LB. NOW.
LinuxBIOS: http://ward.vandewege.net/superiotool-lb.m57sli.dump Proprietary BIOS: http://ward.vandewege.net/superiotool-prop.m57sli.dump
AFAICS the flash configuration is totally botched on LB with floating GPIOs, wrong timing etc.
I have a patch pending which will solve the flashing problem on all M57SLI boards, but I refuse to send it to the list before I have superiotool output to verify.
Looking forward to that patch! Thanks, Ward. -- Ward Vandewege <ward@fsf.org> Free Software Foundation - Senior System Administrator
Hi Ward, On 08.11.2007 16:22, Ward Vandewege wrote:
On Thu, Nov 08, 2007 at 02:05:16PM -0000, LinuxBIOS wrote:
#87: flashrom issues on m57sli-s4
I need superiotool output for a board with parallel flash running under LB. NOW.
LinuxBIOS: http://ward.vandewege.net/superiotool-lb.m57sli.dump Proprietary BIOS: http://ward.vandewege.net/superiotool-prop.m57sli.dump
Thanks! ldn any idx 07 20 21 22 23 24 2b val 06 87 16 00 01 00 00 plcc lb xx val 0a 87 16 00 11 00 00 plcc prop xx val 0a 87 16 00 11 1a 00 soic prop xx xx def NA 87 16 01 00 00 00 ldn 0x7 idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd val 00 00 00 00 00 00 1f 00 00 00 00 00 00 00 01 20 38 00 00 00 00 00 00 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 32 00 plcc lb xx xx xx xx xx xx xx xx xx xx xx xx val 00 43 20 00 81 00 1f 00 00 08 00 00 00 00 01 00 38 00 00 00 00 00 00 00 00 00 00 00 01 00 00 43 20 00 00 00 40 00 00 00 00 00 00 00 00 10 40 00 00 00 00 28 00 00 00 00 00 32 00 plcc prop xx xx xx val 00 43 20 00 81 00 1f 00 00 08 00 08 20 00 00 00 38 00 00 00 00 00 00 00 00 00 00 00 01 00 00 43 20 00 00 00 40 00 00 00 00 00 00 00 00 10 40 00 00 00 00 28 00 00 00 00 00 32 00 soic prop xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 20 38 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 The patch below will NOT work, I have yet to figure out how to tell Config.lb that I want to set a 8-bit value (which is a simple value and not irq/drq/io) in a superio section. But it should be enough to base a real patch on it. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Index: LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb =================================================================== --- LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb (Revision 2953) +++ LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb (Arbeitskopie) @@ -239,7 +239,9 @@ device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/ite/it8716f - device pnp 2e.0 off # Floppy + device pnp 2e.0 off # Floppy and anyLDN + 0x23 = 0x11 # watchdog from CLKIN, CLKIN = 24 MHz + #0x24 = 0x1a # serial flash (SPI only) io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 @@ -269,6 +271,30 @@ device pnp 2e.6 on # Mouse irq 0x70 = 12 end + device pnp 2e.7 on # GPIO, SPI flash + 0x25 = 0x0 # pin 84 is not GP10 + 0x26 = 0x43 # pin 21 is GP26, pin 26 is GP21, pin 27 is GP20 + 0x27 = 0x20 # pin 13 is GP35 + #0x28 = 0x0 # pin 70 is not GP46 + 0x29 = 0x81 # pin 6,3,128,127,126 is GP63,64,65,66,67 + #0x2c = 0x1f # Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V + io 0x62 = 0x800 # simple i/o base + #io 0x64 = 0x820 # serial flash io (SPI only) + #0x71 = 0x1 # watch dog force timeout (parallel flash only) + irq 0x72 = 0x0 # no WDT interrupt + 0xb8 = 0x0 # GPIO pin set 1 disable internal pullup + 0xbc = 0x01 # GPIO pin set 5 enable internal pullup + #0xc0 = 0x0 # SIO pin set 1 alternate function + 0xc1 = 0x43 # SIO pin set 2 mixed function + 0xc2 = 0x20 # SIO pin set 3 mixed function + #0xc3 = 0x0 # SIO pin set 4 alternate function + #0xc8 = 0x0 # SIO pin set 1 input mode + 0xc9 = 0x0 # SIO pin set 2 mixed input/output mode + #0xcb = 0x0 # SIO pin set 4 input mode + #0xf0 = 0x10 # generate SMI# on EC IRQ + #0xf1 = 0x40 # SMI# level trigger + 0xf6 = 0x28 # HWMON alert beep pin location + end device pnp 2e.8 off # MIDI io 0x60 = 0x300 irq 0x70 = 10 @@ -305,6 +331,7 @@ device i2c 57 on end end end # SM +#wtf?!? we already have device pci 1.1 in the section above device pci 1.1 on # SM 1 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? # chip drivers/generic/generic #PCIXA Slot1 The "wtf?!?" comment is intentional and designates another bug. However, I have no idea which device number we need here. Regards, Carl-Daniel
Hi Ward, On 08.11.2007 16:51, Carl-Daniel Hailfinger wrote:
On 08.11.2007 16:22, Ward Vandewege wrote:
On Thu, Nov 08, 2007 at 02:05:16PM -0000, LinuxBIOS wrote:
#87: flashrom issues on m57sli-s4
I need superiotool output for a board with parallel flash running under LB. NOW.
LinuxBIOS: http://ward.vandewege.net/superiotool-lb.m57sli.dump Proprietary BIOS: http://ward.vandewege.net/superiotool-prop.m57sli.dump
Can you retest with the following patch applied? Thanks.
The "wtf?!?" comment is intentional and designates another bug. However, I have no idea which device number we need here.
Regards, Carl-Daniel Try to fix a few loose ends on the GA-M57SLI Super I/O GPIO configuration. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> --- Index: LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb =================================================================== --- LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb (Revision 2953) +++ LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb (Arbeitskopie) @@ -239,7 +239,9 @@ device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/ite/it8716f - device pnp 2e.0 off # Floppy + device pnp 2e.0 off # Floppy and anyLDN + irq 0x23 = 0x11 # watchdog from CLKIN, CLKIN = 24 MHz + #0x24 = 0x1a # serial flash (SPI only) io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 @@ -269,6 +271,30 @@ device pnp 2e.6 on # Mouse irq 0x70 = 12 end + device pnp 2e.7 on # GPIO, SPI flash + irq 0x25 = 0x0 # pin 84 is not GP10 + irq 0x26 = 0x43 # pin 21 is GP26, pin 26 is GP21, pin 27 is GP20 + irq 0x27 = 0x20 # pin 13 is GP35 + #0x28 = 0x0 # pin 70 is not GP46 + irq 0x29 = 0x81 # pin 6,3,128,127,126 is GP63,64,65,66,67 + #0x2c = 0x1f # Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V + io 0x62 = 0x800 # simple i/o base + #io 0x64 = 0x820 # serial flash io (SPI only) + #0x71 = 0x1 # watch dog force timeout (parallel flash only) + irq 0x72 = 0x0 # no WDT interrupt + irq 0xb8 = 0x0 # GPIO pin set 1 disable internal pullup + irq 0xbc = 0x01 # GPIO pin set 5 enable internal pullup + #0xc0 = 0x0 # SIO pin set 1 alternate function + irq 0xc1 = 0x43 # SIO pin set 2 mixed function + irq 0xc2 = 0x20 # SIO pin set 3 mixed function + #0xc3 = 0x0 # SIO pin set 4 alternate function + #0xc8 = 0x0 # SIO pin set 1 input mode + irq 0xc9 = 0x0 # SIO pin set 2 mixed input/output mode + #0xcb = 0x0 # SIO pin set 4 input mode + #0xf0 = 0x10 # generate SMI# on EC IRQ + #0xf1 = 0x40 # SMI# level trigger + irq 0xf6 = 0x28 # HWMON alert beep pin location + end device pnp 2e.8 off # MIDI io 0x60 = 0x300 irq 0x70 = 10 @@ -305,6 +331,7 @@ device i2c 57 on end end end # SM +#wtf?!? we already have device pci 1.1 in the section above device pci 1.1 on # SM 1 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? # chip drivers/generic/generic #PCIXA Slot1
Hi Carl-Daniel, is it possible that there is no change at all in superiotool output? Or did I not propperly clean my build tree? (I did a ./buildtarget in the target directory after patching and a make clean prior to building as usual). Regards, Andi On Sat, Nov 10, 2007 at 12:48:34AM +0100, Carl-Daniel Hailfinger wrote:
Hi Ward,
On 08.11.2007 16:51, Carl-Daniel Hailfinger wrote:
On 08.11.2007 16:22, Ward Vandewege wrote:
On Thu, Nov 08, 2007 at 02:05:16PM -0000, LinuxBIOS wrote:
#87: flashrom issues on m57sli-s4
I need superiotool output for a board with parallel flash running under LB. NOW.
LinuxBIOS: http://ward.vandewege.net/superiotool-lb.m57sli.dump Proprietary BIOS: http://ward.vandewege.net/superiotool-prop.m57sli.dump
Can you retest with the following patch applied? Thanks.
The "wtf?!?" comment is intentional and designates another bug. However, I have no idea which device number we need here.
Regards, Carl-Daniel
Try to fix a few loose ends on the GA-M57SLI Super I/O GPIO configuration.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
---
Index: LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb =================================================================== --- LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb (Revision 2953) +++ LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb (Arbeitskopie) @@ -239,7 +239,9 @@ device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/ite/it8716f - device pnp 2e.0 off # Floppy + device pnp 2e.0 off # Floppy and anyLDN + irq 0x23 = 0x11 # watchdog from CLKIN, CLKIN = 24 MHz + #0x24 = 0x1a # serial flash (SPI only) io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 @@ -269,6 +271,30 @@ device pnp 2e.6 on # Mouse irq 0x70 = 12 end + device pnp 2e.7 on # GPIO, SPI flash + irq 0x25 = 0x0 # pin 84 is not GP10 + irq 0x26 = 0x43 # pin 21 is GP26, pin 26 is GP21, pin 27 is GP20 + irq 0x27 = 0x20 # pin 13 is GP35 + #0x28 = 0x0 # pin 70 is not GP46 + irq 0x29 = 0x81 # pin 6,3,128,127,126 is GP63,64,65,66,67 + #0x2c = 0x1f # Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V + io 0x62 = 0x800 # simple i/o base + #io 0x64 = 0x820 # serial flash io (SPI only) + #0x71 = 0x1 # watch dog force timeout (parallel flash only) + irq 0x72 = 0x0 # no WDT interrupt + irq 0xb8 = 0x0 # GPIO pin set 1 disable internal pullup + irq 0xbc = 0x01 # GPIO pin set 5 enable internal pullup + #0xc0 = 0x0 # SIO pin set 1 alternate function + irq 0xc1 = 0x43 # SIO pin set 2 mixed function + irq 0xc2 = 0x20 # SIO pin set 3 mixed function + #0xc3 = 0x0 # SIO pin set 4 alternate function + #0xc8 = 0x0 # SIO pin set 1 input mode + irq 0xc9 = 0x0 # SIO pin set 2 mixed input/output mode + #0xcb = 0x0 # SIO pin set 4 input mode + #0xf0 = 0x10 # generate SMI# on EC IRQ + #0xf1 = 0x40 # SMI# level trigger + irq 0xf6 = 0x28 # HWMON alert beep pin location + end device pnp 2e.8 off # MIDI io 0x60 = 0x300 irq 0x70 = 10 @@ -305,6 +331,7 @@ device i2c 57 on end end end # SM +#wtf?!? we already have device pci 1.1 in the section above device pci 1.1 on # SM 1 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? # chip drivers/generic/generic #PCIXA Slot1
-- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
Hi Andi, On 10.11.2007 09:45, Andreas B. Mundt wrote:
is it possible that there is no change at all in superiotool output?
Superiotool output should have changed for LDN 0x7 and NOLDN (the registers before LDN 0x0), the rest should be identical to the output before.
Or did I not propperly clean my build tree? (I did a ./buildtarget in the target directory after patching and a make clean prior to building as usual).
Try to "rm -r gigabyte/m57sli/m57sli", then run buildtarget again, then run "grep -r base=0x800 gigabyte/m57sli/m57sli". This should give you three lines if the patch was applied correctly.
./targets/gigabyte/m57sli/m57sli/failover/static.c: { .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO, .index=0x62, .base=0x800}, ./targets/gigabyte/m57sli/m57sli/fallback/static.c: { .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO, .index=0x62, .base=0x800}, ./targets/gigabyte/m57sli/m57sli/normal/static.c: { .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO, .index=0x62, .base=0x800},
Regards, Carl-Daniel
On Sat, Nov 10, 2007 at 12:43:39PM +0100, Carl-Daniel Hailfinger wrote:
Try to "rm -r gigabyte/m57sli/m57sli", then run buildtarget again, then run "grep -r base=0x800 gigabyte/m57sli/m57sli". This should give you three lines if the patch was applied correctly.
./targets/gigabyte/m57sli/m57sli/failover/static.c: { .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO, .index=0x62, .base=0x800}, ./targets/gigabyte/m57sli/m57sli/fallback/static.c: { .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO, .index=0x62, .base=0x800}, ./targets/gigabyte/m57sli/m57sli/normal/static.c: { .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO, .index=0x62, .base=0x800},
Hi Carl-Daniel, I tried as you suggested and checked it, but still no difference in superiotool output compared to standard LB! I found that I am not able to boot the "Normal" image (after using lxbios), but I guess this is unrelated as the "fallback" image should have the changes as well. So far, Andi
Hi Andi, On 10.11.2007 14:33, Andreas B. Mundt wrote:
I tried as you suggested and checked it, but still no difference in superiotool output compared to standard LB!
Can you try this patch on top of the existing patch? It will give you better debug output for superio config. Index: src/devices/pnp_device.c =================================================================== --- src/devices/pnp_device.c (Revision 2953) +++ src/devices/pnp_device.c (Arbeitskopie) @@ -96,6 +96,8 @@ } /* Now store the resource */ + printk_err("TRACE: %s, index %02x: writing %04x\n", + dev_path(dev), resource->index, resource->base); if (resource->flags & IORESOURCE_IO) { pnp_set_iobase(dev, resource->index, resource->base); } @@ -119,6 +121,8 @@ { int i; + printk_err("TRACE: %s, selecting logical device %02x\n", + dev_path(dev), dev->path.u.pnp.device); /* Select the device */ pnp_set_logical_device(dev); Can you then post the serial boot log (minicom capture)? It should have a few lines with "TRACE:" in it. Then we can check whether the values are set or not. Thanks, Carl-Daniel
On Sat, Nov 10, 2007 at 05:04:32PM +0100, Carl-Daniel Hailfinger wrote:
Hi Andi,
Can you try this patch on top of the existing patch? It will give you better debug output for superio config.
......
Can you then post the serial boot log (minicom capture)? It should have a few lines with "TRACE:" in it. Then we can check whether the values are set or not.
Hi Carl-Daniel, here are the results, I have not looked into details yet, but the TRACE is there: LinuxBIOS-2.0.0_m57sli_Fallback Sat Nov 10 20:04:37 CET 2007 starting... *sysinfo range: [000cf000,000cf730) bsp_apicid=00 core0 started: started ap apicid: 01 SBLink=00 NC node|link=00 begin msr fid, vid 3107121207110202 set fid failed for apicid =00 end msr fid, vid 3107120707110210 mcp55_num:01 ht reset - LinuxBIOS-2.0.0_m57sli_Fallback Sat Nov 10 20:04:37 CET 2007 starting... *sysinfo range: [000cf000,000cf730) bsp_apicid=00 core0 started: started ap apicid: 01 SBLink=00 NC node|link=00 begin msr fid, vid 3107120707110210 set fid failed for apicid =00 end msr fid, vid 3107120707110210 mcp55_num:01 Ram1.00 Ram2.00 Unbuffered 333Mhz Interleaved RAM: 0x00400000 KB Ram3 dimm_mask = 00000033 x4_mask = 00000000 x16_mask = 00000000 single_rank_mask = 00000000 ODC = 00111322 Addr Timing= 002b2220 Initializing memory: done RAM: 0x00500000 KB Setting variable MTRR 2, base: 0MB, range: 2048MB, type WB Setting variable MTRR 3, base: 2048MB, range: 1024MB, type WB set DQS timing:RcvrEn:Pass1: 00 CTLRMaxDelay=13 done set DQS timing:DQSPos: 00 done set DQS timing:RcvrEn:Pass2: 00 CTLRMaxDelay=34 done Total DQS Training : tsc [00]=0000000045b035fc Total DQS Training : tsc [01]=000000004760b7a6 Total DQS Training : tsc [02]=00000000de2ca1bf Total DQS Training : tsc [03]=00000000e067edff Ram4 v_esp=000ceea8 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Copying LinuxBIOS to RAM. src=fffdf000 dst=00100000 linxbios_ram.nrv2b length = 0000d68c linxbios_ram.bin length = 000224ec Jumping to LinuxBIOS. LinuxBIOS-2.0.0_m57sli_Fallback Sat Nov 10 20:04:37 CET 2007 booting... Enumerating buses... APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled PCI: 00:18.3 siblings=1 CPU: APIC: 00 enabled CPU: APIC: 01 enabled PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] enabled PCI: 00:00.0 [10de/0369] enabled PCI: 00:00.0 [10de/0369] enabled next_unitid: 0010 PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [10de/0369] enabled PCI: 00:01.0 [10de/0360] enabled PCI: 00:01.1 [10de/0368] enabled PCI: 00:01.2 [10de/036a] enabled PCI: 00:01.3 [10de/036b] enabled PCI: 00:02.0 [10de/036c] enabled PCI: 00:02.1 [10de/036d] enabled PCI: 00:04.0 [10de/036e] enabled PCI: 00:05.0 [10de/037f] enabled PCI: 00:05.1 [10de/037f] enabled PCI: 00:05.2 [10de/037f] enabled PCI: 00:06.0 [10de/0370] enabled PCI: 00:06.1 [10de/0371] enabled PCI: 00:08.0 [10de/0373] enabled PCI: 00:0a.0 [10de/0376] enabled PCI: 00:0b.0 [10de/0374] enabled PCI: 00:0c.0 [10de/0374] enabled PCI: 00:0d.0 [10de/0378] enabled PCI: 00:0e.0 [10de/0375] enabled PCI: 00:0f.0 [10de/0377] enabled PNP: 002e.0 disabled PNP: 002e.1 enabled PNP: 002e.2 disabled PNP: 002e.3 disabled PNP: 002e.4 enabled PNP: 002e.5 enabled PNP: 002e.6 enabled PNP: 002e.7 enabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled smbus: PCI: 00:01.1[0]->I2C: 01:50 enabled smbus: PCI: 00:01.1[0]->I2C: 01:51 enabled smbus: PCI: 00:01.1[0]->I2C: 01:52 enabled smbus: PCI: 00:01.1[0]->I2C: 01:53 enabled smbus: PCI: 00:01.1[0]->I2C: 01:54 enabled smbus: PCI: 00:01.1[0]->I2C: 01:55 enabled smbus: PCI: 00:01.1[0]->I2C: 01:56 enabled smbus: PCI: 00:01.1[0]->I2C: 01:57 enabled smbus: PCI: 00:01.1[1]->I2C: 02:51 enabled PCI: pci_scan_bus for bus 01 PCI: 01:07.0 [1102/0002] enabled PCI: 01:07.1 [1102/7002] enabled PCI: 01:0a.0 [104c/8024] enabled PCI: pci_scan_bus returning with max=001 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 PCI: pci_scan_bus for bus 03 PCI: pci_scan_bus returning with max=003 PCI: pci_scan_bus for bus 04 PCI: pci_scan_bus returning with max=004 PCI: pci_scan_bus for bus 05 PCI: pci_scan_bus returning with max=005 PCI: pci_scan_bus for bus 06 PCI: pci_scan_bus returning with max=006 PCI: pci_scan_bus for bus 07 PCI: 07:00.0 [10de/0392] enabled PCI: pci_scan_bus returning with max=007 PCI: pci_scan_bus returning with max=007 PCI: pci_scan_bus returning with max=007 done Allocating resources... Reading resources... PNP: 002e.7 missing read_resources PCI: 00:06.0 24 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:0a.0 1c <- [0x00fffff000 - 0x00ffffefff] size 0x00000000 gran 0x0c bus 02 io PCI: 00:0a.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:0a.0 20 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 02 mem PCI: 00:0b.0 1c <- [0x00fffff000 - 0x00ffffefff] size 0x00000000 gran 0x0c bus 03 io PCI: 00:0b.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] size 0x00000000 gran 0x14 bus 03 prefmem PCI: 00:0b.0 20 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 03 mem PCI: 00:0c.0 1c <- [0x00fffff000 - 0x00ffffefff] size 0x00000000 gran 0x0c bus 04 io PCI: 00:0c.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] size 0x00000000 gran 0x14 bus 04 prefmem PCI: 00:0c.0 20 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 04 mem PCI: 00:0d.0 1c <- [0x00fffff000 - 0x00ffffefff] size 0x00000000 gran 0x0c bus 05 io PCI: 00:0d.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] size 0x00000000 gran 0x14 bus 05 prefmem PCI: 00:0d.0 20 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 05 mem PCI: 00:0e.0 1c <- [0x00fffff000 - 0x00ffffefff] size 0x00000000 gran 0x0c bus 06 io PCI: 00:0e.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] size 0x00000000 gran 0x14 bus 06 prefmem PCI: 00:0e.0 20 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 06 mem Done reading resources. Allocating VGA resource PCI: 07:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:0f.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Setting resources... VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device PCI: 00:18.0 1c0 <- [0x0000001000 - 0x0000004fff] size 0x00004000 gran 0x0c io <node 0 link 0> PCI: 00:18.0 1b8 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x14 prefmem <node 0 link 0> PCI: 00:18.0 1b0 <- [0x00f4000000 - 0x00f62fffff] size 0x02300000 gran 0x14 mem <node 0 link 0> PCI: 00:01.0 14 <- [0x00f6244000 - 0x00f6244fff] size 0x00001000 gran 0x0c mem TRACE: PNP: 002e.1, selecting logical device 01 TRACE: PNP: 002e.1, index 60: writing 03f8 PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io TRACE: PNP: 002e.1, index 70: writing 0004 PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq TRACE: PNP: 002e.4, selecting logical device 04 TRACE: PNP: 002e.4, index 60: writing 0290 PNP: 002e.4 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io TRACE: PNP: 002e.4, index 62: writing 0230 PNP: 002e.4 62 <- [0x0000000230 - 0x0000000237] size 0x00000008 gran 0x03 io TRACE: PNP: 002e.4, index 70: writing 0009 PNP: 002e.4 70 <- [0x0000000009 - 0x0000000009] size 0x00000001 gran 0x00 irq TRACE: PNP: 002e.5, selecting logical device 05 TRACE: PNP: 002e.5, index 60: writing 0060 PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io TRACE: PNP: 002e.5, index 62: writing 0064 PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io TRACE: PNP: 002e.5, index 70: writing 0001 PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq TRACE: PNP: 002e.6, selecting logical device 06 TRACE: PNP: 002e.6, index 70: writing 000c PNP: 002e.6 70 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq PNP: 002e.7 missing set_resources PCI: 00:01.1 10 <- [0x0000003c00 - 0x0000003c3f] size 0x00000040 gran 0x06 io PCI: 00:01.1 20 <- [0x0000003c40 - 0x0000003c7f] size 0x00000040 gran 0x06 io PCI: 00:01.1 24 <- [0x0000003c80 - 0x0000003cbf] size 0x00000040 gran 0x06 io PCI: 00:01.1 60 <- [0x0000003000 - 0x00000030ff] size 0x00000100 gran 0x08 io PCI: 00:01.1 64 <- [0x0000003400 - 0x00000034ff] size 0x00000100 gran 0x08 io PCI: 00:01.1 68 <- [0x0000003800 - 0x00000038ff] size 0x00000100 gran 0x08 io PCI: 00:01.3 10 <- [0x00f6200000 - 0x00f623ffff] size 0x00040000 gran 0x12 mem PCI: 00:02.0 10 <- [0x00f6245000 - 0x00f6245fff] size 0x00001000 gran 0x0c mem PCI: 00:02.1 10 <- [0x00f624a000 - 0x00f624a0ff] size 0x00000100 gran 0x08 mem PCI: 00:04.0 20 <- [0x0000003cc0 - 0x0000003ccf] size 0x00000010 gran 0x04 io PCI: 00:05.0 10 <- [0x0000004000 - 0x0000004007] size 0x00000008 gran 0x03 io PCI: 00:05.0 14 <- [0x0000004070 - 0x0000004073] size 0x00000004 gran 0x02 io PCI: 00:05.0 18 <- [0x0000004010 - 0x0000004017] size 0x00000008 gran 0x03 io PCI: 00:05.0 1c <- [0x0000004080 - 0x0000004083] size 0x00000004 gran 0x02 io PCI: 00:05.0 20 <- [0x0000003cd0 - 0x0000003cdf] size 0x00000010 gran 0x04 io PCI: 00:05.0 24 <- [0x00f6246000 - 0x00f6246fff] size 0x00001000 gran 0x0c mem PCI: 00:05.1 10 <- [0x0000004020 - 0x0000004027] size 0x00000008 gran 0x03 io PCI: 00:05.1 14 <- [0x0000004090 - 0x0000004093] size 0x00000004 gran 0x02 io PCI: 00:05.1 18 <- [0x0000004030 - 0x0000004037] size 0x00000008 gran 0x03 io PCI: 00:05.1 1c <- [0x00000040a0 - 0x00000040a3] size 0x00000004 gran 0x02 io PCI: 00:05.1 20 <- [0x0000003ce0 - 0x0000003cef] size 0x00000010 gran 0x04 io PCI: 00:05.1 24 <- [0x00f6247000 - 0x00f6247fff] size 0x00001000 gran 0x0c mem PCI: 00:05.2 10 <- [0x0000004040 - 0x0000004047] size 0x00000008 gran 0x03 io PCI: 00:05.2 14 <- [0x00000040b0 - 0x00000040b3] size 0x00000004 gran 0x02 io PCI: 00:05.2 18 <- [0x0000004050 - 0x0000004057] size 0x00000008 gran 0x03 io PCI: 00:05.2 1c <- [0x00000040c0 - 0x00000040c3] size 0x00000004 gran 0x02 io PCI: 00:05.2 20 <- [0x0000003cf0 - 0x0000003cff] size 0x00000010 gran 0x04 io PCI: 00:05.2 24 <- [0x00f6248000 - 0x00f6248fff] size 0x00001000 gran 0x0c mem PCI: 00:06.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io PCI: 00:06.0 20 <- [0x00f6100000 - 0x00f61fffff] size 0x00100000 gran 0x14 bus 01 mem PCI: 01:07.0 10 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io PCI: 01:07.1 10 <- [0x0000001020 - 0x0000001027] size 0x00000008 gran 0x03 io PCI: 01:0a.0 10 <- [0x00f6104000 - 0x00f61047ff] size 0x00000800 gran 0x0b mem PCI: 01:0a.0 14 <- [0x00f6100000 - 0x00f6103fff] size 0x00004000 gran 0x0e mem PCI: 00:06.1 10 <- [0x00f6240000 - 0x00f6243fff] size 0x00004000 gran 0x0e mem PCI: 00:08.0 10 <- [0x00f6249000 - 0x00f6249fff] size 0x00001000 gran 0x0c mem PCI: 00:08.0 14 <- [0x0000004060 - 0x0000004067] size 0x00000008 gran 0x03 io PCI: 00:08.0 18 <- [0x00f624b000 - 0x00f624b0ff] size 0x00000100 gran 0x08 mem PCI: 00:08.0 1c <- [0x00f624c000 - 0x00f624c00f] size 0x00000010 gran 0x04 mem PCI: 00:0f.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 07 io PCI: 00:0f.0 24 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x14 bus 07 prefmem PCI: 00:0f.0 20 <- [0x00f4000000 - 0x00f60fffff] size 0x02100000 gran 0x14 bus 07 mem PCI: 07:00.0 10 <- [0x00f4000000 - 0x00f4ffffff] size 0x01000000 gran 0x18 mem PCI: 07:00.0 14 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem64 PCI: 07:00.0 1c <- [0x00f5000000 - 0x00f5ffffff] size 0x01000000 gran 0x18 mem64 PCI: 07:00.0 24 <- [0x0000002000 - 0x000000207f] size 0x00000080 gran 0x07 io PCI: 07:00.0 30 <- [0x00f6000000 - 0x00f601ffff] size 0x00020000 gran 0x11 romem PCI: 00:18.3 94 <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x1a mem <gart> Done setting resources. Done allocating resources. Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:00.0 subsystem <- 1022/2b80 PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 subsystem <- 1022/2b80 PCI: 00:01.0 cmd <- 0f mcp55 lpc decode:PNP: 002e.1, base=0x000003f8, end=0x000003ff mcp55 lpc decode:PNP: 002e.4, base=0x00000290, end=0x00000297 mcp55 lpc decode:PNP: 002e.4, base=0x00000230, end=0x00000237 mcp55 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060 mcp55 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064 PNP: 002e.7 missing enable_resources PCI: 00:01.1 subsystem <- 1022/2b80 PCI: 00:01.1 cmd <- 01 PCI: 00:01.2 cmd <- 400 PCI: 00:01.3 cmd <- 02 PCI: 00:02.0 subsystem <- 1022/2b80 PCI: 00:02.0 cmd <- 02 PCI: 00:02.1 subsystem <- 1022/2b80 PCI: 00:02.1 cmd <- 02 PCI: 00:04.0 subsystem <- 1022/2b80 PCI: 00:04.0 cmd <- 01 PCI: 00:05.0 subsystem <- 1022/2b80 PCI: 00:05.0 cmd <- 03 PCI: 00:05.1 subsystem <- 1022/2b80 PCI: 00:05.1 cmd <- 03 PCI: 00:05.2 subsystem <- 1022/2b80 PCI: 00:05.2 cmd <- 03 PCI: 00:06.0 bridge ctrl <- 0a03 PCI: 00:06.0 cmd <- 107 PCI: 01:07.0 cmd <- 01 PCI: 01:07.1 cmd <- 01 PCI: 01:0a.0 cmd <- 02 PCI: 00:06.1 subsystem <- 1022/2b80 PCI: 00:06.1 cmd <- 02 PCI: 00:08.0 subsystem <- 1022/2b80 PCI: 00:08.0 cmd <- 03 PCI: 00:0a.0 bridge ctrl <- 0003 PCI: 00:0a.0 cmd <- 00 PCI: 00:0b.0 bridge ctrl <- 0003 PCI: 00:0b.0 cmd <- 00 PCI: 00:0c.0 bridge ctrl <- 0003 PCI: 00:0c.0 cmd <- 00 PCI: 00:0d.0 bridge ctrl <- 0003 PCI: 00:0d.0 cmd <- 00 PCI: 00:0e.0 bridge ctrl <- 0003 PCI: 00:0e.0 cmd <- 00 PCI: 00:0f.0 bridge ctrl <- 000b PCI: 00:0f.0 cmd <- 07 PCI: 07:00.0 cmd <- 03 PCI: 00:18.1 subsystem <- 1022/2b80 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1022/2b80 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init start_eip=0x00006000, offset=0x00110000, code_size=0x0000005b Initializing CPU #0 CPU: vendor AMD device 60fb1 CPU: family 0f, model 6b, stepping 01 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 4096MB, type WB Setting variable MTRR 1, base: 4096MB, range: 1024MB, type WB Setting variable MTRR 2, base: 3072MB, range: 1024MB, type UC DONE variable MTRRs Clear out the extra MTRR's MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU model AMD Athlon(tm) 64 X2 Dual Core Processor 4800+ Setting up local apic... apic_id: 0x00 done. ECC Disabled CPU #0 Initialized Initializing CPU #1 Waiting for 1 CPUS to stop CPU: vendor AMD device 60fb1 CPU: family 0f, model 6b, stepping 01 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 4096MB, type WB Setting variable MTRR 1, base: 4096MB, range: 1024MB, type WB Setting variable MTRR 2, base: 3072MB, range: 1024MB, type UC DONE variable MTRRs Clear out the extra MTRR's MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU model AMD Athlon(tm) 64 X2 Dual Core Processor 4800+ Setting up local apic... apic_id: 0x01 done. CPU #1 Initialized All AP CPUs stopped PCI: 00:18.0 init PCI: 00:01.0 init set power on after power fail RTC Init RTC: Checksum invalid zeroing cmos Invalid CMOS LB checksum PNP: 002e.1 init PNP: 002e.4 init FAN_CTL: reg = 0x02a9, read value = 0x50 FAN_CTL: reg = 0x02a9, writing value = 0xd7 PNP: 002e.5 init Keyboard init... PNP: 002e.6 init PCI: 00:01.1 init PCI: 00:02.1 init PCI: 00:04.0 init IDE0 PCI: 00:05.0 init SATA S SATA P PCI: 00:05.1 init SATA S SATA P PCI: 00:05.2 init SATA S SATA P PCI: 00:06.0 init dev_root mem base = 0x00e0000000 [0x50] <-- 0xe0000000 PCI: 00:06.1 init base = f6240000 codec_mask = 01 codec viddid: 10ec0883 No verb! PCI: 00:08.0 init MCP55 MAC PHY ID 0x01410c00 PHY ADDR 1 PCI: 00:0a.0 init PCI: 00:0b.0 init PCI: 00:0c.0 init PCI: 00:0d.0 init PCI: 00:0e.0 init PCI: 00:0f.0 init PCI: 00:18.1 init PCI: 00:18.2 init PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:01.2 init PCI: 00:01.3 init PCI: 01:07.0 init PCI: 01:07.1 init PCI: 01:0a.0 init PCI: 07:00.0 init rom address for PCI: 07:00.0 = f6000000 copying VGA ROM Image from 0xf6000000 to 0xc0000, 0xf600 bytes entering emulator halt_sys: file /home/andi/freeBIOS/LinuxBIOSv2/src/devices/emulator/x86emu/ops.c, line 4387 Devices initialized Writing IRQ routing tables to 0xf0000...done. Wrote the mp table end at: 00000020 - 00000274 Moving GDT to 0x500...ok Adjust low_table_end from 0x00000530 to 0x00001000 Adjust rom_table_end from 0x000f0400 to 0x00100000 Wrote linuxbios table at: 00000530 - 00000e20 checksum 9ef5 Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3 rom_stream: 0xfffc0000 - 0xfffdefff Found ELF candidate at offset 0 header_offset is 0 Try to load at offset 0x0 New segment addr 0x100000 size 0x3dd80 offset 0xc0 filesize 0x13d68 (cleaned up) New segment addr 0x100000 size 0x3dd80 offset 0xc0 filesize 0x13d68 New segment addr 0x13dd80 size 0x48 offset 0x13e40 filesize 0x48 (cleaned up) New segment addr 0x13dd80 size 0x48 offset 0x13e40 filesize 0x48 Dropping non PT_LOAD segment Dropping non PT_LOAD segment Loading Segment: addr: 0x00000000bff80000 memsz: 0x000000000003dd80 filesz: 0x0000000000013d68 Clearing Segment: addr: 0x00000000bff93d68 memsz: 0x000000000002a018 Loading Segment: addr: 0x00000000bffbdd80 memsz: 0x0000000000000048 filesz: 0x0000000000000048 Jumping to boot code at 0x10ef9c FILO version 0.5 (andi@flashgordon) Sun Jun 24 11:47:31 CEST 2007 setup_timers: CPU 2400 MHz menu: hde5:/grub/menu.lst find_ide_controller: found PCI IDE controller 10de:037f prog_if=0x85 find_ide_controller: primary channel: native PCI mode find_ide_controller: cmd_base=0x4000 ctrl_base=0x4070 ide_software_reset: Waiting for ide2 to become ready for reset... ok init_drive: Testing for hde init_drive: Probing for hde init_drive: LBA mode, sectors=268435455 init_drive: LBA48 mode, sectors=488395055 init_drive: Init device params... ok hde: LBA48 250GB: SAMSUNG SP2504C init_drive: Testing for hdf init_drive: Probing for hdf print_status: IDE: status=0x0, err=0x0 init_drive: Testing for hdf init_drive: Probing for hdf print_status: IDE: status=0x0, err=0x0 open_pc_partition: Extended partition at 4 open_pc_partition: cur_part=4 at 132825420 devopen: Partition 5 start 132825483 length 2040192 Mounted ext2fs find_ide_controller: found PCI IDE controller 10de:036e prog_if=0x8a find_ide_controller: primary channel: compatibility mode find_ide_controller: cmd_base=0x1f0 ctrl_base=0x3f4 ide_software_reset: Waiting for ide0 to become ready for reset... ok init_drive: Testing for hda init_drive: Probing for hda print_status: IDE: status=0x51, err=0x4 init_drive: Testing for hda init_drive: Probing for hda hda: ATAPI: Optiarc DVD RW AD-7173A pio_packet: no drq after sending packet print_status: IDE: status=0x51, err=0x64 atapi_request_sense: 70 00 06 00 00 00 00 0a 00 00 00 00 29 00 00 00 00 00 pio_packet: no drq after sending packet print_status: IDE: status=0x51, err=0x24 atapi_request_sense: 70 00 02 00 00 00 00 0a 00 00 00 00 3a 00 00 80 46 d3 atapi_detect_medium: Device reports MEDIUM NOT PRESENT Media detection failed devopen: failed to open ide pio_packet: no drq after sending packet print_status: IDE: status=0x51, err=0x24 atapi_request_sense: 70 00 02 00 00 00 00 0a 00 00 00 00 3a 00 00 80 46 d3 atapi_detect_medium: Device reports MEDIUM NOT PRESENT Media detection failed devopen: failed to open ide pio_packet: no drq after sending packet print_status: IDE: status=0x51, err=0x24 atapi_request_sense: 70 00 02 00 00 00 00 0a 00 00 00 00 3a 00 00 80 47 ae atapi_detect_medium: Device reports MEDIUM NOT PRESENT Media detection failed devopen: failed to open ide pio_packet: no drq after sending packet print_status: IDE: status=0x51, err=0x24 atapi_request_sense: 70 00 02 00 00 00 00 0a 00 00 00 00 3a 00 00 80 47 ae atapi_detect_medium: Device reports MEDIUM NOT PRESENT Media detection failed devopen: failed to open ide pio_packet: no drq after sending packet print_status: IDE: status=0x51, err=0x24 atapi_request_sense: 70 00 02 00 00 00 00 0a 00 00 00 00 3a 00 00 80 47 ae atapi_detect_medium: Device reports MEDIUM NOT PRESENT Media detection failed devopen: failed to open ide pio_packet: no drq after sending packet print_status: IDE: status=0x51, err=0x24 atapi_request_sense: 70 00 02 00 00 00 00 0a 00 00 00 00 3a 00 00 80 48 88 atapi_detect_medium: Device reports MEDIUM NOT PRESENT Media detection failed devopen: failed to open ide pio_packet: no drq after sending packet print_status: IDE: status=0x51, err=0x24 atapi_request_sense: 70 00 02 00 00 00 00 0a 00 00 00 00 3a 00 00 80 48 88 atapi_detect_medium: Device reports MEDIUM NOT PRESENT Media detection failed devopen: failed to open ide pio_packet: no drq after sending packet print_status: IDE: status=0x51, err=0x24 atapi_request_sense: 70 00 02 00 00 00 00 0a 00 00 00 00 3a 00 00 80 48 88 atapi_detect_medium: Device reports MEDIUM NOT PRESENT Media detection failed devopen: failed to open ide pio_packet: no drq after sending packet print_status: IDE: status=0x51, err=0x24 atapi_request_sense: 70 00 02 00 00 00 00 0a 00 00 00 00 3a 00 00 80 49 62 atapi_detect_medium: Device reports MEDIUM NOT PRESENT Media detection failed devopen: failed to open ide pio_packet: no drq after sending packet print_status: IDE: status=0x51, err=0x24 atapi_request_sense: 70 00 02 00 00 00 00 0a 00 00 00 00 3a 00 00 80 49 62 atapi_detect_medium: Device reports MEDIUM NOT PRESENT Media detection failed devopen: failed to open ide pio_packet: no drq after sending packet print_status: IDE: status=0x51, err=0x24 atapi_request_sense: 70 00 02 00 00 00 00 0a 00 00 00 00 3a 00 00 80 49 62 atapi_detect_medium: Device reports MEDIUM NOT PRESENT Media detection failed devopen: failed to open ide devopen: already open Mounted ext2fs devopen: already open Found Linux version 2.6.21 (root@flashgordon) #4 SMP Sun Jun 24 21:35:21 CEST 2007 bzImage. Loading kernel... ok Jumping to entry point...
Hi Andi, On 10.11.2007 20:15, Andreas B. Mundt wrote:
On Sat, Nov 10, 2007 at 05:04:32PM +0100, Carl-Daniel Hailfinger wrote:
Can you try this patch on top of the existing patch? It will give you better debug output for superio config.
......
Can you then post the serial boot log (minicom capture)? It should have a few lines with "TRACE:" in it. Then we can check whether the values are set or not.
here are the results, I have not looked into details yet, but the TRACE is there:
Thanks!
LinuxBIOS-2.0.0_m57sli_Fallback Sat Nov 10 20:04:37 CET 2007 starting... [...]
Setting resources... VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device PCI: 00:18.0 1c0 <- [0x0000001000 - 0x0000004fff] size 0x00004000 gran 0x0c io <node 0 link 0> PCI: 00:18.0 1b8 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x14 prefmem <node 0 link 0> PCI: 00:18.0 1b0 <- [0x00f4000000 - 0x00f62fffff] size 0x02300000 gran 0x14 mem <node 0 link 0> PCI: 00:01.0 14 <- [0x00f6244000 - 0x00f6244fff] size 0x00001000 gran 0x0c mem TRACE: PNP: 002e.1, selecting logical device 01 TRACE: PNP: 002e.1, index 60: writing 03f8 PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io TRACE: PNP: 002e.1, index 70: writing 0004 PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq TRACE: PNP: 002e.4, selecting logical device 04 TRACE: PNP: 002e.4, index 60: writing 0290 PNP: 002e.4 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io TRACE: PNP: 002e.4, index 62: writing 0230 PNP: 002e.4 62 <- [0x0000000230 - 0x0000000237] size 0x00000008 gran 0x03 io TRACE: PNP: 002e.4, index 70: writing 0009 PNP: 002e.4 70 <- [0x0000000009 - 0x0000000009] size 0x00000001 gran 0x00 irq TRACE: PNP: 002e.5, selecting logical device 05 TRACE: PNP: 002e.5, index 60: writing 0060 PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io TRACE: PNP: 002e.5, index 62: writing 0064 PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io TRACE: PNP: 002e.5, index 70: writing 0001 PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq TRACE: PNP: 002e.6, selecting logical device 06 TRACE: PNP: 002e.6, index 70: writing 000c PNP: 002e.6 70 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq PNP: 002e.7 missing set_resources
Boom. The log shows why both parts of the Config.lb patch were ineffective. Can you try the patch below on top of it? This should fix the values for LDN 0x7. If not, please supply a boot log. Index: LinuxBIOSv2/src/superio/ite/it8716f/superio.c =================================================================== --- LinuxBIOSv2/src/superio/ite/it8716f/superio.c (Revision 2953) +++ LinuxBIOSv2/src/superio/ite/it8716f/superio.c (Arbeitskopie) @@ -152,7 +152,7 @@ {&ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7ff, 0}, {0x7ff, 0x4},}, {&ops, IT8716F_KBCM, PNP_IRQ0,}, - // No 7 { 0,}, + {&ops, IT8716F_GPIO,}, {&ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4},}, {&ops, IT8716F_GAME, PNP_IO0, {0x7ff, 0},}, {&ops, IT8716F_IR,}, Index: LinuxBIOSv2/src/superio/ite/it8716f/it8716f.h =================================================================== --- LinuxBIOSv2/src/superio/ite/it8716f/it8716f.h (Revision 2953) +++ LinuxBIOSv2/src/superio/ite/it8716f/it8716f.h (Arbeitskopie) @@ -28,6 +28,7 @@ #define IT8716F_EC 0x04 /* Environment controller */ #define IT8716F_KBCK 0x05 /* Keyboard */ #define IT8716F_KBCM 0x06 /* Mouse */ +#define IT8716F_GPIO 0x07 /* GPIO */ #define IT8716F_MIDI 0x08 /* MIDI port */ #define IT8716F_GAME 0x09 /* GAME port */ #define IT8716F_IR 0x0a /* Consumer IR */ Regards, Carl-Daniel
On Sun, Nov 11, 2007 at 03:52:22PM +0100, Carl-Daniel Hailfinger wrote:
Index: LinuxBIOSv2/src/superio/ite/it8716f/superio.c =================================================================== --- LinuxBIOSv2/src/superio/ite/it8716f/superio.c (Revision 2953) +++ LinuxBIOSv2/src/superio/ite/it8716f/superio.c (Arbeitskopie) @@ -152,7 +152,7 @@ {&ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7ff, 0}, {0x7ff, 0x4},}, {&ops, IT8716F_KBCM, PNP_IRQ0,}, - // No 7 { 0,}, + {&ops, IT8716F_GPIO,}, {&ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4},}, {&ops, IT8716F_GAME, PNP_IO0, {0x7ff, 0},}, {&ops, IT8716F_IR,}, Index: LinuxBIOSv2/src/superio/ite/it8716f/it8716f.h =================================================================== --- LinuxBIOSv2/src/superio/ite/it8716f/it8716f.h (Revision 2953) +++ LinuxBIOSv2/src/superio/ite/it8716f/it8716f.h (Arbeitskopie) @@ -28,6 +28,7 @@ #define IT8716F_EC 0x04 /* Environment controller */ #define IT8716F_KBCK 0x05 /* Keyboard */ #define IT8716F_KBCM 0x06 /* Mouse */ +#define IT8716F_GPIO 0x07 /* GPIO */ #define IT8716F_MIDI 0x08 /* MIDI port */ #define IT8716F_GAME 0x09 /* GAME port */ #define IT8716F_IR 0x0a /* Consumer IR */
Indeed, this is a bug in the code. If it works and if you add a Signed-off-by line: Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
PNP: 002e.7 missing set_resources
Boom. The log shows why both parts of the Config.lb patch were ineffective. Can you try the patch below on top of it? This should fix the values for LDN 0x7. If not, please supply a boot log.
Hi Carl-Daniel, here is the superiotool diff: $ diff -u andi_LB andi_LB_patch --- andi_LB 2007-11-08 18:51:40.000000000 +0100 +++ andi_LB_patch 2007-11-11 18:15:33.000000000 +0100 @@ -43,7 +43,7 @@ def 00 0c 02 00 LDN 0x07 idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd -val 00 00 00 00 00 00 1f 00 00 00 00 00 00 00 01 20 38 00 00 00 00 00 00 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 32 00 +val 00 43 20 00 81 00 1f 00 00 08 00 00 00 00 00 00 38 00 00 00 00 00 00 00 00 00 00 00 01 00 00 43 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 00 00 32 00 def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 20 38 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 LDN 0x08 idx 30 60 61 70 f0 Find part of the serial console boot log below for completeness. And: For the first time I was able to write with flashrom and LB: $flashrom -Vv --write linuxbios.rom Calibrating delay loop... 662M loops per second. OK. Found canidate at: 00000530-00000e70 Found LinuxBIOS table at 0x00000530. LinuxBIOS table found at 0x2b57030a4530. LinuxBIOS header(24) checksum: e613 table(2368) checksum: 7ef0 entries: 14 Vendor ID: GIGABYTE, part ID: m57sli Found chipset "NVIDIA MCP55", enabling flash write... OK. ..... SST49LF040B found at physical address 0xfff80000. Flash part is SST49LF040B (512 KB). LinuxBIOS last image size (not ROM size) is 4096 bytes. Manufacturer: GIGABYTE Mainboard ID: m57sli This firmware image matches this motherboard. Programming page: 0007 at address: 0x00070000 Verifying flash... VERIFIED. Regards, Andi TRACE: PNP: 002e.7, selecting logical device 07 TRACE: PNP: 002e.7, index 25: writing 0000 PNP: 002e.7 25 <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 irq TRACE: PNP: 002e.7, index 26: writing 0043 PNP: 002e.7 26 <- [0x0000000043 - 0x0000000042] size 0x00000000 gran 0x00 irq TRACE: PNP: 002e.7, index 27: writing 0020 PNP: 002e.7 27 <- [0x0000000020 - 0x000000001f] size 0x00000000 gran 0x00 irq TRACE: PNP: 002e.7, index 29: writing 0081 PNP: 002e.7 29 <- [0x0000000081 - 0x0000000080] size 0x00000000 gran 0x00 irq TRACE: PNP: 002e.7, index 62: writing 0800 PNP: 002e.7 62 <- [0x0000000800 - 0x00000007ff] size 0x00000000 gran 0x00 io TRACE: PNP: 002e.7, index 72: writing 0000 PNP: 002e.7 72 <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 irq TRACE: PNP: 002e.7, index b8: writing 0000 PNP: 002e.7 b8 <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 irq TRACE: PNP: 002e.7, index bc: writing 0001 PNP: 002e.7 bc <- [0x0000000001 - 0x0000000000] size 0x00000000 gran 0x00 irq TRACE: PNP: 002e.7, index c1: writing 0043 PNP: 002e.7 c1 <- [0x0000000043 - 0x0000000042] size 0x00000000 gran 0x00 irq TRACE: PNP: 002e.7, index c2: writing 0020 PNP: 002e.7 c2 <- [0x0000000020 - 0x000000001f] size 0x00000000 gran 0x00 irq TRACE: PNP: 002e.7, index c9: writing 0000 PNP: 002e.7 c9 <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 irq TRACE: PNP: 002e.7, index f6: writing 0028 PNP: 002e.7 f6 <- [0x0000000028 - 0x0000000027] size 0x00000000 gran 0x00 irq PCI: 00:01.1 10 <- [0x0000003c00 - 0x0000003c3f] size 0x00000040 gran 0x06 io PCI: 00:01.1 20 <- [0x0000003c40 - 0x0000003c7f] size 0x00000040 gran 0x06 io PCI: 00:01.1 24 <- [0x0000003c80 - 0x0000003cbf] size 0x00000040 gran 0x06 io PCI: 00:01.1 60 <- [0x0000003000 - 0x00000030ff] size 0x00000100 gran 0x08 io PCI: 00:01.1 64 <- [0x0000003400 - 0x00000034ff] size 0x00000100 gran 0x08 io PCI: 00:01.1 68 <- [0x0000003800 - 0x00000038ff] size 0x00000100 gran 0x08 io PCI: 00:01.3 10 <- [0x00f6200000 - 0x00f623ffff] size 0x00040000 gran 0x12 mem PCI: 00:02.0 10 <- [0x00f6245000 - 0x00f6245fff] size 0x00001000 gran 0x0c mem PCI: 00:02.1 10 <- [0x00f624a000 - 0x00f624a0ff] size 0x00000100 gran 0x08 mem PCI: 00:04.0 20 <- [0x0000003cc0 - 0x0000003ccf] size 0x00000010 gran 0x04 io PCI: 00:05.0 10 <- [0x0000004000 - 0x0000004007] size 0x00000008 gran 0x03 io PCI: 00:05.0 14 <- [0x0000004070 - 0x0000004073] size 0x00000004 gran 0x02 io PCI: 00:05.0 18 <- [0x0000004010 - 0x0000004017] size 0x00000008 gran 0x03 io PCI: 00:05.0 1c <- [0x0000004080 - 0x0000004083] size 0x00000004 gran 0x02 io PCI: 00:05.0 20 <- [0x0000003cd0 - 0x0000003cdf] size 0x00000010 gran 0x04 io PCI: 00:05.0 24 <- [0x00f6246000 - 0x00f6246fff] size 0x00001000 gran 0x0c mem PCI: 00:05.1 10 <- [0x0000004020 - 0x0000004027] size 0x00000008 gran 0x03 io PCI: 00:05.1 14 <- [0x0000004090 - 0x0000004093] size 0x00000004 gran 0x02 io PCI: 00:05.1 18 <- [0x0000004030 - 0x0000004037] size 0x00000008 gran 0x03 io PCI: 00:05.1 1c <- [0x00000040a0 - 0x00000040a3] size 0x00000004 gran 0x02 io PCI: 00:05.1 20 <- [0x0000003ce0 - 0x0000003cef] size 0x00000010 gran 0x04 io PCI: 00:05.1 24 <- [0x00f6247000 - 0x00f6247fff] size 0x00001000 gran 0x0c mem PCI: 00:05.2 10 <- [0x0000004040 - 0x0000004047] size 0x00000008 gran 0x03 io PCI: 00:05.2 14 <- [0x00000040b0 - 0x00000040b3] size 0x00000004 gran 0x02 io PCI: 00:05.2 18 <- [0x0000004050 - 0x0000004057] size 0x00000008 gran 0x03 io PCI: 00:05.2 1c <- [0x00000040c0 - 0x00000040c3] size 0x00000004 gran 0x02 io PCI: 00:05.2 20 <- [0x0000003cf0 - 0x0000003cff] size 0x00000010 gran 0x04 io PCI: 00:05.2 24 <- [0x00f6248000 - 0x00f6248fff] size 0x00001000 gran 0x0c mem PCI: 00:06.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io PCI: 00:06.0 20 <- [0x00f6100000 - 0x00f61fffff] size 0x00100000 gran 0x14 bus 01 mem PCI: 01:07.0 10 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io PCI: 01:07.1 10 <- [0x0000001020 - 0x0000001027] size 0x00000008 gran 0x03 io PCI: 01:0a.0 10 <- [0x00f6104000 - 0x00f61047ff] size 0x00000800 gran 0x0b mem PCI: 01:0a.0 14 <- [0x00f6100000 - 0x00f6103fff] size 0x00004000 gran 0x0e mem PCI: 00:06.1 10 <- [0x00f6240000 - 0x00f6243fff] size 0x00004000 gran 0x0e mem PCI: 00:08.0 10 <- [0x00f6249000 - 0x00f6249fff] size 0x00001000 gran 0x0c mem PCI: 00:08.0 14 <- [0x0000004060 - 0x0000004067] size 0x00000008 gran 0x03 io PCI: 00:08.0 18 <- [0x00f624b000 - 0x00f624b0ff] size 0x00000100 gran 0x08 mem PCI: 00:08.0 1c <- [0x00f624c000 - 0x00f624c00f] size 0x00000010 gran 0x04 mem PCI: 00:0f.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 07 io PCI: 00:0f.0 24 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x14 bus 07 prefmem PCI: 00:0f.0 20 <- [0x00f4000000 - 0x00f60fffff] size 0x02100000 gran 0x14 bus 07 mem PCI: 07:00.0 10 <- [0x00f4000000 - 0x00f4ffffff] size 0x01000000 gran 0x18 mem PCI: 07:00.0 14 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem64 PCI: 07:00.0 1c <- [0x00f5000000 - 0x00f5ffffff] size 0x01000000 gran 0x18 mem64 PCI: 07:00.0 24 <- [0x0000002000 - 0x000000207f] size 0x00000080 gran 0x07 io PCI: 07:00.0 30 <- [0x00f6000000 - 0x00f601ffff] size 0x00020000 gran 0x11 romem PCI: 00:18.3 94 <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x1a mem <gart> Done setting resources.
On Sunday 11 November 2007 15:52, Carl-Daniel Hailfinger wrote:
Boom. The log shows why both parts of the Config.lb patch were ineffective. Can you try the patch below on top of it? This should fix the values for LDN 0x7. If not, please supply a boot log.
Index: LinuxBIOSv2/src/superio/ite/it8716f/superio.c =================================================================== --- LinuxBIOSv2/src/superio/ite/it8716f/superio.c (Revision 2953) +++ LinuxBIOSv2/src/superio/ite/it8716f/superio.c (Arbeitskopie) @@ -152,7 +152,7 @@ {&ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7ff, 0}, {0x7ff, 0x4},}, {&ops, IT8716F_KBCM, PNP_IRQ0,}, - // No 7 { 0,}, + {&ops, IT8716F_GPIO,}, {&ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4},}, {&ops, IT8716F_GAME, PNP_IO0, {0x7ff, 0},}, {&ops, IT8716F_IR,}, Index: LinuxBIOSv2/src/superio/ite/it8716f/it8716f.h =================================================================== --- LinuxBIOSv2/src/superio/ite/it8716f/it8716f.h (Revision 2953) +++ LinuxBIOSv2/src/superio/ite/it8716f/it8716f.h (Arbeitskopie) @@ -28,6 +28,7 @@ #define IT8716F_EC 0x04 /* Environment controller */ #define IT8716F_KBCK 0x05 /* Keyboard */ #define IT8716F_KBCM 0x06 /* Mouse */ +#define IT8716F_GPIO 0x07 /* GPIO */ #define IT8716F_MIDI 0x08 /* MIDI port */ #define IT8716F_GAME 0x09 /* GAME port */ #define IT8716F_IR 0x0a /* Consumer IR */
Regards, Carl-Daniel
Obviously needed to get the initial patch working. Acked-by: Torsten Duwe <duwe@lst.de>
Torsten Duwe wrote:
On Sunday 11 November 2007 15:52, Carl-Daniel Hailfinger wrote:
Boom. The log shows why both parts of the Config.lb patch were ineffective. Can you try the patch below on top of it? This should fix the values for LDN 0x7. If not, please supply a boot log.
Index: LinuxBIOSv2/src/superio/ite/it8716f/superio.c =================================================================== --- LinuxBIOSv2/src/superio/ite/it8716f/superio.c (Revision 2953) +++ LinuxBIOSv2/src/superio/ite/it8716f/superio.c (Arbeitskopie) @@ -152,7 +152,7 @@ {&ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7ff, 0}, {0x7ff, 0x4},}, {&ops, IT8716F_KBCM, PNP_IRQ0,}, - // No 7 { 0,}, + {&ops, IT8716F_GPIO,}, {&ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4},}, {&ops, IT8716F_GAME, PNP_IO0, {0x7ff, 0},}, {&ops, IT8716F_IR,}, Index: LinuxBIOSv2/src/superio/ite/it8716f/it8716f.h =================================================================== --- LinuxBIOSv2/src/superio/ite/it8716f/it8716f.h (Revision 2953) +++ LinuxBIOSv2/src/superio/ite/it8716f/it8716f.h (Arbeitskopie) @@ -28,6 +28,7 @@ #define IT8716F_EC 0x04 /* Environment controller */ #define IT8716F_KBCK 0x05 /* Keyboard */ #define IT8716F_KBCM 0x06 /* Mouse */ +#define IT8716F_GPIO 0x07 /* GPIO */ #define IT8716F_MIDI 0x08 /* MIDI port */ #define IT8716F_GAME 0x09 /* GAME port */ #define IT8716F_IR 0x0a /* Consumer IR */
Regards, Carl-Daniel
Obviously needed to get the initial patch working.
Acked-by: Torsten Duwe <duwe@lst.de>
Still need a signed-off-by line, please. Thanks, good to hear this is somewhat working! Does write work as well? -Corey
On Monday 12 November 2007, Corey Osgood wrote:
Still need a signed-off-by line, please. Thanks, good to hear this is somewhat working! Does write work as well?
"Writing" always worked for me, in a sense that I could zero single bits; this much I verified from the read-back broken image. Then I tried to erase the chip just to find that this had little effect. Could this explain why Ward could successfully reflash one in a while? Torsten
On 12.11.2007 12:29, Torsten Duwe wrote:
On Monday 12 November 2007, Corey Osgood wrote:
Still need a signed-off-by line, please. Thanks, good to hear this is somewhat working! Does write work as well?
"Writing" always worked for me, in a sense that I could zero single bits; this much I verified from the read-back broken image. Then I tried to erase the chip just to find that this had little effect. Could this explain why Ward could successfully reflash one in a while?
That, or the fact that a few lines connected to the flash chip were floating, resulting in unpredictable behaviour. Carl-Daniel
On 12.11.2007 01:19, Torsten Duwe wrote:
On Sunday 11 November 2007 15:52, Carl-Daniel Hailfinger wrote:
Boom. The log shows why both parts of the Config.lb patch were ineffective. Can you try the patch below on top of it? This should fix the values for LDN 0x7. If not, please supply a boot log.
Index: LinuxBIOSv2/src/superio/ite/it8716f/superio.c =================================================================== --- LinuxBIOSv2/src/superio/ite/it8716f/superio.c (Revision 2953) +++ LinuxBIOSv2/src/superio/ite/it8716f/superio.c (Arbeitskopie) @@ -152,7 +152,7 @@ {&ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7ff, 0}, {0x7ff, 0x4},}, {&ops, IT8716F_KBCM, PNP_IRQ0,}, - // No 7 { 0,}, + {&ops, IT8716F_GPIO,}, {&ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4},}, {&ops, IT8716F_GAME, PNP_IO0, {0x7ff, 0},}, {&ops, IT8716F_IR,}, Index: LinuxBIOSv2/src/superio/ite/it8716f/it8716f.h =================================================================== --- LinuxBIOSv2/src/superio/ite/it8716f/it8716f.h (Revision 2953) +++ LinuxBIOSv2/src/superio/ite/it8716f/it8716f.h (Arbeitskopie) @@ -28,6 +28,7 @@ #define IT8716F_EC 0x04 /* Environment controller */ #define IT8716F_KBCK 0x05 /* Keyboard */ #define IT8716F_KBCM 0x06 /* Mouse */ +#define IT8716F_GPIO 0x07 /* GPIO */ #define IT8716F_MIDI 0x08 /* MIDI port */ #define IT8716F_GAME 0x09 /* GAME port */ #define IT8716F_IR 0x0a /* Consumer IR */
Regards, Carl-Daniel
Obviously needed to get the initial patch working.
Acked-by: Torsten Duwe <duwe@lst.de>
Thanks, committed in r2955. Torsten, Andi, thanks for testing! Regards, Carl-Daniel
On Saturday 10 November 2007 00:48, Carl-Daniel Hailfinger wrote:
Hi Ward,
On 08.11.2007 16:51, Carl-Daniel Hailfinger wrote:
On 08.11.2007 16:22, Ward Vandewege wrote:
On Thu, Nov 08, 2007 at 02:05:16PM -0000, LinuxBIOS wrote:
#87: flashrom issues on m57sli-s4
I need superiotool output for a board with parallel flash running under LB. NOW.
LinuxBIOS: http://ward.vandewege.net/superiotool-lb.m57sli.dump Proprietary BIOS: http://ward.vandewege.net/superiotool-prop.m57sli.dump
Can you retest with the following patch applied? Thanks.
The "wtf?!?" comment is intentional and designates another bug. However, I have no idea which device number we need here.
Regards, Carl-Daniel
Try to fix a few loose ends on the GA-M57SLI Super I/O GPIO configuration.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Flash erase on my board was failing reliably. Now it works! Acked-by: Torsten Duwe <duwe@lst.de>
---
Index: LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb =================================================================== --- LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb (Revision 2953) +++ LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb (Arbeitskopie) @@ -239,7 +239,9 @@ device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/ite/it8716f - device pnp 2e.0 off # Floppy + device pnp 2e.0 off # Floppy and anyLDN + irq 0x23 = 0x11 # watchdog from CLKIN, CLKIN = 24 MHz + #0x24 = 0x1a # serial flash (SPI only) io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 @@ -269,6 +271,30 @@ device pnp 2e.6 on # Mouse irq 0x70 = 12 end + device pnp 2e.7 on # GPIO, SPI flash + irq 0x25 = 0x0 # pin 84 is not GP10 + irq 0x26 = 0x43 # pin 21 is GP26, pin 26 is GP21, pin 27 is GP20 + irq 0x27 = 0x20 # pin 13 is GP35 + #0x28 = 0x0 # pin 70 is not GP46 + irq 0x29 = 0x81 # pin 6,3,128,127,126 is GP63,64,65,66,67 + #0x2c = 0x1f # Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V + io 0x62 = 0x800 # simple i/o base + #io 0x64 = 0x820 # serial flash io (SPI only) + #0x71 = 0x1 # watch dog force timeout (parallel flash only) + irq 0x72 = 0x0 # no WDT interrupt + irq 0xb8 = 0x0 # GPIO pin set 1 disable internal pullup + irq 0xbc = 0x01 # GPIO pin set 5 enable internal pullup + #0xc0 = 0x0 # SIO pin set 1 alternate function + irq 0xc1 = 0x43 # SIO pin set 2 mixed function + irq 0xc2 = 0x20 # SIO pin set 3 mixed function + #0xc3 = 0x0 # SIO pin set 4 alternate function + #0xc8 = 0x0 # SIO pin set 1 input mode + irq 0xc9 = 0x0 # SIO pin set 2 mixed input/output mode + #0xcb = 0x0 # SIO pin set 4 input mode + #0xf0 = 0x10 # generate SMI# on EC IRQ + #0xf1 = 0x40 # SMI# level trigger + irq 0xf6 = 0x28 # HWMON alert beep pin location + end device pnp 2e.8 off # MIDI io 0x60 = 0x300 irq 0x70 = 10 @@ -305,6 +331,7 @@ device i2c 57 on end end end # SM +#wtf?!? we already have device pci 1.1 in the section above device pci 1.1 on # SM 1 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? # chip drivers/generic/generic #PCIXA Slot1
Torsten Duwe wrote:
On Saturday 10 November 2007 00:48, Carl-Daniel Hailfinger wrote:
Hi Ward,
On 08.11.2007 16:51, Carl-Daniel Hailfinger wrote:
On 08.11.2007 16:22, Ward Vandewege wrote:
On Thu, Nov 08, 2007 at 02:05:16PM -0000, LinuxBIOS wrote:
#87: flashrom issues on m57sli-s4
I need superiotool output for a board with parallel flash running under LB. NOW.
LinuxBIOS: http://ward.vandewege.net/superiotool-lb.m57sli.dump Proprietary BIOS: http://ward.vandewege.net/superiotool-prop.m57sli.dump
Can you retest with the following patch applied? Thanks.
The "wtf?!?" comment is intentional and designates another bug. However, I have no idea which device number we need here.
Regards, Carl-Daniel
Try to fix a few loose ends on the GA-M57SLI Super I/O GPIO configuration.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Flash erase on my board was failing reliably. Now it works! Acked-by: Torsten Duwe <duwe@lst.de>
---
Index: LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb =================================================================== --- LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb (Revision 2953) +++ LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb (Arbeitskopie) @@ -239,7 +239,9 @@ device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/ite/it8716f - device pnp 2e.0 off # Floppy + device pnp 2e.0 off # Floppy and anyLDN + irq 0x23 = 0x11 # watchdog from CLKIN, CLKIN = 24 MHz + #0x24 = 0x1a # serial flash (SPI only) io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 @@ -269,6 +271,30 @@ device pnp 2e.6 on # Mouse irq 0x70 = 12 end + device pnp 2e.7 on # GPIO, SPI flash + irq 0x25 = 0x0 # pin 84 is not GP10 + irq 0x26 = 0x43 # pin 21 is GP26, pin 26 is GP21, pin 27 is GP20 + irq 0x27 = 0x20 # pin 13 is GP35 + #0x28 = 0x0 # pin 70 is not GP46 + irq 0x29 = 0x81 # pin 6,3,128,127,126 is GP63,64,65,66,67 + #0x2c = 0x1f # Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V + io 0x62 = 0x800 # simple i/o base + #io 0x64 = 0x820 # serial flash io (SPI only) + #0x71 = 0x1 # watch dog force timeout (parallel flash only) + irq 0x72 = 0x0 # no WDT interrupt + irq 0xb8 = 0x0 # GPIO pin set 1 disable internal pullup + irq 0xbc = 0x01 # GPIO pin set 5 enable internal pullup + #0xc0 = 0x0 # SIO pin set 1 alternate function + irq 0xc1 = 0x43 # SIO pin set 2 mixed function + irq 0xc2 = 0x20 # SIO pin set 3 mixed function + #0xc3 = 0x0 # SIO pin set 4 alternate function + #0xc8 = 0x0 # SIO pin set 1 input mode + irq 0xc9 = 0x0 # SIO pin set 2 mixed input/output mode + #0xcb = 0x0 # SIO pin set 4 input mode + #0xf0 = 0x10 # generate SMI# on EC IRQ + #0xf1 = 0x40 # SMI# level trigger + irq 0xf6 = 0x28 # HWMON alert beep pin location + end device pnp 2e.8 off # MIDI io 0x60 = 0x300 irq 0x70 = 10 @@ -305,6 +331,7 @@ device i2c 57 on end end end # SM +#wtf?!? we already have device pci 1.1 in the section above device pci 1.1 on # SM 1 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? # chip drivers/generic/generic #PCIXA Slot1
r2954, with a desperate attempt at trying to fit comments into 80 char lines. Thanks! -Corey
On 08.11.2007 15:05, LinuxBIOS wrote:
#87: flashrom issues on m57sli-s4 -------------------------+-------------------------------------------------- Reporter: ward | Owner: hailfinger Type: defect | Status: new Priority: major | Milestone: Component: flashrom | Version: v2 Resolution: | Keywords: Dependencies: | Patchstatus: there is no patch -------------------------+-------------------------------------------------- Changes (by hailfinger):
* owner: somebody => hailfinger
Comment:
I need superiotool output for a board with parallel flash running under LB. NOW.
AFAICS the flash configuration is totally botched on LB with floating GPIOs, wrong timing etc.
I have a patch pending which will solve the flashing problem on all M57SLI boards, but I refuse to send it to the list before I have superiotool output to verify.
Since trac seems to be down, this message goes to the list: Flashing parallel flash is fixed in r2955. To be able to autodetect presence of serial flash, I'd like full superiotool output for * board with parallel flash * board with serial flash both running LinuxBIOS r2955 or later. I hope to find a bit which differs in superio configuration that can be used to select the right code path for enabling SPI flash (decode and flash functionality). Regards, Carl-Daniel
Am Montag, 12. November 2007 12:30:33 schrieb Carl-Daniel Hailfinger:
On 08.11.2007 15:05, LinuxBIOS wrote:
#87: flashrom issues on m57sli-s4 -------------------------+----------------------------------------------- --- Reporter: ward | Owner: hailfinger Type: defect | Status: new Priority: major | Milestone: Component: flashrom | Version: v2 Resolution: | Keywords: Dependencies: | Patchstatus: there is no patch -------------------------+----------------------------------------------- --- Changes (by hailfinger):
* owner: somebody => hailfinger
Comment:
I need superiotool output for a board with parallel flash running under LB. NOW.
AFAICS the flash configuration is totally botched on LB with floating GPIOs, wrong timing etc.
I have a patch pending which will solve the flashing problem on all M57SLI boards, but I refuse to send it to the list before I have superiotool output to verify.
Since trac seems to be down, this message goes to the list:
Flashing parallel flash is fixed in r2955.
To be able to autodetect presence of serial flash, I'd like full superiotool output for * board with parallel flash * board with serial flash here is the output form superiotool for a board with serial flash. flashrom under lb fails on detecting the SPI part. (sry, but i don't know the detailed error message any more.)
both running LinuxBIOS r2955 or later. I hope to find a bit which differs in superio configuration that can be used to select the right code path for enabling SPI flash (decode and flash functionality).
Regards, Carl-Daniel regards, harald
Am Montag, 12. November 2007 22:41:05 schrieb Harald Gutmann:
To be able to autodetect presence of serial flash, I'd like full superiotool output for * board with parallel flash * board with serial flash
here is the output form superiotool for a board with serial flash. flashrom under lb fails on detecting the SPI part. (sry, but i don't know the detailed error message any more.) sry, but i hit the wron button, so i attach the necessary informations here.
regards, harald
On 12.11.2007 22:45, Harald Gutmann wrote:
Am Montag, 12. November 2007 22:41:05 schrieb Harald Gutmann:
To be able to autodetect presence of serial flash, I'd like full superiotool output for * board with parallel flash * board with serial flash
here is the output form superiotool for a board with serial flash. flashrom under lb fails on detecting the SPI part. (sry, but i don't know the detailed error message any more.)
sry, but i hit the wron button, so i attach the necessary informations here.
Thanks! Found ITE IT8716F (id=0x8716, rev=0x0) at 0x2e Register dump: idx 07 20 21 22 23 24 2b -val 01 0a +val 0a 87 16 00 11 1a 00 def NA 87 16 01 00 00 00 23: Clock Selection 24: Software Suspend and Flash LDN 0x00 idx 30 60 61 70 74 f0 f1 -val 00 00 +val 01 03 f0 06 02 00 80 def 00 03 f0 06 02 00 00 30: FDC Enable f1: FDC Special Config 2 LDN 0x02 idx 30 60 61 70 f0 f1 f2 f3 -val 02 f8 03 +val 00 00 00 00 00 50 00 7f def 00 02 f8 03 00 50 00 7f 60+61: Serial Port 2 Base Addr 70: Serial Port 2 IRQ LDN 0x03 idx 30 60 61 62 63 70 74 f0 -val 00 07 78 +val 01 03 78 00 00 07 04 08 def 00 03 78 07 78 07 03 03 30: Parallel Port Enable 62+63: Parallel Port Secondary Base Addr LDN 0x04 idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 -val 02 30 09 +val 01 02 90 00 00 00 80 00 0a 00 81 00 1d def 00 02 90 02 30 09 00 00 00 00 00 NA NA 62+63: PME Direct Access Base Addr 70: Environment Controller IRQ LDN 0x05 idx 30 60 61 62 63 70 71 f0 -val 48 +val 01 00 60 00 64 01 02 68 def 01 00 60 00 64 01 02 00 f0: KBC Special Config LDN 0x06 idx 30 70 71 f0 -val 01 0c +val 00 00 02 00 def 00 0c 02 00 30: KBC Mouse Enable 70: KBC Mouse IRQ LDN 0x07 idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd -val 00 00 01 00 00 00 +val 00 43 20 00 81 00 1f 00 00 08 00 08 20 00 00 00 38 00 00 00 00 00 00 00 00 00 00 00 01 00 00 43 20 00 00 00 40 00 00 00 00 00 00 00 00 10 40 00 00 00 00 28 00 00 00 00 00 32 00 def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 20 38 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 64+65: Serial Flash Base Addr 71: Watch Dog Timer c9: Simple I/O Set 2 f0+f1: SMI Control We have to change * NOLDN idx 0x24 (Flash) * LDN 0x07 idx 0x64+0x65 (Flash), 0xc9 (Simple I/O) The rest of the differences is either "don't care" at the moment or changing is actively harmful. If we ever decide to support automatic fan control and stuff like that, we have to revisit LDN 0x04. If we ever decide to NOT support EPP/ECP parallel port modes, we have to revisit LDN 0x03. Regards, Carl-Daniel Try this patch: Autodetect presence of serial flash and set up the board accordingly. This enables us to have only one configuration and one set of code for all revisions of the Gigabyte GA-M57SLI-S2. Remaining issues: Fan/environment control Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> --- Index: LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb =================================================================== --- LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb (Revision 2955) +++ LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb (Arbeitskopie) @@ -310,7 +310,7 @@ # SIO pin set 1 input mode #irq 0xc8 = 0x0 # SIO pin set 2 mixed input/output mode - irq 0xc9 = 0x0 + irq 0xc9 = 0x40 # SIO pin set 4 input mode #irq 0xcb = 0x0 # Generate SMI# on EC IRQ Index: LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c =================================================================== --- LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c (Revision 2955) +++ LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c (Arbeitskopie) @@ -93,6 +93,7 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO) #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" @@ -265,13 +266,27 @@ int needs_reset = 0; unsigned bsp_apicid = 0; + uint8_t tmp = 0; if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x23, 1); + /* The following line will set CLKIN to 24 MHz */ + pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 1); + tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP); + /* Is serial flash enabled? Then enable writing to serial flash. */ + if (tmp & 0x0e) { + pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP, tmp | 0x10); + pnp_set_logical_device(GPIO_DEV); + /* Set Serial Flash interface to 0x0820 */ + pnp_write_config(GPIO_DEV, 0x64, 0x08); + pnp_write_config(GPIO_DEV, 0x65, 0x20); + /* We can get away with not resetting the logical device because + * it8716f_enable_dev(SERIAL_DEV, TTYS0_BASE) will do that. + */ + } it8716f_enable_dev(SERIAL_DEV, TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV);
Am Dienstag, 13. November 2007 02:27:21 schrieb Carl-Daniel Hailfinger:
Found ITE IT8716F (id=0x8716, rev=0x0) at 0x2e Register dump: idx 07 20 21 22 23 24 2b -val 01 0a +val 0a 87 16 00 11 1a 00 def NA 87 16 01 00 00 00 23: Clock Selection 24: Software Suspend and Flash
LDN 0x00 idx 30 60 61 70 74 f0 f1 -val 00 00 +val 01 03 f0 06 02 00 80 def 00 03 f0 06 02 00 00 30: FDC Enable f1: FDC Special Config 2
LDN 0x02 idx 30 60 61 70 f0 f1 f2 f3 -val 02 f8 03 +val 00 00 00 00 00 50 00 7f def 00 02 f8 03 00 50 00 7f 60+61: Serial Port 2 Base Addr 70: Serial Port 2 IRQ
LDN 0x03 idx 30 60 61 62 63 70 74 f0 -val 00 07 78 +val 01 03 78 00 00 07 04 08 def 00 03 78 07 78 07 03 03 30: Parallel Port Enable 62+63: Parallel Port Secondary Base Addr
LDN 0x04 idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 -val 02 30 09 +val 01 02 90 00 00 00 80 00 0a 00 81 00 1d def 00 02 90 02 30 09 00 00 00 00 00 NA NA 62+63: PME Direct Access Base Addr 70: Environment Controller IRQ
LDN 0x05 idx 30 60 61 62 63 70 71 f0 -val 48 +val 01 00 60 00 64 01 02 68 def 01 00 60 00 64 01 02 00 f0: KBC Special Config
LDN 0x06 idx 30 70 71 f0 -val 01 0c +val 00 00 02 00 def 00 0c 02 00 30: KBC Mouse Enable 70: KBC Mouse IRQ
LDN 0x07 idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd -val 00 00 01 00 00 00 +val 00 43 20 00 81 00 1f 00 00 08 00 08 20 00 00 00 38 00 00 00 00 00 00 00 00 00 00 00 01 00 00 43 20 00 00 00 40 00 00 00 00 00 00 00 00 10 40 00 00 00 00 28 00 00 00 00 00 32 00 def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 20 38 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 64+65: Serial Flash Base Addr 71: Watch Dog Timer c9: Simple I/O Set 2 f0+f1: SMI Control
We have to change * NOLDN idx 0x24 (Flash) * LDN 0x07 idx 0x64+0x65 (Flash), 0xc9 (Simple I/O) The rest of the differences is either "don't care" at the moment or changing is actively harmful. If we ever decide to support automatic fan control and stuff like that, we have to revisit LDN 0x04. If we ever decide to NOT support EPP/ECP parallel port modes, we have to revisit LDN 0x03.
Regards, Carl-Daniel
Try this patch:
done, but flashrom fails. here is a diff from the lb-superiotool output from rev2955 to the superiotool output from rev2958 with your patch. --- superiotool.lb-rev2955 2007-11-13 15:19:15.000000000 +0100 +++ superiotool.lb-rev2958-patched 2007-11-13 15:18:47.000000000 +0100 @@ -34,7 +34,7 @@ def 00 0c 02 00 LDN 0x07 idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd -val 00 43 20 00 81 00 1f 00 00 08 00 00 00 00 01 00 38 00 00 00 00 00 00 00 00 00 00 00 01 00 00 43 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 00 00 32 00 +val 00 43 20 00 81 00 1f 00 00 08 00 00 00 00 00 00 38 00 00 00 00 00 00 00 00 00 00 00 01 00 00 43 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 00 00 32 00 def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 20 38 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 LDN 0x08 idx 30 60 61 70 f0 here is the shortened output from flashrom in rev2958: benchvice flashrom # ./flashrom -m gigabyte:m57sli -V Calibrating delay loop... 1394M loops per second. OK. Found canidate at: 00000530-00000e44 Found LinuxBIOS table at 0x00000530. LinuxBIOS table found at 0x2aba65d7c530. LinuxBIOS header(24) checksum: 5d9c table(2324) checksum: 0794 entries: 14 Vendor ID: GIGABYTE, part ID: m57sli Overwritten by command line, vendor ID: gigabyte, part ID: m57sli. Found chipset "NVIDIA MCP55", enabling flash write... OK. Found board "GIGABYTE GA-M57SLI-S4": enabling flash write... Serial flash segment 0xfffe0000-0xffffffff enabled Serial flash segment 0x000e0000-0x000fffff enabled Serial flash segment 0xffee0000-0xffefffff disabled Serial flash segment 0xfff80000-0xfffeffff enabled LPC write to serial flash disabled serial flash pin 29 FAILED! Probing for MX25L4005, 512 KB generic_spi_command called, but no SPI chipset detected No EEPROM/flash device found. regards, harald
On 13.11.2007 15:27, Harald Gutmann wrote:
Am Dienstag, 13. November 2007 02:27:21 schrieb Carl-Daniel Hailfinger:
We have to change * NOLDN idx 0x24 (Flash) * LDN 0x07 idx 0x64+0x65 (Flash), 0xc9 (Simple I/O) The rest of the differences is either "don't care" at the moment or changing is actively harmful. If we ever decide to support automatic fan control and stuff like that, we have to revisit LDN 0x04. If we ever decide to NOT support EPP/ECP parallel port modes, we have to revisit LDN 0x03.
Try this patch:
done, but flashrom fails. here is a diff from the lb-superiotool output from rev2955 to the superiotool output from rev2958 with your patch.
Misunderstanding? I wanted you to boot r2958 with my patch. Superiotool/Flashrom version is unimportant and will not cause differences. Regards, Carl-Daniel
Am Dienstag, 13. November 2007 16:08:01 schrieb Carl-Daniel Hailfinger:
On 13.11.2007 15:27, Harald Gutmann wrote:
Am Dienstag, 13. November 2007 02:27:21 schrieb Carl-Daniel Hailfinger:
We have to change * NOLDN idx 0x24 (Flash) * LDN 0x07 idx 0x64+0x65 (Flash), 0xc9 (Simple I/O) The rest of the differences is either "don't care" at the moment or changing is actively harmful. If we ever decide to support automatic fan control and stuff like that, we have to revisit LDN 0x04. If we ever decide to NOT support EPP/ECP parallel port modes, we have to revisit LDN 0x03.
Try this patch:
done, but flashrom fails. here is a diff from the lb-superiotool output from rev2955 to the "rev2955" from the linuxbios image, without your patch.
superiotool output from rev2958 with your patch. "rev2958 with your patch" <- from linuxbios image with the last patch from this thread.
Misunderstanding? I wanted you to boot r2958 with my patch. i don't think so. Superiotool/Flashrom version is unimportant and will not cause differences. yes, i know.
Regards, Carl-Daniel regards, harald
On 13.11.2007 16:36, Harald Gutmann wrote:
Am Dienstag, 13. November 2007 16:08:01 schrieb Carl-Daniel Hailfinger:
On 13.11.2007 15:27, Harald Gutmann wrote:
Am Dienstag, 13. November 2007 02:27:21 schrieb Carl-Daniel Hailfinger:
We have to change * NOLDN idx 0x24 (Flash) * LDN 0x07 idx 0x64+0x65 (Flash), 0xc9 (Simple I/O) The rest of the differences is either "don't care" at the moment or changing is actively harmful. If we ever decide to support automatic fan control and stuff like that, we have to revisit LDN 0x04. If we ever decide to NOT support EPP/ECP parallel port modes, we have to revisit LDN 0x03.
Try this patch:
done, but flashrom fails. here is a diff from the lb-superiotool output from rev2955 to the
"rev2955" from the linuxbios image, without your patch.
superiotool output from rev2958 with your patch.
"rev2958 with your patch" <- from linuxbios image with the last patch from this thread.
Strange. None of the changes in my patch show up in your superiotool output. That either means these registers are special or some part of the patch was ineffective or it was not applied. The changes in superiotool output have no relation at all to the patch. LDN 0x7 idx 0xc9 should have value 0x40, but your diff claims it is still 0x0. Since everything else is normal, the only possible conclusion is that you either booted an image without my patch (not necessarily your fault) or something magic resets all values to those from a revision without my patch. Did you remove the build directory before rebuilding? Did you power off the machine before booting with the patch? Can you run superiotool before running flashrom? Regards, Carl-Daniel
Am Dienstag, 13. November 2007 16:53:54 schrieb Carl-Daniel Hailfinger:
Strange. None of the changes in my patch show up in your superiotool output. That either means these registers are special or some part of the patch was ineffective or it was not applied. you are right! - it seems that somewhere a mistake happened to me, but i can't say exactly where. i did a new co from the lb v2 and added your patch, build the image flashed and the superiotool output looks much more different. this time i built it manually, not with the buildrom tool like before.
i attached a diff between the superiotool output from new linuxbios with your patch and the output from superiotool from an older revision of lb. also a second diff between the new lb version with your patch and the propritary bios is attached. (superiotool outputs) flashrom also don't fail any more with the "old" error message, but it seems to hang on probing for the mx25l4005a: benchvice flashrom # ./flashrom -m gigabyte:m57sli -V Calibrating delay loop... 916M loops per second. OK. Found canidate at: 00000530-00000e44 Found LinuxBIOS table at 0x00000530. LinuxBIOS table found at 0x2ac58971e530. LinuxBIOS header(24) checksum: 5897 table(2324) checksum: 0c99 entries: 14 Vendor ID: GIGABYTE, part ID: m57sli Overwritten by command line, vendor ID: gigabyte, part ID: m57sli. Found chipset "NVIDIA MCP55", enabling flash write... OK. Found board "GIGABYTE GA-M57SLI-S4": enabling flash write... Serial flash segment 0xfffe0000-0xffffffff enabled Serial flash segment 0x000e0000-0x000fffff enabled Serial flash segment 0xffee0000-0xffefffff disabled Serial flash segment 0xfff80000-0xfffeffff enabled LPC write to serial flash enabled serial flash pin 29 OK. Probing for Am29F040B, 512 KB probe_29f040b: id1 0x7f, id2 0x45 Probing for Am29LV040B, 512 KB probe_29f040b: id1 0x7f, id2 0x45 Probing for Am29F016D, 2048 KB probe_29f040b: id1 0xff, id2 0xff Probing for AE49F2008, 256 KB probe_jedec: id1 0x7f, id2 0x45 Probing for At29C040A, 512 KB probe_jedec: id1 0x7f, id2 0x45 Probing for At29C020, 256 KB probe_jedec: id1 0x7f, id2 0x45 Probing for MBM29F400TC, 512 KB probe_m29f400bt: id1 0x7f, id2 0x4c Probing for MX29F002, 256 KB probe_29f002: id1 0x7f, id2 0x45 Probing for MX25L4005, 512 KB at this point nothing more happens.
The changes in superiotool output have no relation at all to the patch. LDN 0x7 idx 0xc9 should have value 0x40, but your diff claims it is still 0x0. Since everything else is normal, the only possible conclusion is that you either booted an image without my patch (not necessarily your fault) or something magic resets all values to those from a revision without my patch.
Did you remove the build directory before rebuilding? Did you power off the machine before booting with the patch? Can you run superiotool before running flashrom? i thaught i've done everything right, but somewhere a mistake happened.
Regards, Carl-Daniel
regards, harald
On Tue, Nov 13, 2007 at 07:34:22PM +0100, Harald Gutmann wrote:
Am Dienstag, 13. November 2007 16:53:54 schrieb Carl-Daniel Hailfinger:
Strange. None of the changes in my patch show up in your superiotool output. That either means these registers are special or some part of the patch was ineffective or it was not applied. you are right! - it seems that somewhere a mistake happened to me, but i can't say exactly where. i did a new co from the lb v2 and added your patch, build the image flashed and the superiotool output looks much more different. this time i built it manually, not with the buildrom tool like before.
Here's your problem. buildrom always uses one specific svn revision which is hardcoded in buildrom, it doesn't get new ones automatically. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
Am Dienstag, 13. November 2007 19:57:45 schrieb Uwe Hermann:
On Tue, Nov 13, 2007 at 07:34:22PM +0100, Harald Gutmann wrote:
Am Dienstag, 13. November 2007 16:53:54 schrieb Carl-Daniel Hailfinger:
Strange. None of the changes in my patch show up in your superiotool output. That either means these registers are special or some part of the patch was ineffective or it was not applied.
you are right! - it seems that somewhere a mistake happened to me, but i can't say exactly where. i did a new co from the lb v2 and added your patch, build the image flashed and the superiotool output looks much more different. this time i built it manually, not with the buildrom tool like before.
Here's your problem. buildrom always uses one specific svn revision which is hardcoded in buildrom, it doesn't get new ones automatically.
i know that, but i can set the "override specified linuxbios version" in make menuconfig, and update the source/linuxbios/svn via svn up. but i don't know exactly if the buildrom tree overwrites the updates in the source tree of linuxbios
Uwe.
Harald
On Tue, Nov 13, 2007 at 08:51:17PM +0100, Harald Gutmann wrote:
Here's your problem. buildrom always uses one specific svn revision which is hardcoded in buildrom, it doesn't get new ones automatically.
i know that, but i can set the "override specified linuxbios version" in make menuconfig, and update the source/linuxbios/svn via svn up. but i don't know exactly if the buildrom tree overwrites the updates in the source tree of linuxbios
I always do a make distclean before I do a new make. Thanks, Ward. -- Ward Vandewege <ward@fsf.org> Free Software Foundation - Senior System Administrator
On 13.11.2007 19:34, Harald Gutmann wrote:
Am Dienstag, 13. November 2007 16:53:54 schrieb Carl-Daniel Hailfinger:
Strange. None of the changes in my patch show up in your superiotool output. That either means these registers are special or some part of the patch was ineffective or it was not applied.
you are right! - it seems that somewhere a mistake happened to me, but i can't say exactly where.
Thanks for retrying manually.
i attached a diff between the superiotool output from new linuxbios with your patch and the output from superiotool from an older revision of lb. also a second diff between the new lb version with your patch and the propritary bios is attached. (superiotool outputs)
Thanks! It seems the patch is almost commit-ready.
flashrom also don't fail any more with the "old" error message, but it seems to hang on probing for the mx25l4005a: benchvice flashrom # ./flashrom -m gigabyte:m57sli -V Calibrating delay loop... 916M loops per second. OK. Found canidate at: 00000530-00000e44 Found LinuxBIOS table at 0x00000530. LinuxBIOS table found at 0x2ac58971e530. LinuxBIOS header(24) checksum: 5897 table(2324) checksum: 0c99 entries: 14 Vendor ID: GIGABYTE, part ID: m57sli Overwritten by command line, vendor ID: gigabyte, part ID: m57sli. Found chipset "NVIDIA MCP55", enabling flash write... OK. Found board "GIGABYTE GA-M57SLI-S4": enabling flash write... Serial flash segment 0xfffe0000-0xffffffff enabled Serial flash segment 0x000e0000-0x000fffff enabled Serial flash segment 0xffee0000-0xffefffff disabled Serial flash segment 0xfff80000-0xfffeffff enabled LPC write to serial flash enabled serial flash pin 29 OK. Probing for Am29F040B, 512 KB probe_29f040b: id1 0x7f, id2 0x45 Probing for Am29LV040B, 512 KB probe_29f040b: id1 0x7f, id2 0x45 Probing for Am29F016D, 2048 KB probe_29f040b: id1 0xff, id2 0xff Probing for AE49F2008, 256 KB probe_jedec: id1 0x7f, id2 0x45 Probing for At29C040A, 512 KB probe_jedec: id1 0x7f, id2 0x45 Probing for At29C020, 256 KB probe_jedec: id1 0x7f, id2 0x45 Probing for MBM29F400TC, 512 KB probe_m29f400bt: id1 0x7f, id2 0x4c Probing for MX29F002, 256 KB probe_29f002: id1 0x7f, id2 0x45 Probing for MX25L4005, 512 KB
at this point nothing more happens.
Can you abort flashrom with Ctrl-C or does the whole machine hang? If the machine does not hang, can you give me an Acked-by: tag? That way I can commit and improve from there. Regards, Carl-Daniel
Am Mittwoch, 14. November 2007 01:14:52 schrieb Carl-Daniel Hailfinger:
On 13.11.2007 19:34, Harald Gutmann wrote:
Am Dienstag, 13. November 2007 16:53:54 schrieb Carl-Daniel Hailfinger:
Strange. None of the changes in my patch show up in your superiotool output. That either means these registers are special or some part of the patch was ineffective or it was not applied.
you are right! - it seems that somewhere a mistake happened to me, but i can't say exactly where.
Thanks for retrying manually.
i attached a diff between the superiotool output from new linuxbios with your patch and the output from superiotool from an older revision of lb. also a second diff between the new lb version with your patch and the propritary bios is attached. (superiotool outputs)
Thanks! It seems the patch is almost commit-ready.
flashrom also don't fail any more with the "old" error message, but it seems to hang on probing for the mx25l4005a: benchvice flashrom # ./flashrom -m gigabyte:m57sli -V Calibrating delay loop... 916M loops per second. OK. Found canidate at: 00000530-00000e44 Found LinuxBIOS table at 0x00000530. LinuxBIOS table found at 0x2ac58971e530. LinuxBIOS header(24) checksum: 5897 table(2324) checksum: 0c99 entries: 14 Vendor ID: GIGABYTE, part ID: m57sli Overwritten by command line, vendor ID: gigabyte, part ID: m57sli. Found chipset "NVIDIA MCP55", enabling flash write... OK. Found board "GIGABYTE GA-M57SLI-S4": enabling flash write... Serial flash segment 0xfffe0000-0xffffffff enabled Serial flash segment 0x000e0000-0x000fffff enabled Serial flash segment 0xffee0000-0xffefffff disabled Serial flash segment 0xfff80000-0xfffeffff enabled LPC write to serial flash enabled serial flash pin 29 OK. Probing for Am29F040B, 512 KB probe_29f040b: id1 0x7f, id2 0x45 Probing for Am29LV040B, 512 KB probe_29f040b: id1 0x7f, id2 0x45 Probing for Am29F016D, 2048 KB probe_29f040b: id1 0xff, id2 0xff Probing for AE49F2008, 256 KB probe_jedec: id1 0x7f, id2 0x45 Probing for At29C040A, 512 KB probe_jedec: id1 0x7f, id2 0x45 Probing for At29C020, 256 KB probe_jedec: id1 0x7f, id2 0x45 Probing for MBM29F400TC, 512 KB probe_m29f400bt: id1 0x7f, id2 0x4c Probing for MX29F002, 256 KB probe_29f002: id1 0x7f, id2 0x45 Probing for MX25L4005, 512 KB
at this point nothing more happens.
Can you abort flashrom with Ctrl-C or does the whole machine hang? Just flashrom hangs, and i'm able to abort it with Ctrl-C.
If the machine does not hang, can you give me an Acked-by: tag? That way I can commit and improve from there.
Acked-by: Harald Gutmann <harald.gutmann@gmx.net>
Regards, Carl-Daniel regards, Harald
On 14.11.2007 08:46, Harald Gutmann wrote:
Am Mittwoch, 14. November 2007 01:14:52 schrieb Carl-Daniel Hailfinger:
On 13.11.2007 19:34, Harald Gutmann wrote:
Probing for MX25L4005, 512 KB
at this point nothing more happens.
Can you abort flashrom with Ctrl-C or does the whole machine hang?
Just flashrom hangs, and i'm able to abort it with Ctrl-C.
If the machine does not hang, can you give me an Acked-by: tag? That way I can commit and improve from there.
Acked-by: Harald Gutmann <harald.gutmann@gmx.net>
Thanks, committed in r2972. Regards, Carl-Daniel
#87: flashrom issues on m57sli-s4 -------------------------+-------------------------------------------------- Reporter: ward | Owner: hailfinger Type: defect | Status: assigned Priority: major | Milestone: Component: flashrom | Version: v2 Resolution: | Keywords: Dependencies: | Patchstatus: there is no patch -------------------------+-------------------------------------------------- Changes (by hailfinger): * status: new => assigned Comment: Thanks to Torsten and Andi for testing. This is fixed in r2955 for parallel flash. Serial flash remains to be solved. For that I need superiotool output for both board generations under LB rev2955. -- Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/87#comment:5> LinuxBIOS <http://www.linuxbios.org/>
participants (8)
-
Andreas B. Mundt -
Carl-Daniel Hailfinger -
Corey Osgood -
Harald Gutmann -
LinuxBIOS -
Torsten Duwe -
Uwe Hermann -
Ward Vandewege