September 2026 - coreboot - mail.coreboot.org

[coreboot - Bug #601] (New) superio/nuvoton/npcd378:379 FAN issue sandy/ivy-bridge & haswell on HP
by Walter Sonius Oct. 15, 2026

Oct. 15, 2026

Issue #601 has been reported by Walter Sonius. ---------------------------------------- Bug #601: superio/nuvoton/npcd378:379 FAN issue sandy/ivy-bridge & haswell on HP https://ticket.coreboot.org/issues/601 * Author: Walter Sonius * Status: New * Priority: Normal * Assignee: Patrick Rudolph * Category: board support * Target version: main * Start date: 2025-07-05 * Affected versions: 25.03 * Affected hardware: compaq_8200_elite_sff, compaq_8300_elite_sff, compaq_pro_6300_sff, 260_g1_dm, prodesk_600_g1_sff ---------------------------------------- The NPCD378 HWM FAN control is limited to the PSU FAN only but should work for the "compaq_8200_elite_sff" according to its [commit and instruction](https://review.coreboot.org/c/coreboot/+/26050), which states "... the SuperIO has to be notified that a write is ongoing. After clearing the write-lock bit all changes are applied...". Is there a special command that I missed that "clears the write-lock" or is there a bug and is its current implementation broken? Since adjusting the nvram parameter `sudo nvramtool -w psu_fan_lvl=1-7`and doing a reboot or cold powerup does show that the nvram parameter changes (can be confirmed by coreboot log or reading the nvram parameter after boot again) it never changes the actual PSU FAN speed! Tried multiple coreboot/seabios/edk2 versions the last 3 months on 5 different HP machines and came to the following conclusion. The following nvramtool `psu_fan_lvl=values` reflect the following PWM feedback from the coreboot log: ``` =1 [INFO ] NPCD378: PSU fan PWM 0x37 =2 [INFO ] NPCD378: PSU fan PWM 0x57 =3 [INFO ] NPCD378: PSU fan PWM 0x77 =4 [INFO ] NPCD378: PSU fan PWM 0x97 =5 [INFO ] NPCD378: PSU fan PWM 0xb7 =6 [INFO ] NPCD378: PSU fan PWM 0xd7 =7 [INFO ] NPCD378: PSU fan PWM 0xf8 ``` The following 3 supported sandy/ivy bridge HP variants share the same issue that nvram parameters and coreboot log show the requested manual `psu_fan_lvl` values but its PSU FAN speed won't change according to these values, atleast its FANs keep spinning after post/boot on these machines: ``` VALUE FAN SPEED compaq_8200_elite_sff NPCD378 adjusts remains same compaq_8300_elite_sff NPCD379 adjusts remains same compaq_pro_6300_sff NPCD379 adjusts remains same ``` The following 2 yet uncommited HP Haswell coreboot variants, "HP 260 G1 DM (Desktop Mini) Business PC" and "HP Prodesk 600 G1 SFF" both come with a NPCD379 and both share the same issue with the former 3 variants that the `psu_fan_lvl` value's can be adjusted by nvramtool(if cmos backend is added to the code) and verified during boot or nvramtool that these values have changed with affecting the PSU FAN speed in a undesired way: ``` VALUE FAN SPEED 260_g1_dm NPCD379 adjusts stops spinning prodesk_600_g1_sff NPCD379 adjusts stops spinning ``` These 2 Haswell machines will halt "and stop spinning" the PSU FAN as soon as during post the "PSU fan PWM" value kicks in!!! A side note is needed for the HP 260 G1 DM since it only has a single FAN, so I'm not sure if its CPU or its PSU FAN technically and its OEM BIOS misses a option the adjust FAN speed compared to the other 4 HP models! Another side note for the Prodesk 600 G1 SFF is that I'm forced to use a aftermarket non HP CPU FAN(old Intel CPU FAN), but it keeps spinning after coreboot post. Removing the FAN/HWM code from the superio NPCD378 source, leads to the opposite it will force the PSU FAN to its MAXIMUM speed after poweron but atleast keeps the FAN spinning. This maximum forced full speed FAN behaviour can also be replicated by removing one of the 4 FAN wires, red or white cable not sure anymore. Interesting FAN notes: In case of the "Prodesk 600 G1", swapping its PSU with the PSU from the "compaq_8300_elite_sff" keeps the PSU fan spinning during and after coreboot post but it will still not adjust its PSU FAN speed to its requested values! Also the other way around, putting the PSU of the "Prodesk 600 G1" inside the "compaq_8300_elite_sff" stops the PSU FAN during coreboot post, but running the OEM firmware, keeps the fan spinning and let it adjust to all requested values on its donor FAN. So it seems there is a certain PWM compatibility to control these FAN's in similar ways between these boards. It seems the the newer PSU FAN from the Haswell generation can actually disable / stop spinning on a certain PWM value while older FAN keep spinning on these lower/ same PWM values. Compared to the [initial support commit](https://review.coreboot.org/c/coreboot/+/26050) by Patrick Rudolph, around April 2021 there were some [code](https://review.coreboot.org/c/coreboot/+/52511) [fixes](https://review.coreboot.org/c/coreboot/+/52671) but after that the last time this `psu_fan_lvl` code was verified functional was between 2023-05-02 and 2023-07-03 noted in the [boardsupport commit](https://review.coreboot.org/c/coreboot/+/74906) of the variant `compaq_8300_elite_sff_usdt` by Riku Viitanen. History for "coreboot/src/superio/nuvoton/npcd378" shows [6 patches](https://github.com/coreboot/coreboot/commits/main/src/superio/nuvo… from november 2023 till today. Any tips hints welcome. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

2 5

[coreboot - Bug #576] (New) GPIO locking is broken on Kaby Lake and possibly other platforms
by Mate Kukri Oct. 8, 2026

Oct. 8, 2026

Issue #576 has been reported by Mate Kukri. ---------------------------------------- Bug #576: GPIO locking is broken on Kaby Lake and possibly other platforms https://ticket.coreboot.org/issues/576 * Author: Mate Kukri * Status: New * Priority: Normal * Target version: none * Start date: 2025-01-30 ---------------------------------------- Many supported Kaby Lake boards (and possibly newer platforms as well) are vulnerable to [TPM GPIO reset attacks](https://mkukri.xyz/2024/06/01/tpm-gpio-fail.html). Trying to fix this by marking the affected GPIOs as locked in gpio.h and even also selecting `SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS` does not work. This was discovered last year and briefly discussed on #coreboot, but it came up again on the Heads matrix group in relation to supporting the TPM on the in-progress ThinkPad T480 port. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

5 11

Easiest hardware to get started with coreboot
by Ashok Arora Oct. 5, 2026

Oct. 5, 2026

Hi, I was planning to port coreboot to untested motherboards, but due to my recent job, I haven’t been able to spend enough time on it. To scratch my itch of getting some hardware to boot, I’d like to know what you think is the easiest hardware to install coreboot on. Ideally, it would be nice if it also supports Libreboot. Regards*,* A

4 3

[coreboot - Bug #642] (New) x201t Turbo boost not working, CPU running hot
by Janez Novak Oct. 4, 2026

Oct. 4, 2026

Issue #642 has been reported by Janez Novak. ---------------------------------------- Bug #642: x201t Turbo boost not working, CPU running hot https://ticket.coreboot.org/issues/642 * Author: Janez Novak * Status: New * Priority: Normal * Category: chipset configuration * Target version: main * Start date: 2026-05-03 * Affected versions: main * Affected hardware: Lenovo X201 Tablet * Affected OS: All ---------------------------------------- Hello, i installed Coreboot on my x201t but turbo boost isn’t working and cpu won’t go past 2.1 GHz. My processor is an i7 640LM. Something i also noticed is that the system runs hotter with coreboot than with stock bios but i don’t know what’s causing that. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

3 13

[coreboot - Bug #620] (New) X230(t) does not work since commit 97dbfd3098ae12ef3f51e5f95cd6d66c25214205 was merged
by Hustler One Oct. 3, 2026

Oct. 3, 2026

Issue #620 has been reported by Hustler One. ---------------------------------------- Bug #620: X230(t) does not work since commit 97dbfd3098ae12ef3f51e5f95cd6d66c25214205 was merged https://ticket.coreboot.org/issues/620 * Author: Hustler One * Status: New * Priority: High * Category: coreboot common code * Target version: main * Start date: 2025-12-31 * Affected versions: main * Related links: https://www.reddit.com/r/coreboot/comments/1pu5vlp/x230t_does_not_get_past_… https://www.reddit.com/r/coreboot/comments/1pyzcvf/no_video_output_with_upd… * Affected hardware: x230t ---------------------------------------- Releases 25.09, 25.12 are affected. 25.06 works. The commit 97dbfd3098ae12ef3f51e5f95cd6d66c25214205 prevents the x230t from going past the `postcar` stage, hence it being inoperable since it won't load into the main payload. I have attempted to debug using flashconsole but the trail runs cold after `postcar`. Credit to iam_tj for finding the commit. Also, Libreboot is somehow unaffected by this. I don't know if lbmk undoes this commit or not at this time. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

4 5

[coreboot - Bug #623] (New) On T480/S, missing P-state data from ACPI tables prevents Xen from performing frequency scaling
by herme herme Oct. 3, 2026

Oct. 3, 2026

Issue #623 has been reported by herme herme. ---------------------------------------- Bug #623: On T480/S, missing P-state data from ACPI tables prevents Xen from performing frequency scaling https://ticket.coreboot.org/issues/623 * Author: herme herme * Status: New * Priority: Normal * Target version: none * Start date: 2026-01-16 * Affected versions: main * Affected hardware: T480/S * Affected OS: QubesOS ---------------------------------------- Hello Currently, P-state data is missing from ACPI tables on T480/S. On my T480S running libreboot, this was confirmed by using the iasl command to decompile the tables at `/sys/firmware/acpi/tables/`; grepping for `_PSS`, `_PCT` and `_PPC` didn't return any results. (Another user)[https://codeberg.org/libreboot/lbmk/issues/394] has confirmed that this is also the case for the similar T480 device, with latest release build of libreboot (26.01 RC1). Meanwhile, in the vendor T480S BIOS, this data is present (contributed by @henk on #coreboot IRC channel): ``` # grep -r -e _PCT -e _PPC -e _PSS *.dsl DSDT.dsl: If (CondRefOf (\_PR.PR00._PPC)) DSDT.dsl: If ((CondRefOf (\_PR.PR00._PSS) && CondRefOf (\_PR.PR00._PPC))) SSDT1.dsl: External (_PR_.PR00._PSS, MethodObj) // 0 Arguments SSDT1.dsl: Name (_PPC, Zero) // _PPC: Performance Present Capabilities SSDT1.dsl: If (CondRefOf (\_PR.PR00._PSS)) SSDT1.dsl: Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States SSDT1.dsl: If (CondRefOf (\_PR.PR00._PSS)) SSDT1.dsl: Return (\_PR.PR00._PSS ()) SSDT1.dsl: If (CondRefOf (\_PR.PR00._PSS)) SSDT8.dsl: If (CondRefOf (\_PR.PR00._PSS)) ``` The Linux kernel doesn't rely on this data to perform frequency scaling, because native support is provided by the intel_pstate driver. However, the Xen kernel lacks this native support. When the data is missing, as in my case, the Xen-based QubesOS runs underclocked and is only barely usable. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

4 8

Bug of the latest 3rdparty/libgfxinit
by Persmule Oct. 2, 2026

Oct. 2, 2026

coreboot 7a5f91cae93cc0a5420bb3569f521a8addb228ed built for hp elitebook 2170p (possibly for other ivb targets as well) timeout when reading EDID, log: > [DEBUG] PCI: 00:00:02.0 init > [DEBUG] Starting cbfs_boot_device > [INFO ] CBFS: Found 'vbt.bin' @0x2ee40 size 0x55c in mcache @0x7ffdc154 > [INFO ] VB2:vb2_digest_init() 1372 bytes, hash algo 1, HW acceleration unsupported > [DEBUG] TPM: Digest of `CBFS: vbt.bin` to PCR 2 logged > [INFO ] Timestamp - starting LZMA decompress (ignore for x86): 34157786266 > [INFO ] Timestamp - finished LZMA decompress (ignore for x86): 34171367170 > [INFO ] Found a VBT of 4280 bytes > [INFO ] GMA: Found VBT in CBFS > [INFO ] GMA: Found valid VBT in CBFS > [DEBUG] GT Power Management Init > [DEBUG] IVB GT2 17W Power Meter Weights > [DEBUG] GT Power Management Init (post VBIOS) > [2.913019] HW.GFX.GMA.Initialize > [2.915797] HW.GFX.GMA.Panel.Setup_PP_Sequencer > [2.919940] HW.GFX.GMA.Panel.Setup_PP_Sequencer > [2.924085] HW.GFX.GMA.Registers.Read: 0x012c07d0 <- 0x000c7208:PCH_PP_ON_DELAYS > [2.931165] HW.GFX.GMA.Registers.Read: 0x00e607d0 <- 0x000c720c:PCH_PP_OFF_DELAYS > [2.938331] HW.GFX.GMA.Registers.Read: 0x00186905 <- 0x000c7210:PCH_PP_DIVISOR > [2.945238] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_CONTROL > [2.951110] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7204:PCH_PP_CONTROL > [2.958016] HW.GFX.GMA.Registers.Write: 0xabcd0002 -> 0x000c7204:PCH_PP_CONTROL > [2.965025] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S CPU_VGACNTRL > [2.970964] HW.GFX.GMA.Registers.Read: 0x00002900 <- 0x00041000:CPU_VGACNTRL > [2.977699] HW.GFX.GMA.Registers.Write: 0x80002900 -> 0x00041000:CPU_VGACNTRL > [2.984433] HW.GFX.GMA.Registers.Write: 0x00001402 -> 0x000c6200:PCH_DREF_CONTROL > [2.991515] HW.GFX.GMA.Registers.Read: 0x00001402 <- 0x000c6200:PCH_DREF_CONTROL > [2.998595] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A > [3.003774] HW.GFX.GMA.Registers.Read: 0x00000018 <- 0x00064000:DDI_BUF_CTL_A > [3.010595] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_LVDS > [3.015343] HW.GFX.GMA.Registers.Read: 0x00000002 <- 0x000e1180:PCH_LVDS > [3.021732] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A > [3.026912] HW.GFX.GMA.Registers.Read: 0x00000018 <- 0x00064000:DDI_BUF_CTL_A > [3.033733] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_HDMIB > [3.038569] HW.GFX.GMA.Registers.Read: 0x0000001c <- 0x000e1140:PCH_HDMIB > [3.045044] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_B > [3.049793] HW.GFX.GMA.Registers.Read: 0x00000004 <- 0x000e4100:PCH_DP_B > [3.056182] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL > [3.061880] HW.GFX.GMA.Registers.Read: 0x00101010 <- 0x000c4030:SHOTPLUG_CTL > [3.068615] HW.GFX.GMA.Registers.Write: 0x00101013 -> 0x000c4030:SHOTPLUG_CTL > [3.075350] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_HDMIC > [3.080184] HW.GFX.GMA.Registers.Read: 0x0000001c <- 0x000e1150:PCH_HDMIC > [3.086660] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_C > [3.091409] HW.GFX.GMA.Registers.Read: 0x00000004 <- 0x000e4200:PCH_DP_C > [3.097797] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL > [3.103496] HW.GFX.GMA.Registers.Read: 0x00101010 <- 0x000c4030:SHOTPLUG_CTL > [3.110230] HW.GFX.GMA.Registers.Write: 0x00101310 -> 0x000c4030:SHOTPLUG_CTL > [3.116965] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_HDMID > [3.121800] HW.GFX.GMA.Registers.Read: 0x0000001c <- 0x000e1160:PCH_HDMID > [3.128276] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_D > [3.133026] HW.GFX.GMA.Registers.Read: 0x00000004 <- 0x000e4300:PCH_DP_D > [3.139415] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL > [3.145113] HW.GFX.GMA.Registers.Read: 0x00101010 <- 0x000c4030:SHOTPLUG_CTL > [3.151848] HW.GFX.GMA.Registers.Write: 0x00131010 -> 0x000c4030:SHOTPLUG_CTL > [3.158582] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_RAWCLK_FREQ > [3.164540] HW.GFX.GMA.Registers.Read: 0x0000007d <- 0x000c6204:PCH_RAWCLK_FREQ > [3.171533] HW.GFX.GMA.Registers.Write: 0x0000007d -> 0x000c6204:PCH_RAWCLK_FREQ > [3.178527] HW.GFX.GMA.Panel.On > [3.181290] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_PP_CONTROL > [3.186557] HW.GFX.GMA.Registers.Read: 0xabcd0002 <- 0x000c7204:PCH_PP_CONTROL > [3.193464] HW.GFX.GMA.Registers.Set_Mask: 0x00000001 .S PCH_PP_CONTROL > [3.199681] HW.GFX.GMA.Registers.Read: 0xabcd0002 <- 0x000c7204:PCH_PP_CONTROL > [3.206588] HW.GFX.GMA.Registers.Write: 0xabcd0003 -> 0x000c7204:PCH_PP_CONTROL > [3.213495] HW.GFX.GMA.Display_Probing.Read_EDID > [3.217726] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_B > [3.223166] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4110:PCH_DP_AUX_CTL_B > [3.230246] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4114:PCH_DP_AUX_DATA_B_1 > [3.237586] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_B > [3.243630] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4110:PCH_DP_AUX_CTL_B > [3.250709] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4110:PCH_DP_AUX_CTL_B > [3.257790] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4110:PCH_DP_AUX_CTL_B > [3.265993] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B > [3.273071] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_B > [3.278511] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B > [3.285591] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4114:PCH_DP_AUX_DATA_B_1 > [3.292931] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_B > [3.298974] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B > [3.306053] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4110:PCH_DP_AUX_CTL_B > [3.313134] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4110:PCH_DP_AUX_CTL_B > [3.321337] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B > [3.328415] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_B > [3.333854] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B > [3.340933] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4114:PCH_DP_AUX_DATA_B_1 > [3.348273] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_B > [3.354318] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B > [3.361396] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4110:PCH_DP_AUX_CTL_B > [3.368477] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4110:PCH_DP_AUX_CTL_B > [3.376681] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4110:PCH_DP_AUX_CTL_B > [3.383759] HW.GFX.GMA.Display_Probing.Read_EDID > [3.387989] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_C > [3.393430] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4210:PCH_DP_AUX_CTL_C > [3.400508] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4214:PCH_DP_AUX_DATA_C_1 > [3.407849] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_C > [3.413893] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4210:PCH_DP_AUX_CTL_C > [3.420972] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4210:PCH_DP_AUX_CTL_C > [3.428053] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4210:PCH_DP_AUX_CTL_C > [3.436256] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C > [3.443334] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_C > [3.448774] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C > [3.455854] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4214:PCH_DP_AUX_DATA_C_1 > [3.463194] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_C > [3.469237] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C > [3.476317] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4210:PCH_DP_AUX_CTL_C > [3.483397] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4210:PCH_DP_AUX_CTL_C > [3.491601] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C > [3.498679] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_C > [3.504119] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C > [3.511199] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4214:PCH_DP_AUX_DATA_C_1 > [3.518539] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_C > [3.524582] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C > [3.531661] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4210:PCH_DP_AUX_CTL_C > [3.538743] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4210:PCH_DP_AUX_CTL_C > [3.546945] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4210:PCH_DP_AUX_CTL_C > [3.554023] HW.GFX.GMA.Display_Probing.Read_EDID > [3.558253] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_D > [3.563694] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4310:PCH_DP_AUX_CTL_D > [3.570772] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4314:PCH_DP_AUX_DATA_D_1 > [3.578112] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_D > [3.584156] HW.GFX.GMA.Registers.Read: 0x00050000 <- 0x000e4310:PCH_DP_AUX_CTL_D > [3.591236] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4310:PCH_DP_AUX_CTL_D > [3.598316] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4310:PCH_DP_AUX_CTL_D > [3.606519] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D > [3.613599] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_D > [3.619038] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D > [3.626117] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4314:PCH_DP_AUX_DATA_D_1 > [3.633457] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_D > [3.639501] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D > [3.646580] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4310:PCH_DP_AUX_CTL_D > [3.653661] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4310:PCH_DP_AUX_CTL_D > [3.661864] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D > [3.668943] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_DP_AUX_CTL_D > [3.674383] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D > [3.681463] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x000e4314:PCH_DP_AUX_DATA_D_1 > [3.688802] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_DP_AUX_CTL_D > [3.694845] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D > [3.701924] HW.GFX.GMA.Registers.Write: 0xd635003f -> 0x000e4310:PCH_DP_AUX_CTL_D > [3.709005] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x000e4310:PCH_DP_AUX_CTL_D > [3.717208] HW.GFX.GMA.Registers.Read: 0x5545003f <- 0x000e4310:PCH_DP_AUX_CTL_D > [3.724286] HW.GFX.GMA.Display_Probing.Read_EDID > [3.728516] HW.GFX.GMA.I2C.I2C_Read > [3.731624] HW.GFX.GMA.I2C.Init_GMBUS > [3.734906] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2 > [3.742590] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4 > [3.749153] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5 > [3.755715] HW.GFX.GMA.Registers.Write: 0x00000005 -> 0x000c5100:PCH_GMBUS0 > [3.762276] HW.GFX.GMA.I2C.Check_And_Reset > [3.765989] HW.GFX.GMA.Registers.Read: 0x00000800 <- 0x000c5108:PCH_GMBUS2 > [3.772551] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1 > [3.779114] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 > [3.836799] HW.GFX.GMA.Registers.Wait: Timed Out! > [3.840958] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2 > [3.847520] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2 > [3.855204] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1 > [3.861767] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1 > [3.868329] HW.GFX.GMA.I2C.Release_GMBUS > [3.871868] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0 > [3.878430] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2 > [3.884992] HW.GFX.GMA.Display_Probing.Read_EDID > [3.889221] HW.GFX.GMA.I2C.I2C_Read > [3.892329] HW.GFX.GMA.I2C.Init_GMBUS > [3.895609] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2 > [3.903294] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4 > [3.909856] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5 > [3.916418] HW.GFX.GMA.Registers.Write: 0x00000004 -> 0x000c5100:PCH_GMBUS0 > [3.922980] HW.GFX.GMA.I2C.Check_And_Reset > [3.926693] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c5108:PCH_GMBUS2 > [3.933253] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1 > [3.939815] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 > [3.997500] HW.GFX.GMA.Registers.Wait: Timed Out! > [4.001660] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2 > [4.008220] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2 > [4.015906] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1 > [4.022467] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1 > [4.029030] HW.GFX.GMA.I2C.Release_GMBUS > [4.032568] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0 > [4.039131] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2 > [4.045692] HW.GFX.GMA.Display_Probing.Read_EDID > [4.049923] HW.GFX.GMA.I2C.I2C_Read > [4.053031] HW.GFX.GMA.I2C.Init_GMBUS > [4.056312] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2 > [4.063996] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4 > [4.070558] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5 > [4.077119] HW.GFX.GMA.Registers.Write: 0x00000006 -> 0x000c5100:PCH_GMBUS0 > [4.083681] HW.GFX.GMA.I2C.Check_And_Reset > [4.087395] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c5108:PCH_GMBUS2 > [4.093956] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1 > [4.100518] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 > [4.158204] HW.GFX.GMA.Registers.Wait: Timed Out! > [4.162363] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2 > [4.168925] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2 > [4.176610] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1 > [4.183172] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1 > [4.189734] HW.GFX.GMA.I2C.Release_GMBUS > [4.193273] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0 > [4.199836] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2 > [4.206398] HW.GFX.GMA.Display_Probing.Read_EDID > [4.210627] HW.GFX.GMA.I2C.I2C_Read > [4.213735] HW.GFX.GMA.I2C.Init_GMBUS > [4.217016] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2 > [4.224701] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4 > [4.231263] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5 > [4.237826] HW.GFX.GMA.Registers.Write: 0x00000002 -> 0x000c5100:PCH_GMBUS0 > [4.244388] HW.GFX.GMA.I2C.Check_And_Reset > [4.248100] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c5108:PCH_GMBUS2 > [4.254661] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1 > [4.261224] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 > [4.318908] HW.GFX.GMA.Registers.Wait: Timed Out! > [4.323067] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2 > [4.329629] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2 > [4.337313] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1 > [4.343875] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1 > [4.350437] HW.GFX.GMA.I2C.Release_GMBUS > [4.353977] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0 > [4.360539] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2 > [4.367100] HW.GFX.GMA.Panel.Wait_On > [4.370295] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x30000000 & 0x000c7200:PCH_PP_STATUS > [4.378238] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PCH_PP_CONTROL > [4.384627] HW.GFX.GMA.Registers.Read: 0xabcd0003 <- 0x000c7204:PCH_PP_CONTROL > [4.391535] HW.GFX.GMA.Registers.Write: 0xabcd0003 -> 0x000c7204:PCH_PP_CONTROL > [4.398442] HW.GFX.GMA.Display_Probing.Read_EDID > [4.402673] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A > [4.407854] HW.GFX.GMA.Registers.Read: 0x014300c8 <- 0x00064010:DDI_AUX_CTL_A > [4.414674] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064014:DDI_AUX_DATA_A_1 > [4.421753] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A > [4.427539] HW.GFX.GMA.Registers.Read: 0x014300c8 <- 0x00064010:DDI_AUX_CTL_A > [4.434359] HW.GFX.GMA.Registers.Write: 0xd63300c8 -> 0x00064010:DDI_AUX_CTL_A > [4.441181] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A > [4.449124] HW.GFX.GMA.Registers.Read: 0x554300c8 <- 0x00064010:DDI_AUX_CTL_A > [4.455945] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A > [4.461125] HW.GFX.GMA.Registers.Read: 0x554300c8 <- 0x00064010:DDI_AUX_CTL_A > [4.467946] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064014:DDI_AUX_DATA_A_1 > [4.475026] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A > [4.480811] HW.GFX.GMA.Registers.Read: 0x554300c8 <- 0x00064010:DDI_AUX_CTL_A > [4.487632] HW.GFX.GMA.Registers.Write: 0xd63300c8 -> 0x00064010:DDI_AUX_CTL_A > [4.494453] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A > [4.502396] HW.GFX.GMA.Registers.Read: 0x554300c8 <- 0x00064010:DDI_AUX_CTL_A > [4.509218] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A > [4.514399] HW.GFX.GMA.Registers.Read: 0x554300c8 <- 0x00064010:DDI_AUX_CTL_A > [4.521219] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064014:DDI_AUX_DATA_A_1 > [4.528299] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A > [4.534084] HW.GFX.GMA.Registers.Read: 0x554300c8 <- 0x00064010:DDI_AUX_CTL_A > [4.540906] HW.GFX.GMA.Registers.Write: 0xd63300c8 -> 0x00064010:DDI_AUX_CTL_A > [4.547727] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A > [4.555669] HW.GFX.GMA.Registers.Read: 0x554300c8 <- 0x00064010:DDI_AUX_CTL_A > [4.562491] HW.GFX.GMA.Panel.Off > [4.565340] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_PP_CONTROL > [4.570607] HW.GFX.GMA.Registers.Read: 0xabcd0003 <- 0x000c7204:PCH_PP_CONTROL > [4.577514] HW.GFX.GMA.Registers.Unset_Mask: 0x00000009 !S PCH_PP_CONTROL > [4.583903] HW.GFX.GMA.Registers.Read: 0xabcd0003 <- 0x000c7204:PCH_PP_CONTROL > [4.590810] HW.GFX.GMA.Registers.Write: 0xabcd0002 -> 0x000c7204:PCH_PP_CONTROL > [4.620718] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x30000000 & 0x000c7200:PCH_PP_STATUS > [DEBUG] PCI: 00:00:02.0 init finished in 1779 msecs The screen is totally black. Reverting the last change for 3rdparty/libgfxinit (bdb8f59e9de777c1ab6d4395cc5b632f6346700a) makes the screen work again.

3 10

coreboot
by clyde Sept. 30, 2026

Sept. 30, 2026

Is it possible to use coreboot with any of the Zorin operating systems? If it is, how would I learn the details? Many thanks, Eric Jones

2 1

coreboot Meetings Announcement And Agenda Call
by mina＠coreboot.org Sept. 28, 2026

Sept. 28, 2026

Dear coreboot Community, Please be reminded that our upcoming coreboot leadership meeting is scheduled for Wednesday, September 30, 2026. [1] Kindly update the meeting agenda with any issues you'd like to discuss during the meeting. [2] Thank you. Best regards, Mina. ## Current Agenda Items * No active issues on the agenda yet. [1](https://coreboot.org/calendar.html). [2](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkK….

1 0

MRC/FSP/NRI for Xeon E5 v3/v4? (prerequisite for X99 motherboards)
by Matt B Sept. 27, 2026

Sept. 27, 2026

Hi all, There are some interesting and inexpensive motherboards out there that appear to be re-manufactured and aimed at enthusiasts, placing E5 v3/v4 Xeons on boards with support for DDR3 (even ECC) and in microATX form factors. [1] They're quite inexpensive and seem attractive for the budget-conscious server enthusiast. The catch is that there isn't support in coreboot for E5 Xeons in coreboot afaik, and I'm not sure if there are even the prerequisite firmware support bits available to get there. Is anyone able to shed light on this? -M [1] https://www.aliexpress.com/item/1005012010772569.html

1 0