February 2026 - coreboot - mail.coreboot.org

[coreboot - Support #626] (New) Haswell/T440p: Support for 16GB DDR3L modules with NRI?
by Christian Schrötter March 3, 2026

March 3, 2026

Issue #626 has been reported by Christian Schrötter. ---------------------------------------- Support #626: Haswell/T440p: Support for 16GB DDR3L modules with NRI? https://ticket.coreboot.org/issues/626 * Author: Christian Schrötter * Status: New * Priority: Low * Target version: none * Start date: 2026-01-29 * Affected hardware: T440p ---------------------------------------- There are rumors, that 16GB modules may be supported with NRI, even though the original BIOS nor the MRC blob support them in a T440p. I really wanted to test this myself, but unfortunately with limited success... I have tested two different RAM modules over the last two months: * ~~ZimaBlade - 16GB PC3L-10600S~~ (returned to seller) * Micron MT16KTF2G64HZ-1G6A1 - 16GB PC3L-12800S Both showed identical errors: * The graphics output (via VGA) is mangled and unusable. Only a small "condensed" area is visible. * EDK2 and memtest86+ start successfully (with the mentioned graphics issue), but memtest86+ crashes after a few seconds and causes a reset/reboot. * GRUB2 loads successfully, but Debian (12/13) hangs at some point. Probably during kernel initialization. The 16GB module from Micron starts up in other devices (Igel M340C + Lenovo T450s) without any problems and survives a memtest86+ over several hours. So it doesn't appear to be defective. I then added various other 2/4/8 GB modules in addition to the 16GB module. Funnily enough, this changes the graphics output! Now every second line (each consisting of a few pixels in height) is displayed correctly. Unfortunately, this does not change the fact, that memtets86+ crashes and Debian can't boot. I purchased a USB dongle (with a FT232H chip) specifically to read all Coreboot debug logs and have attached these along with my build configuration for v25.12! I would like to know whether 16GB modules are really not supported in a T440p with NRI, or whether this could be a bug? I am happy to execute further tests or flash specific commits. ---Files-------------------------------- defconfig (650 Bytes) 1769676506-2512-nri-2gb.log (51.8 KB) 1769677242-2512-nri-16gb-bottom.log (137 KB) 1769677400-2512-nri-16gb-top.log (85.4 KB) 1769677514-2512-nri-16gb+2gb.log (152 KB) 1769677649-2512-nri-16gb.log (85.4 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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coreboot Meetings Announcement And Agenda Call
by mina＠coreboot.org Feb. 27, 2026

Feb. 27, 2026

Dear coreboot Community, Please note that our next leadership meeting is scheduled for Wednesday, March 4, 2026. [1] Kindly update the agenda with any issues you'd like to discuss during the meeting. [2] Thank you. Best regards, Mina. [1](https://coreboot.org/calendar.html) [2](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkK…

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[coreboot - Bug #631] (New) Topton X2E (N150) instabilities/timer issues
by Victor Bessonov Feb. 23, 2026

Feb. 23, 2026

Issue #631 has been reported by Victor Bessonov. ---------------------------------------- Bug #631: Topton X2E (N150) instabilities/timer issues https://ticket.coreboot.org/issues/631 * Author: Victor Bessonov * Status: New * Priority: Normal * Target version: none * Start date: 2026-02-23 * Affected versions: main * Affected hardware: Topton X2E * Affected OS: Linux, BSD ---------------------------------------- Image built from master (c9578eac246) as 25.12 does not support iPXE with SecureBoot in edk2 payload. After flashing the image a few bugs were discovered (all may be related to the same root cause) 1. Some USB drives and NVMes may be not detected in edk2 on boot - setting port speed to Gen3 manually and turning off power saving mostly helps with NVMes, however some flash drives may still need to be unplugged and re-plugged back 2. Booting from Ventoy USB mostly doesn't work - some linux images wait for mount and then fail with timout, others will just hang. Ventoy itself boots quickly and reliably. 3. USB booting from images written directly to flash mostly works, however BSD may still hang or panic out with spinlock timeout panic (OpnSense/FreeBSD) 4. Linux kernel reports about broken IRQ 9 (acpi_sci=low seemingly removes the message from dmesg) 5. After several tries to boot, BSD system got installed without any issues, however after rebooting into it the system became extremely laggy (even printing to the console worked word-by-word, high LA without any userspace CPU-loading process), switching the timer from LAPIC to HPET on running system seemingly resolved all the laginess instantly 6. Linux kernel reports that HPET is dysfunctional in PC10 (shouldn't it be fine on Alder Lake?) Build config (I tried both with default xApic and x2Apic - doesn't seem to change anything): ``` shell CONFIG_VENDOR_TOPTON=y # CONFIG_POST_DEVICE is not set # CONFIG_POST_IO is not set CONFIG_TPM_MEASURED_BOOT=y CONFIG_BOARD_TOPTON_X2E_N150=y # CONFIG_FSP_HYPERTHREADING is not set CONFIG_X2APIC_ONLY=y CONFIG_TPM2=y CONFIG_TPM_MEASURE_MRC_CACHE=y CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6=y CONFIG_PAYLOAD_EDK2=y CONFIG_EDK2_ENABLE_IPXE=y ``` The majority of these problems can be explained by faulty timer - the reason for a single ticket I'm also attaching the patch suggested in Discord channel for reference - doesn't seem to solve the issue ---Files-------------------------------- coreboot.log (63.9 KB) linux-boot.log (274 KB) gpio.patch (3.1 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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2026_02_25 coreboot Group Review Session
by mina＠coreboot.org Feb. 23, 2026

Feb. 23, 2026

Hello coreboot, Kindly note that our upcoming group review session is scheduled for Wednesday, February 25. https://meet.google.com/kpu-yozw-gtt Check the coreboot calendar for the time in your timezone: https://coreboot.org/calendar.html Here is a link to the list of patches to be reviewed this week: (https://docs.google.com/spreadsheets/d/1io-tewVlkX3PAkhR9ttCKjJXiXR9Emy6qsY…) Please add any specific patches you'd like the group to review to the top of the sheet. Since an hour may not be sufficient to address all patches on the list, reviewing patches in advance is greatly appreciated. Thank you. Best regards, Mina.

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[coreboot - Bug #624] (New) Memory speed in SMBIOS is incorrectly doubled on Haswell
by Ron Nazarov Feb. 22, 2026

Feb. 22, 2026

Issue #624 has been reported by Ron Nazarov. ---------------------------------------- Bug #624: Memory speed in SMBIOS is incorrectly doubled on Haswell https://ticket.coreboot.org/issues/624 * Author: Ron Nazarov * Status: New * Priority: Normal * Assignee: Angel Pons * Target version: none * Start date: 2026-01-21 * Affected versions: main * Affected hardware: Haswell ---------------------------------------- Tested on a Dell Precision T1700 SFF with NRI, my 1600 MT/s (800 MHz) RAM is reported by `dmidecode -t 17` as running at 3200 MT/s. This bug was introduced in https://review.coreboot.org/c/coreboot/+/89598/6. The frequency is doubled in `dimm->ddr_frequency = ddr_freq_mhz * 2; /* In MT/s */`, however (at least on NRI, I did not test MRC), `ddr_freq_mhz` (defined as `(mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100`) is actually in MT/s, and so already doubled. I also see this in coreboot logs: `[DEBUG] memcfg DDR3 clock 1600 MHz`. This debug print (added in https://review.coreboot.org/c/coreboot/+/89599/4) is printing `DIV_ROUND_CLOSEST(mchbar_read32(MC_BIOS_DATA) * 13333 * 2, 100)`, which is pretty much the same as `ddr_freq_mhz` (except using `DIV_ROUND_CLOSEST`). -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #629] (New) TPM Deactivation x230
by Richard Hiltrude Feb. 22, 2026

Feb. 22, 2026

Issue #629 has been reported by Richard Hiltrude. ---------------------------------------- Bug #629: TPM Deactivation x230 https://ticket.coreboot.org/issues/629 * Author: Richard Hiltrude * Status: New * Priority: High * Category: Payloads * Target version: main * Start date: 2026-02-22 * Affected versions: main * Affected hardware: x230 ---------------------------------------- When I try to disable TPM on the x230 and turn it off, there is no option to save, only the ESC key. When I press ESC, it restarts, but when I access the TPM menu again, everything is still active! SeaBIOS 1.17.0 Perhaps there is also an error in SeaBIOS. cbmem log TPM: flags disable=0, deactivated=0, nvlocked=1 ![](https://i.ibb.co/M58XTQBN/x230.png) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #259] (Closed) T440p: Tianocore unable to boot Windows 10 (MACHINE_CHECK_EXCEPTION)
by Angel Pons Feb. 21, 2026

Feb. 21, 2026

Issue #259 has been updated by Angel Pons. Status changed from New to Closed ---------------------------------------- Bug #259: T440p: Tianocore unable to boot Windows 10 (MACHINE_CHECK_EXCEPTION) https://ticket.coreboot.org/issues/259#change-2225 * Author: Crazy Fox * Status: Closed * Priority: Normal * Assignee: Angel Pons * Category: board support * Start date: 2020-06-09 ---------------------------------------- Hi, Team! I've successfully corebooted my T440p (without dGPU) - Debian 10 works fine, but unable to boot into Windows 10 - getting BSOD with Stop Code: `MACHINE_CHECK_EXCEPTION` The same exception appears even trying to boot from Windows usb installation media. Tried different config options, tried coreboot master and v4.11/v4.12 tags with the same result There is some info about my setup: ~~~ $ git rev-parse HEAD 342a8c3b2bc0845638e852af01f3054256a8446c ~~~ ~~~ $ sudo hwinfo --cpu --short cpu: Intel(R) Core(TM) i7-4800MQ CPU @ 2.70GHz, 800 MHz ~~~ ~~~ $ cat defconfig CONFIG_LOCALVERSION="GLETA1WW (2.55)" CONFIG_USE_OPTION_TABLE=y CONFIG_TIMESTAMPS_ON_CONSOLE=y CONFIG_FW_CONFIG=y CONFIG_FW_CONFIG_SOURCE_CBFS=y CONFIG_VENDOR_LENOVO=y CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_CBFS_SIZE=0x200000 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="20AWS0VK00" CONFIG_HAVE_IFD_BIN=y CONFIG_BOARD_LENOVO_THINKPAD_T440P=y CONFIG_CONSOLE_POST=y CONFIG_PCIEXP_L1_SUB_STATE=y CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE=y CONFIG_HAVE_MRC=y CONFIG_MRC_FILE="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/mrc.bin" CONFIG_PCIEXP_CLK_PM=y CONFIG_VALIDATE_INTEL_DESCRIPTOR=y CONFIG_H8_SUPPORT_BT_ON_WIFI=y CONFIG_HAVE_ME_BIN=y CONFIG_CHECK_ME=y CONFIG_USE_ME_CLEANER=y CONFIG_HAVE_GBE_BIN=y CONFIG_ELOG=y CONFIG_USBDEBUG=y CONFIG_USBDEBUG_DONGLE_FTDI_FT232H=y CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y CONFIG_DRIVERS_PS2_KEYBOARD=y CONFIG_DEBUG_TPM=y CONFIG_TPM_RDRESP_NEED_DELAY=y CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y CONFIG_PAYLOAD_TIANOCORE=y ~~~ ---Files-------------------------------- results.log (343 KB) ntbtlog.txt (20.2 KB) IMG_20200610_131344.jpg (114 KB) IMG_20200610_132042.jpg (120 KB) IMG_20200610_132407.jpg (123 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #628] (New) mb/asus/h61-series: variant p8h61-i_r2_0 won't POST on recent coreboot version mmio / tpm range ?
by Walter Sonius Feb. 21, 2026

Feb. 21, 2026

Issue #628 has been reported by Walter Sonius. ---------------------------------------- Bug #628: mb/asus/h61-series: variant p8h61-i_r2_0 won't POST on recent coreboot version mmio / tpm range ? https://ticket.coreboot.org/issues/628 * Author: Walter Sonius * Status: New * Priority: Normal * Assignee: Patrick Rudolph * Target version: none * Start date: 2026-02-21 * Affected versions: main ---------------------------------------- Variant Asus h61-series p8h61-i_r2_0 WIP code under review: https://review.coreboot.org/c/coreboot/+/91337 Possible issue commit sb/intel/bd82x6x/lpc: Advertise all fixed MMIO ranges: https://review.coreboot.org/c/coreboot/+/91040 If this patch is applied to old coreboot codebase 25.06-77-g812d0e2f626d as a whole or on current codebase, boot will stall before POST/BOOT so no screen but machine stays powered on and hangs forever, on old codebase you seen USB poweron on current codebase you don't! SPI console log snippet loops here from old coreboot codebase, see diff at line ~470 and ~550: ``` Resource didn't fit!!! PNP: 002e.a 60 * size: 0x8 limit: fff io ``` Uploaded 3 SPI logs from old coreboot base, mmio123456 means whole patch CB:91040 applied and mmio12346 means skipped the TPM part (5th block) of that patch, the shortest named file is the one with original unpatched `lpc.c` file! ---Files-------------------------------- p8h61ir2-21-old-edk2-spilogdb-cbmem.rom.log (256 KB) p8h61ir2-21-old-edk2-spilogdb-mmio12346-cbmem.rom.log (256 KB) p8h61ir2-21-old-edk2-spilogdb-mmio123456-cbmem.rom.log (256 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #449] (New) ThinkPad T440p fail to start, continous beeping & LED blinking
by Crazy Fox Feb. 21, 2026

Feb. 21, 2026

Issue #449 has been reported by Crazy Fox. ---------------------------------------- Bug #449: ThinkPad T440p fail to start, continous beeping & LED blinking https://ticket.coreboot.org/issues/449 * Author: Crazy Fox * Status: New * Priority: Normal * Category: coreboot common code * Target version: 4.18 * Start date: 2023-01-14 * Affected versions: 4.18 * Affected hardware: haswell ---------------------------------------- Hi, Team Being corebooted before and works fine on 4.17. After flashing 4.18 my t440p wont startup (black screen, constant beeping & LED blinking). I've tried and retried different nconfigs but result is the same. I know that it is lack of information, but I need to recover the laptop first to grab some logs from it. Log from FT232H's debug is attached, the rest of info (defconfig, flashrom command etc. will upload soon) ---Files-------------------------------- coreboot_t440p_emerg.log (7.85 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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Native RAM Init: Logs of *Haswell NRI: Implement 1D margin training*
by Paul Menzel Feb. 21, 2026

Feb. 21, 2026

Dear coreboot community, Angel uploaded patchset 5 of their change-set/commit *Haswell NRI: Implement 1D margin training* [1], and shared the debug logs [2]. Great work and interesting to me. Kind regards, Paul [1]: https://review.coreboot.org/c/coreboot/+/89314 [2]: https://paste.flashrom.org/view.php?id=3808 PS: Excerpt: ``` Bit lane information Channel 0 Byte 0 1 2 3 4 5 6 7 Bit 0123456701234567012345670123456701234567012345670123456701234567 WrDqsDelay -31 ................................................................ -30 ................................................................ -29 ................................................................ -28 ................................................................ -27 ................................................................ -26 ................................................................ -25 ................................................................ -24 ................................................................ -23 ................................................................ -22 ................................................................ -21 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################################################################ 28 ################################################################ 29 ################################################################ 30 ################################################################ 31 ################################################################ C0.R0: Left Right Width Center B0: -31 11 42 -10 B1: -31 10 41 -11 B2: -31 12 43 -10 B3: -31 13 44 -9 B4: -31 12 43 -10 B5: -31 10 41 -11 B6: -31 10 41 -11 B7: -31 13 44 -9 C1.R0: Left Right Width Center B0: -25 19 44 -3 B1: -23 14 37 -5 B2: -25 16 41 -5 B3: -26 20 46 -3 B4: -25 16 41 -5 B5: -24 13 37 -6 B6: -23 17 40 -3 B7: -23 14 37 -5 ```

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