September 2025 - coreboot - mail.coreboot.org

[coreboot - Bug #439] (New) Lenovo X201 Turbo Boost not working
by Lukas Karg Nov. 17, 2025

Nov. 17, 2025

Issue #439 has been reported by Lukas Karg. ---------------------------------------- Bug #439: Lenovo X201 Turbo Boost not working https://ticket.coreboot.org/issues/439 * Author: Lukas Karg * Status: New * Priority: High * Target version: none * Start date: 2022-11-18 * Affected versions: master * Affected hardware: Lenovo X201 * Affected OS: Linux, Windows, ... ---------------------------------------- -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #601] (New) superio/nuvoton/npcd378:379 FAN issue sandy/ivy-bridge & haswell on HP
by Walter Sonius Nov. 13, 2025

Nov. 13, 2025

Issue #601 has been reported by Walter Sonius. ---------------------------------------- Bug #601: superio/nuvoton/npcd378:379 FAN issue sandy/ivy-bridge & haswell on HP https://ticket.coreboot.org/issues/601 * Author: Walter Sonius * Status: New * Priority: Normal * Assignee: Patrick Rudolph * Category: board support * Target version: main * Start date: 2025-07-05 * Affected versions: 25.03 * Affected hardware: compaq_8200_elite_sff, compaq_8300_elite_sff, compaq_pro_6300_sff, 260_g1_dm, prodesk_600_g1_sff ---------------------------------------- The NPCD378 HWM FAN control is limited to the PSU FAN only but should work for the "compaq_8200_elite_sff" according to its [commit and instruction](https://review.coreboot.org/c/coreboot/+/26050), which states "... the SuperIO has to be notified that a write is ongoing. After clearing the write-lock bit all changes are applied...". Is there a special command that I missed that "clears the write-lock" or is there a bug and is its current implementation broken? Since adjusting the nvram parameter `sudo nvramtool -w psu_fan_lvl=1-7`and doing a reboot or cold powerup does show that the nvram parameter changes (can be confirmed by coreboot log or reading the nvram parameter after boot again) it never changes the actual PSU FAN speed! Tried multiple coreboot/seabios/edk2 versions the last 3 months on 5 different HP machines and came to the following conclusion. The following nvramtool `psu_fan_lvl=values` reflect the following PWM feedback from the coreboot log: ``` =1 [INFO ] NPCD378: PSU fan PWM 0x37 =2 [INFO ] NPCD378: PSU fan PWM 0x57 =3 [INFO ] NPCD378: PSU fan PWM 0x77 =4 [INFO ] NPCD378: PSU fan PWM 0x97 =5 [INFO ] NPCD378: PSU fan PWM 0xb7 =6 [INFO ] NPCD378: PSU fan PWM 0xd7 =7 [INFO ] NPCD378: PSU fan PWM 0xf8 ``` The following 3 supported sandy/ivy bridge HP variants share the same issue that nvram parameters and coreboot log show the requested manual `psu_fan_lvl` values but its PSU FAN speed won't change according to these values, atleast its FANs keep spinning after post/boot on these machines: ``` VALUE FAN SPEED compaq_8200_elite_sff NPCD378 adjusts remains same compaq_8300_elite_sff NPCD379 adjusts remains same compaq_pro_6300_sff NPCD379 adjusts remains same ``` The following 2 yet uncommited HP Haswell coreboot variants, "HP 260 G1 DM (Desktop Mini) Business PC" and "HP Prodesk 600 G1 SFF" both come with a NPCD379 and both share the same issue with the former 3 variants that the `psu_fan_lvl` value's can be adjusted by nvramtool(if cmos backend is added to the code) and verified during boot or nvramtool that these values have changed with affecting the PSU FAN speed in a undesired way: ``` VALUE FAN SPEED 260_g1_dm NPCD379 adjusts stops spinning prodesk_600_g1_sff NPCD379 adjusts stops spinning ``` These 2 Haswell machines will halt "and stop spinning" the PSU FAN as soon as during post the "PSU fan PWM" value kicks in!!! A side note is needed for the HP 260 G1 DM since it only has a single FAN, so I'm not sure if its CPU or its PSU FAN technically and its OEM BIOS misses a option the adjust FAN speed compared to the other 4 HP models! Another side note for the Prodesk 600 G1 SFF is that I'm forced to use a aftermarket non HP CPU FAN(old Intel CPU FAN), but it keeps spinning after coreboot post. Removing the FAN/HWM code from the superio NPCD378 source, leads to the opposite it will force the PSU FAN to its MAXIMUM speed after poweron but atleast keeps the FAN spinning. This maximum forced full speed FAN behaviour can also be replicated by removing one of the 4 FAN wires, red or white cable not sure anymore. Interesting FAN notes: In case of the "Prodesk 600 G1", swapping its PSU with the PSU from the "compaq_8300_elite_sff" keeps the PSU fan spinning during and after coreboot post but it will still not adjust its PSU FAN speed to its requested values! Also the other way around, putting the PSU of the "Prodesk 600 G1" inside the "compaq_8300_elite_sff" stops the PSU FAN during coreboot post, but running the OEM firmware, keeps the fan spinning and let it adjust to all requested values on its donor FAN. So it seems there is a certain PWM compatibility to control these FAN's in similar ways between these boards. It seems the the newer PSU FAN from the Haswell generation can actually disable / stop spinning on a certain PWM value while older FAN keep spinning on these lower/ same PWM values. Compared to the [initial support commit](https://review.coreboot.org/c/coreboot/+/26050) by Patrick Rudolph, around April 2021 there were some [code](https://review.coreboot.org/c/coreboot/+/52511) [fixes](https://review.coreboot.org/c/coreboot/+/52671) but after that the last time this `psu_fan_lvl` code was verified functional was between 2023-05-02 and 2023-07-03 noted in the [boardsupport commit](https://review.coreboot.org/c/coreboot/+/74906) of the variant `compaq_8300_elite_sff_usdt` by Riku Viitanen. History for "coreboot/src/superio/nuvoton/npcd378" shows [6 patches](https://github.com/coreboot/coreboot/commits/main/src/superio/nuvo… from november 2023 till today. Any tips hints welcome. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #592] (New) Lenovo M920q can't use DIMM2 RAM slot
by Coreboot Enjoyer Nov. 8, 2025

Nov. 8, 2025

Issue #592 has been reported by Coreboot Enjoyer. ---------------------------------------- Bug #592: Lenovo M920q can't use DIMM2 RAM slot https://ticket.coreboot.org/issues/592 * Author: Coreboot Enjoyer * Status: New * Priority: Normal * Category: coreboot common code * Target version: none * Start date: 2025-04-15 * Affected versions: main * Related links: https://github.com/Thrilleratplay/coreboot-builder-scripts/issues/33 Also, it looks like a similar issue to https://ticket.coreboot.org/issues/462 * Affected hardware: Lenovo M920q ---------------------------------------- Building the current coreboot source, as well as commits 497298708c330deb479fbf3ee6a3acc8bff2a102, 640a41f3ee938b794b140218921e0fd63b1d9235 and 7945a31e9172ec2939cc1abc6036962a6efb601b, produces the firmware, that allows to initialize the motherboard if only DIMM1 RAM slot is filled. It fails to initialize, if DIMM1 RAM slot is empty and DIMM2 is filled, as well as if both DIMM1 and DIMM2 are filled. The issue is reproducible with different RAM sticks. I tried every possible combination with Kingston 32GB (2666MHz, CL 19-19-19-43) and Samsung 8GB (2400MHz, CL 17-17-17-39) -- the motherboard recognizes RAM sticks correctly, but still fails when the DIMM2 is filled with any RAM stick. I have also attached the build config file, which uses most of the default options. ---Files-------------------------------- m920q-dimm2-config.txt (27.6 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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coreboot Meetings Announcement And Agenda Call
by mina＠coreboot.org Sept. 29, 2025

Sept. 29, 2025

Dear coreboot Community, Please be reminded that our upcoming leadership meetings for both the early GMT and late GMT time zones are scheduled for Wednesday, October 1, 2025. [1] Kindly take a moment to update the agenda items with issues you'd like to discuss during these meetings. [2] Thank you. ## Current Agenda Items * No active issues on the agenda yet. [1](https://coreboot.org/calendar.html) [2](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkK…

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Asus (AMI) vendor firmware reversing: what does HDA?
by Keith Hui Sept. 24, 2025

Sept. 24, 2025

I'm looking for some tips here. Anyone know which module in an AMI Aptio UEFI initializes HD Audio codecs? I'm doing all this on my p8z77-v_le_plus. My hope is, once I find the module responsible, I can quickly inspect that module in every board in the family and build a correct hda_verb.c for each without actually having one on hand to run autoport on. I'm now able to extract the VBT and USB port configurations straight from vendor firmware image. And if it does something special with its onboard devices, I know which module to load into Ghidra for a deeper look after blowing it apart with uefiextract. However, I'm not yet able to find the part of the firmware that initializes the HDA codec. Based on the two boards I actually own and brought into coreboot, there are setup options within the firmware that touch on the codec, and it certainly is involved on their bringup. One involves the front audio panel and whether a HD Audio or AC97 panel is connected. The setup variables are stored in EFI variable "Setup" with GUID EC87D643-EBA4-4BB5-A1E5-3F3E36B20DA9. There are usually three HDA settings: A main enable, HDA/AC97 front panel selection, and sometimes a SPDIF/HDMI selection. I found their offset within Setup, but I can't find the module that reads the variable(s) and act on them. Currently I use binwalk to scan all the extracted "body.bin" for "Setup" in unicode and try to find those with both signatures, to load them into Ghidra one by one. I'm looking for hints to make the process faster or narrow my scope. Thanks Keith

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2025_09_24 coreboot Group Review Session
by mina＠coreboot.org Sept. 22, 2025

Sept. 22, 2025

Hello coreboot, Kindly note that we have an upcoming group review session scheduled for Wednesday, September 24. https://meet.google.com/kpu-yozw-gtt Check the coreboot calendar for the time in your timezone: https://coreboot.org/calendar.html Find the link to the list of patches to be reviewed this week here: (https://docs.google.com/spreadsheets/d/1io-tewVlkX3PAkhR9ttCKjJXiXR9Emy6qsY…) Please add any specific patches you'd like the group to review to the top of the sheet. Since an hour may not be sufficient to address all patches on the list, reviewing patches in advance is greatly appreciated. Thank you. Best regards, Mina.

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[coreboot - Support #610] (New) Coreboot on TGL
by Muhammad Ammar Sept. 19, 2025

Sept. 19, 2025

Issue #610 has been reported by Muhammad Ammar. ---------------------------------------- Support #610: Coreboot on TGL https://ticket.coreboot.org/issues/610 * Author: Muhammad Ammar * Status: New * Priority: Normal * Category: build system * Target version: none * Start date: 2025-09-18 ---------------------------------------- Hi We have developed a custom board using tgl up3 processor. Uptil now we were building slimbootloader for checking all interfaces. We were successful with all peripherals except audio codec which is connected via soundwire interface and that support is not present in slimbootloader. Hence we decided to shift to coreboot. The issue we are facing is that in slimbootloader we stitch the bios bin with the IFWI (Gbe Me etc) and create a FULL image that is flashed on board. However, with coreboot only the bios is generated and we dont have any rom.layout for our custom board. I havent yet tried Flashing the bios image generated with coreboot as it is. As it may fail without the IFWI image. Could you help us out in our initial setup. Any help would be greatly appreciated. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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2025-09-17 - coreboot Leadership Meetings Minutes
by mina＠coreboot.org Sept. 18, 2025

Sept. 18, 2025

# 2025-09-17 - coreboot Leadership Meetings ## Open Action Items * 2024-11-27 * [Open] Send out poll with regards to LLM usage (requested by SFC) * 2024-10-30 * [Open] Add clarification to docs: “Do not use gerrit change-id or CB: format in reference to already-merged patches.” * 2024-10-16 * [Open] Matt: Set up a meeting to discuss board status alternatives and send out invites. * Decouple data collection with uploading * Require gerrit credentials or other auth to push * Json format? * https://github.com/chrultrabook/linux-tools/blob/main/debugging.sh * 2024-09-18 * [Open] Jon:Schedule a dedicated meeting to discuss the Coverity defects and action plan. * Werner: Send out an invite for the meeting. Sent out a poll to find a time slot: https://rallly.co/invite/1c8J3azXAcje * 2024-05-01 * [Open] Nick Van Der Harst volunteered for Dutch. "Gogo gogo" would like to translate to Russian (?). * 2024-01-10 * Nico: (https://review.coreboot.org/q/topic:enforce_region_api) * [Open] Daniel: Look at how we want to localize (non-console) strings for coreboot. Long-term project. ## Announcements & Events * OSFC 2025 Dates: October 7–10, 2025 # Late GMT Leadership Meeting Minutes ## Attendees Mina Asante, Werner Zeh, Julius Werner, Alicja Michalska, Martin Roth, Karthik R, Matt DeVillier, David Hendricks, Maximilian Brune, Jon Murphy. ## Minutes ### Discuss the early meeting agenda. ### The coreboot 25.09 release is next week. * The release is scheduled for Thursday, September 25. ### openSFI - Please review and consider attending meetings and contributing: * (https://www.youtube.com/live/1CE6olXT604) * (https://docs.google.com/document/d/1Y7zZQa3NA6LjjShRZzVksMPGMYJh1qcc/edit) # Early GMT Leadership Meeting Minutes ## Attendees Mina Asante, Ziang Wang, Werner Zeh. ## Minutes ### [Ziang] To raise coreboot ACPI support for QEMU RISC-V virt as a project in the RISC-V Software Ecosystem (RISE) community (require RISE membership for link below): (https://lf-rise.atlassian.net/wiki/spaces/HOME/pages/8589425/Firmware+Proje…) * Project Update: project is well accepted by the community, and a new tracker has been established: (https://lf-rise.atlassian.net/wiki/spaces/HOME/pages/661585922/COREBOOT_00_…) # Next Leadership Meetings Date * October 1, 2025. * [coreboot Calendar](https://coreboot.org/calendar.html). # Notice Decisions shown here are not necessarily final and are based on the current information available. If there are questions or comments about decisions made, or additional information to present, please put it on the leadership meeting agenda and show up if possible to discuss it. Of course items may also be discussed on the mailing list, but as it's difficult to interpret tone over email, controversial topics frequently do not have good progress in those discussions. For particularly difficult issues, it may be best to try to schedule another meeting. We now host two leadership meetings, one in early GMT and one in late GMT, to better accommodate participants from the Asian time zones. Kindly note that both sessions use the same meeting notes and Google Meet link. # coreboot Leadership Meeting Notes https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgK…

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coreboot Meetings Announcement And Agenda Call
by mina＠coreboot.org Sept. 15, 2025

Sept. 15, 2025

Dear coreboot Community, Please be reminded that our upcoming leadership meetings for both the early GMT and late GMT time zones are scheduled for Wednesday, September 17, 2025. [1] Kindly take a moment to update the agenda items with issues you'd like to discuss during these meetings. [2] Thank you. ## Current Agenda Items * No active issues on the agenda yet. [1](https://coreboot.org/calendar.html) [2](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkK…

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[coreboot - Bug #518] make xconfig - g++: fatal error: no input files
by Dmytro Aleksandrov Sept. 12, 2025

Sept. 12, 2025

Issue #518 has been updated by Dmytro Aleksandrov. James Feeney wrote: > $ git rev-parse HEAD > 62c25351c101a3d5c7104aa6fc34e71990478dde > Arch Linux > make 4.4.1-2 > > $ make -d xconfig > ... > Found '/sdb/coreboot.main/util/kconfig/qconf.cc'. > ... > No implicit rule found for '/sdb/coreboot.main/util/kconfig/qconf.cc'. > ... > Finished prerequisites of target file 'build/util/kconfig/qconf.o'. > Must remake target 'build/util/kconfig/qconf.o'. > /sdb/coreboot.main/util/kconfig/Makefile.inc:63: update target 'build/util/kconfig/qconf.o' due to: target does not exist > ... > g++: fatal error: no input files > compilation terminated. > ... https://review.coreboot.org/c/coreboot/+/89006 The issue was fixed and merged into mainline. You can now configure using qconf UI. ---------------------------------------- Bug #518: make xconfig - g++: fatal error: no input files https://ticket.coreboot.org/issues/518#change-2148 * Author: James Feeney * Status: New * Priority: Normal * Category: build system * Target version: none * Start date: 2023-12-07 * Affected versions: 4.21 ---------------------------------------- $ git rev-parse HEAD 62c25351c101a3d5c7104aa6fc34e71990478dde Arch Linux make 4.4.1-2 $ make -d xconfig ... Found '/sdb/coreboot.main/util/kconfig/qconf.cc'. ... No implicit rule found for '/sdb/coreboot.main/util/kconfig/qconf.cc'. ... Finished prerequisites of target file 'build/util/kconfig/qconf.o'. Must remake target 'build/util/kconfig/qconf.o'. /sdb/coreboot.main/util/kconfig/Makefile.inc:63: update target 'build/util/kconfig/qconf.o' due to: target does not exist ... g++: fatal error: no input files compilation terminated. ... -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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