June 2025 - coreboot - mail.coreboot.org

[coreboot - Support #597] (New) success mb/dell: OptiPlex 5040 SFF works with adjusted Optiplex 3050 Micro code port
by Walter Sonius July 8, 2025

July 8, 2025

Issue #597 has been reported by Walter Sonius. ---------------------------------------- Support #597: success mb/dell: OptiPlex 5040 SFF works with adjusted Optiplex 3050 Micro code port https://ticket.coreboot.org/issues/597 * Author: Walter Sonius * Status: New * Priority: Normal * Category: board support * Target version: none * Start date: 2025-05-19 * Affected versions: 25.03 ---------------------------------------- Not sure to put this under support or refactoring, since adding this code to upstream coreboot using gerrit may look straight forward and easy to have a nice working optiplex_5040 port. My concern is however that the original `dell/optiplex_3050` code might need to be refactored into a variant first before this code will be accepted and that refactoring may be to much for me as a newbie. But it works... it works really well indeed. By mostly reusing `dell/optiplex_3050` port code which takes care of handling some variants 'SFF/MICRO' hinted by 'ramstage.c' for its own 3050 series itself, I just reused all of the code which I mostly don't understand and therefor may be wrong to put that as NEW board into the code tree. Although I have 'autoport logs' made for my 'optiplex_5040_sff' I don't know how to translate/apply correct that to my model(if needed). But since you have to start somewhere, and autoport only made logs I therefor just want to share this code and progress. Specs: Dell Optiplex 5040 SFF Motherboard: DP/N 0T7D40, CN-0T7D40-72200, 588-00HF-A00 OEM BIOS version: 1.22.0 03/16/2022 Reg Model: D11S Reg Type: D11S001 Service tag: HPR6C92 CPU: i3-6100 This Optiplex 5040 SFF motherboard looks very similar to the 3050 SFF(shares the same OEM BIOS as the 3050 micro) except for the following visual differences: 4 DDR3L slots vs 2 DDR4 slots (DDR4-sodimm on the micro) 1 PCIe 4x length (open) black slot vs 1x length (closed), micro none 3 SATA connectors vs 2 SATA (black missing), micro one 4 USB3 back ports vs 2 USB3 2 DisplayPorts vs 1 DisplayPort 1 serial vs 0 serial port 1 VGA(using motherboard header) vs 0 VGA 2 PS2 vs 0 PS2 ports Q170 chipset vs B250 chipset First the initial deguard requirement was the same for my optiplex_5040 sff as for the optiplex_3050 micro, as well as flashing or recovery. A minor edit to the [deguard code](https://ticket.coreboot.org/issues/588) is necessary to complete the deguard instruction. With the following crucial edits to the 'optiplex_3050' port its 'Kconfig', 'romstage.c' and minor edits to the existing 'devicetree.cb' almost everything started working: First hang on RAM issue ["[EMERG] FspMemoryInit error, status=0x80000007"](https://ticket.coreboot.org/issues/594) was fixed by adjusting 'Kconfig' `config DIMM_SPD_SIZE` from `default 512 # DDR4` to `256 # DDR3` and editing 'romstage.c' with additional addresses and changing `CaVrefConfig 2` to `0` made all 4 DIMM slots work: ``` > struct spd_block blk = { .addr_map = { 0x50, 0x51, 0x52, 0x53 } }; mem_cfg->DqPinsInterleaved = 1; > mem_cfg->CaVrefConfig = 0; mem_cfg->MemorySpdDataLen = blk.len; > mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; > mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; > mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; > mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; ``` By some additional edits to 'devicetree.cb' all PCIe slots(16x,4x,M2-ssd), all USB2&3 ports, all SATA ports and both PS2 ports started to function. Only the USB OC values have my concern, don't know what they stand for. ``` > # SLOT2 x16 > device ref peg0 on > register "Peg0MaxLinkWidth" = "Peg0_x16" > > # Configure PCIe clockgen in PCH > register "PcieRpClkReqSupport[0]" = "1" > register "PcieRpClkReqNumber[0]" = "0" > register "PcieRpClkSrcNumber[0]" = "0" > end > --- > device ref south_xhci on > register "usb2_ports" = "{ > [0] = USB2_PORT_MID(OC0), // Front panel (blue) > [1] = USB2_PORT_MID(OC0), // Front panel (blue) > [2] = USB2_PORT_MID(OC3), // Back panel (blue) > [3] = USB2_PORT_MID(OC2), // Back panel (blue) > [4] = USB2_PORT_MID(OC1), // Back panel (blue) > [5] = USB2_PORT_MID(OC1), // Back panel rightup (black) > [6] = USB2_PORT_MID(OC1), // Back panel (blue) > [7] = USB2_PORT_MID(OC1), // Back panel rightlow (black) > [8] = USB2_PORT_MID(OC_SKIP), // Front Panel rightlow (black) > [9] = USB2_PORT_MID(OC_SKIP), // Front Panel rightup (black) > > }" > register "usb3_ports" = "{ > [0] = USB3_PORT_DEFAULT(OC0), // Front panel (blue) > [1] = USB3_PORT_DEFAULT(OC0), // Front panel (blue) > [2] = USB3_PORT_DEFAULT(OC2), // Back panel (blue) > [3] = USB3_PORT_DEFAULT(OC2), // Back panel (blue) > [4] = USB3_PORT_DEFAULT(OC1), // Back panel (blue) > [5] = USB3_PORT_DEFAULT(OC1), // Back panel (blue) > }" > end --- > register "SataPortsEnable[1]" = "1" > register "SataPortsEnable[2]" = "1" --- < device ref pcie_rp21 on < register "PcieRpClkReqSupport[20]" = "1" < register "PcieRpClkReqNumber[20]" = "3" < register "PcieRpAdvancedErrorReporting[20]" = "1" < register "PcieRpLtrEnable[20]" = "true" < register "PcieRpClkSrcNumber[20]" = "3" < register "PcieRpHotPlug[20]" = "1" < end < < # Realtek LAN < device ref pcie_rp5 on < register "PcieRpClkReqSupport[4]" = "0" < register "PcieRpHotPlug[4]" = "0" < end < < # M.2 WiFi < device ref pcie_rp8 on < register "PcieRpClkReqSupport[7]" = "0" < register "PcieRpHotPlug[7]" = "1" --- > # SLOT3_M.2 > device ref pcie_rp17 on > register "PcieRpClkReqSupport[16]" = "1" > register "PcieRpClkReqNumber[16]" = "3" > register "PcieRpAdvancedErrorReporting[16]" = "1" > register "PcieRpLtrEnable[16]" = "true" > register "PcieRpClkSrcNumber[16]" = "3" > register "PcieRpHotPlug[16]" = "1" > end > > # SLOT1 x4 > device ref pcie_rp9 on > register "PcieRpClkReqSupport[8]" = "0" > register "PcieRpHotPlug[8]" = "1" > end --- > device pnp 2e.1 on # 8042 > io 0x60 = 0x60 > irq 0x0f = 0 > irq 0x70 = 1 > irq 0x72 = 12 > end --- > chip drivers/pc80/tpm > device pnp 0c31.0 on end > end --- > device ref gbe on end ``` Also TPM2 and onboard ethernet came alive with final edits to 'Kconfig': ``` > select MAINBOARD_HAS_TPM2 > select MEMORY_MAPPED_TPM > select MAINBOARD_USES_IFD_GBE_REGION ``` All audio ports including chassis speaker(soundcard) work using unchanged optiplex_3050 code, however autoport logs ran on OEM show different codec(chipset) and parameters for the 5040_sff compared to 3050 micro this may need to be alterned for correctness? Video output was unreliable until I replaced 'data.vbt' with the one extracted from original Dell Optiplex 5040 SFF 1.22 OEM bios (debugfs) and altered 'gma-mainboard.ads' to have HDMI and 2 DisplayPorts working perfectly. Only the VGA port, which is shown as 3rd DisplayPort (xrandr) uses the original motherboard breakout to the chassis VGA won't work at all (port not detected no BOOT nor OS). ``` ports : constant Port_List := (HDMI1, -- External HDMI DP2, -- External DP (bottom) DP1, -- External DP (top) DP3, -- External VGA (opt. breakout cable) others => Disabled); ``` Tested this on coreboot-25.03-519-ga2010cf5eeea both SeaBIOS 1.16.3 and EDK2 MrChromeBox 2502 payloads booting KDE NEON Linux 6.11 fine. Besides the "VGA port" only "Wake for LAN" isn't working for me yet every other port/connection/slot does work even combined iGPU and dGPU, leds, and CPU Fan speed also varies boot/restart. My concern is with the USB OC values, allot of GPIO values copied from the 3050 port and not correct to autoport and other stuff I might overlook. Feel free to check the added drop in optiplex_5040_sff.zip file with mostly a copy of 3050 micro port code to build a functional optiplex_5040_sff target or spin a variant into gerrit which I can assist and confirm testing. ---Files-------------------------------- autoport-corebooted-dell_optiplex_5040_sff.zip (208 KB) autoport-OEM122-dell_optiplex_5040_sff-deguard.zip (419 KB) optiplex_5040_sff.zip (14 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Support #581] (New) success new variant "compaq_pro_6300_sff" for hp/snb_ivb_desktops compatible with "compaq_8300_elite_sff" template
by Walter Sonius July 8, 2025

July 8, 2025

Issue #581 has been reported by Walter Sonius. ---------------------------------------- Support #581: success new variant "compaq_pro_6300_sff" for hp/snb_ivb_desktops compatible with "compaq_8300_elite_sff" template https://ticket.coreboot.org/issues/581 * Author: Walter Sonius * Status: New * Priority: Normal * Category: board support * Target version: none * Start date: 2025-03-15 ---------------------------------------- Successful flash and coreboot SeaBIOS functioning of a HP "compaq_pro_6300_sff" with a unchanged "compaq_8300_elite_sff" template using coreboot (24.12-758-g1e7ba810c6bb) and SeaBIOS (version rel-1.16.3-0-ga6ed6b70). These two HP Compaq devices are extremely similar, they use the same OEM proprietary BIOS upgrade files. Hardware wise the only 3 noticeable differences are that the "compaq_8300_elite_sff" comes with a Q77 chipset, SuperIO NPCD378 and J32 labeled 16x length "white" PCI-E slot versus a Q75 chipset, SuperIO NPCD379HAKFX with the J32 labeled slot populated with a limited physical 1x length "black" PCI-E slot on the "compaq_pro_6300_sff". Flashing from OEM proprietary BIOS 3.08revA enabling the FDO jumper on the motherboard as described for the compaq_8300_elite_sff works by booting with "iomem=relaxed" kernel parameter and specifying the specific 16MB chip 25Q128A: flashrom -p internal -w cbtest.rom -c "MT25QL128" Tested and Working: Poweron/Poweroff/Reboot CPU i3-3220 / e3-1225v2 RAM 1x 2x 4x populated slots total of 4GB/8GB/16GB/24GB (both 1.35v and 1.5v modules mixed with ECC) Serial port (including coreboot) PS2 keyboard (including SeaBIOS) PS2 mouse SATA 3 ports (blue/white/white) USB 2.0 4x front & 2x back ports USB 3.0 4x back ports Ethernet 1Gbit/100Mbit Display port works in SeaBIOS and OS VGA port only works in OS! PCI using realtek RTL8169 1Gb PCIE 3.0 16x using 2.0 8x 10Gb intel X540-AT2 / using 1.0 16x Nvidia Geforce 6200 LE (also works in SeaBIOS) PCIE 2.0 1x using 2.0 1x 2.5Gb realtek RTL8125 PCIE 2.0 1x using 1.0 1x 1Gb intel 82574L (SeaBIOS loads option rom) Audio built-in speaker (plays music in OS compared to legacy bleep pc-speaker) Audio front panel 3.5 mm headphone jack (auto disables built-in Speakers and selects Headphones) Audio front panel 3.5 mm headphone&mic jack (only microphone works with 4 pin 3.5mm combi mic/headphone) Audio back panel 3.5mm green jack (manually select Line Out and it works) Sensors CPU and 2 motherboard sensors SuperIO Booting USB / SATA(HDD/DVD) OS: Fedora-mate Linux kernel 6.11.4 / 6.13.6, KDE neon Linux kernel 6.8.0-52 Flashrom: needs additional parameters compared to OEM BIOS both for read/write depending on flashrom version? flashrom -p internal:boardmismatch=force,ich_spi_mode=hwseq -w test.rom -c "Opague flash chip" Tested not Working: RAM ECC functioning (see coreboot log) SATA port black Wakeonlan, it just auto wakes from itself so cannot verify... iGPU multigpu with PCIE nvidia geforce 6200 le, only PCIE nvidia geforce works and iGPU gets disabled. What to do next to get this "compaq_pro_6300_sff" variant officially supported? *Supply more logs/info? *Fill a bug for the ECC not working or first get this variant supported as is? *Fill a bug that VGA doesn't work in SeaBIOS? *Fill a bug/ticket on the flashrom support list for the difference in parameters needed pre/post flash? https://support.hp.com/us-en/drivers/hp-compaq-pro-6300-small-form-factor-p… https://support.hp.com/in-en/drivers/hp-compaq-elite-8300-small-form-factor… Walter Sonius ---Files-------------------------------- cb-log-hp-compaq_pro_6300_sff.txt (51.8 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #596] (New) Allocate resources from top down AND extend PCIe resource window above 4G together breaks libgfxinit bootscreen
by Walter Sonius July 5, 2025

July 5, 2025

Issue #596 has been reported by Walter Sonius. ---------------------------------------- Bug #596: Allocate resources from top down AND extend PCIe resource window above 4G together breaks libgfxinit bootscreen https://ticket.coreboot.org/issues/596 * Author: Walter Sonius * Status: New * Priority: Normal * Target version: none * Start date: 2025-05-19 * Affected versions: 25.03 ---------------------------------------- When enabling both `Allocate resources from top down` [enabled by default and fixed recently](https://review.coreboot.org/c/coreboot/+/87504) and `Extend resource window for PCIe devices above 4G` libgfxinit will break during bootscreen and other PCIe issues like failing wifi drivers may occur. Tested coreboot-25.03-519-ga2010cf5eeea (a2010cf5eeea6ad4a154cfb13760092f0865af3f) with Dell_Optiplex_5040_sff (i3-6100) and earlier Coreboot 25.03-467-gf0ad05b57ebe with Lenovo [x201](https://ticket.coreboot.org/issues/548#note-10) with MrChromeBox EDK2 2502. Can/should these 2 options be used together, if I understand correctly when using a modern efi GOP dGPU together with resizeable-bar all 3 options(+Support PCIe Resizable BARs) need to be enabled? Only using `Allocate resources from top down` or `Extend resource window for PCIe devices above 4G` does not lead up to this issue. ---Files-------------------------------- cb-log-dell-5040-sff-notd-a4b-ok-bootscreen.txt (41 KB) cb-log-dell-5040-sff-td-noa4b-ok-bootscreen.txt (41 KB) cb-log-dell-5040-sff-td-a4b-no-bootscreen.txt (40.5 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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2025_07_02 coreboot Review Session
by mina＠coreboot.org July 1, 2025

July 1, 2025

Hello coreboot, Kindly note that we have an upcoming group review session scheduled for Wednesday, July 2, 2025. https://meet.google.com/kpu-yozw-gtt Check the coreboot calendar for the time in your timezone: https://coreboot.org/calendar.html Here is the link to the list of patches to be reviewed this week: (https://docs.google.com/spreadsheets/d/1io-tewVlkX3PAkhR9ttCKjJXiXR9Emy6qsY…) Please add any specific patches you'd like the group to review to the top of the sheet. Since an hour is not sufficient to address all patches on the list, reviewing patches in advance is greatly appreciated. Thank you. Best regards, Mina.

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coreboot 25.06 has been tagged
by coreboot org June 28, 2025

June 28, 2025

Hi all, I wanted to announce that the coreboot 25.06 release has been tagged in the git repo. Over the next week, we'll be doing the final testing of the release. If all goes well, we plan to make the announcement for the 25.06 release on the coreboot blog on July 4th. Thanks to everyone who made this possible. Martin

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2025-06-25 - coreboot Leadership Late GMT Meeting Minutes
by mina＠coreboot.org June 26, 2025

June 26, 2025

# 2025-06-25 - coreboot Leadership Meeting late GMT ## Attendees Mina Asante, Werner Zeh, Kilian Krause, Ziang Wang, Alicja Michalska, Jay Talbott, Maximilian Brune, Martin Roth, Julius Werner, David Hendricks. ## Open Action Items * 2025-05-14 * [Open] Martin: Review the list of people with +2 rights and update it before the next release. * 2024-11-27 * [Open] Send out poll with regards to LLM usage (requested by SFC) * 2024-10-30 * [Open] Add clarification to docs, “do not use gerrit change-id or CB: format in reference to already-merged patches.” * 2024-10-16 * [Open] Matt: Set up a meeting to discuss board status alternatives and send out invites. * Decouple data collection with uploading * Require gerrit credentials or other auth to push * Json format? * https://github.com/chrultrabook/linux-tools/blob/main/debugging.sh * 2024-09-18 * [Open] Jon: Schedule a dedicated meeting to discuss the Coverity defects and action plan. * Werner: Send out an invite for the meeting. Sent out a poll to find a time slot: https://rallly.co/invite/1c8J3azXAcje * 2024-05-01 * [Open] Nick Van Der Harst volunteered for Dutch. "gogo gogo" would like to translate to Russian(?) * 2024-01-10 * Nico: (https://review.coreboot.org/q/topic:enforce_region_api) * [Open] Daniel: Look at how we want to localize (non-console) strings for coreboot. Long-term project. ## Minutes ### [Martin] Which one of the existing channels are we using as the “official” coreboot channel. Slack, discord, irc? * This discussion came up at the 05-28 - coreboot Leadership Meeting where we all seemed to agree with Werner’s suggestion to use one of our existing communities rather than creating a new one. But we couldn’t decide which of the existing channels to use so I thought to bring it up again. * Max: Do we need anything official * Werner/martin: The issue is that people mention things in whichever they use. We’re missing issues because communication is split across the various communication channels. * Set up a poll to see what people use. * IRC/Slack/Discord/Google chat/Mailing list/Matrix * Wermer: When we make the poll - please describe the issue we’re trying to solve ### [Martin] Asia Meeting Time Again * What we have figured out and what we are still working on. * Picked a time: 2:00 pm china time, 7:00 am Germany, and 5:00 am GMT * Keep meeting minutes in this document * Create AM/PM meeting - label with gmt time zones. * Send out invitation * Set up meeting with coreboot accounts * Start 4 weeks from now. * Same day and week as the current meeting. ### [David] Vendor branches/repos * Did we have a doc about this? Paul was asking recently. * Martin will write a doc **Information:** * Release was delayed due to travel. Should be done this friday (June 27) # Next Leadership Meeting * July 9, 2025. * [coreboot Calendar](https://coreboot.org/calendar.html). # Notice Decisions shown here are not necessarily final and are based on the current information available. If there are questions or comments about decisions made, or additional information to present, please put it on the leadership meeting agenda, and show up if possible to discuss it. Of course, items may also be discussed on the mailing list, but as it's difficult to interpret tone over email, controversial topics frequently do not have good progress in those discussions. For particularly difficult issues, it may be best to try to schedule another meeting. # coreboot leadership meeting minutes https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgK…

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coreboot Meetings Announcement And Agenda Call
by mina＠coreboot.org June 23, 2025

June 23, 2025

Dear coreboot Community, Kindly note that our upcoming leadership meeting is scheduled for Wednesday, June 25, 2025. [1] Please update the agenda with issues you wish to see addressed during the meeting. [2] Thank you. Best regards, Mina Asante. [1](https://coreboot.org/calendar.html) [2](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkK…

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OSFF Funding for Open-Source Work
by Christian Walter June 21, 2025

June 21, 2025

Hi all, I just want you to be aware of that the Open-Source Firmware Foundation is giving out Micro-Funding (up to 5000 EUR) for open-source work. If you got anything that you like some funding for, feel free to apply. Short application with the key information is good enough! https://opensourcefirmware.foundation/funding/small-scale-high-impact-firmw… Looking forward for feedback! Best, Chris -- *Christian Walter* *Head of Firmware Development / Cyber Security * 9elements GmbH, Kortumstraße 19-21, 44787 Bochum, Germany Email: christian.walter(a)9elements.com Phone: _+49 234 68 94 188 <tel:+492346894188>_ Mobile: _+49 176 70845047 <tel:+4917670845047>_ Sitz der Gesellschaft: Bochum Handelsregister: Amtsgericht Bochum, HRB 17519 Geschäftsführung: Sebastian Deutsch, Eray Basar Datenschutzhinweise nach Art. 13 DSGVO <https://9elements.com/privacy>

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[coreboot - Bug #600] (New) [Intel Eaglestream platform ]PCH HSIO bifurcation.
by guo deng June 21, 2025

June 21, 2025

Issue #600 has been reported by guo deng. ---------------------------------------- Bug #600: [Intel Eaglestream platform ]PCH HSIO bifurcation. https://ticket.coreboot.org/issues/600 * Author: guo deng * Status: New * Priority: Normal * Target version: 25.03 * Start date: 2025-06-21 * Due date: 2025-06-30 * Affected versions: 25.03 * Needs backport to: 25.03 * Related links: Please refer to the following linker which is about the intel eaglestream platform CRB board in Coreboot. https://github.com/coreboot/coreboot/tree/main/src/mainboard/intel/archerci… * Affected hardware: [Intel Eaglestream platform ] * Affected OS: NONE ---------------------------------------- [Intel Eaglestream platform ] I have already checked the coreboot code , but I can't find any code about how to configure the PCH HSIO pcie bifurcation by Intel FSP ? Please refer to the following linker which is about the intel eaglestream platform CRB board in Coreboot. ( https://github.com/coreboot/coreboot/tree/main/src/mainboard/intel/archerci… ) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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New branch *dev_bd*
by Paul Menzel June 20, 2025

June 20, 2025

Dear coreboot folks, I think, it’s hidden in the leadership meeting minutes [1], but still, it’d be nice to have an announcement on the list about the new branch *dev_bd*, as it shows up for people doing `git remote update` and also in the Gerrit interface. I assume *dev_bd* abbreviates *development* and *ByteDance*. Is review welcomed for changes targeting this branch? For people not wanting to see this in the Gerrit interface, do you have hints how to hide it? Anyway, it’s great to see upstream work from ByteDance! Kind regards, Paul [1]: https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgK…

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