June 2025 - coreboot - mail.coreboot.org

[coreboot - Bug #439] (New) Lenovo X201 Turbo Boost not working
by Lukas Karg Nov. 17, 2025

Nov. 17, 2025

Issue #439 has been reported by Lukas Karg. ---------------------------------------- Bug #439: Lenovo X201 Turbo Boost not working https://ticket.coreboot.org/issues/439 * Author: Lukas Karg * Status: New * Priority: High * Target version: none * Start date: 2022-11-18 * Affected versions: master * Affected hardware: Lenovo X201 * Affected OS: Linux, Windows, ... ---------------------------------------- -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #592] (New) Lenovo M920q can't use DIMM2 RAM slot
by Coreboot Enjoyer Nov. 8, 2025

Nov. 8, 2025

Issue #592 has been reported by Coreboot Enjoyer. ---------------------------------------- Bug #592: Lenovo M920q can't use DIMM2 RAM slot https://ticket.coreboot.org/issues/592 * Author: Coreboot Enjoyer * Status: New * Priority: Normal * Category: coreboot common code * Target version: none * Start date: 2025-04-15 * Affected versions: main * Related links: https://github.com/Thrilleratplay/coreboot-builder-scripts/issues/33 Also, it looks like a similar issue to https://ticket.coreboot.org/issues/462 * Affected hardware: Lenovo M920q ---------------------------------------- Building the current coreboot source, as well as commits 497298708c330deb479fbf3ee6a3acc8bff2a102, 640a41f3ee938b794b140218921e0fd63b1d9235 and 7945a31e9172ec2939cc1abc6036962a6efb601b, produces the firmware, that allows to initialize the motherboard if only DIMM1 RAM slot is filled. It fails to initialize, if DIMM1 RAM slot is empty and DIMM2 is filled, as well as if both DIMM1 and DIMM2 are filled. The issue is reproducible with different RAM sticks. I tried every possible combination with Kingston 32GB (2666MHz, CL 19-19-19-43) and Samsung 8GB (2400MHz, CL 17-17-17-39) -- the motherboard recognizes RAM sticks correctly, but still fails when the DIMM2 is filled with any RAM stick. I have also attached the build config file, which uses most of the default options. ---Files-------------------------------- m920q-dimm2-config.txt (27.6 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Feature #433] (New) Unify TPM drivers in coreboot
by Michał Żygowski Sept. 7, 2025

Sept. 7, 2025

Issue #433 has been reported by Michał Żygowski. ---------------------------------------- Feature #433: Unify TPM drivers in coreboot https://ticket.coreboot.org/issues/433 * Author: Michał Żygowski * Status: New * Priority: Normal * Target version: none * Start date: 2022-10-24 ---------------------------------------- Add an option to compile all drivers for TPM 1.2, 2.0 TIS and CRB. The motivation is to not build multiple coreboot ROMs for each possible TPM supported by the platform. The tasks would include: - runtime TPM detection (probing TPM_INTF_CAPABILITY and TPM_INTERFACE_ID) - rename the TPM driver functions, make them static and expose them as a driver structure, e.g. struct tpm_driver { void (*init)(void); int (*open)(void); int (*close)(void); int (*sendrecv)(const uint8_t *sendbuf, size_t send_size, uint8_t *recvbuf, size_t *recv_len); } - based on the detected TPM, hook the tpm_driver functions to provide the global TPM API: tis_open, tis_close, tis_init, tis_sendrecv. Some additional API to get vendor/device name could also be considered. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #538] (New) [Soft Brick] x230 Dock Causes Internal Display to "Permanently" Malfunction
by Brian L Sept. 7, 2025

Sept. 7, 2025

Issue #538 has been reported by Brian L. ---------------------------------------- Bug #538: [Soft Brick] x230 Dock Causes Internal Display to "Permanently" Malfunction https://ticket.coreboot.org/issues/538 * Author: Brian L * Status: New * Priority: High * Target version: none * Start date: 2024-05-14 * Affected hardware: Lenovo x230 ---------------------------------------- Environment: - Lenovo x230 - Stock screen replaced with Pixel Qi (not sure if relevant) (plug & play LVDS) - Coreboot using Heads (coreboot + linuxboot) - Official lenovo docking station connected to external monitor via DisplayPort Bug Trigger: Using Heads/coreboot fine for years with my Pixel Qi screen modded x230. I then bought a Lenovo docking station. Booted up, everything worked fine. Disconnected from dock, booted up, and there was no bios screen. Screen did not turn on until taken over by Linux Kernel. Once in userspace, wayland could no longer identify the monitor as a Pixel Qi or its proper resolution. EDID is blank. Booting with docking station allows bios to show on external display. Restarting did *not* fix the issue, reflashing heads did *not* fix the issue, flashing skulls (coreboot + seabios) did *not* fix the issue. Flashing stock bios *did fix* the issue. I can now see BIOS screen and get proper EDID in userspace whether on the dock or not. *However* reflashing coreboot again, even coming from stock bios working state, and I immediately now no longer get a BIOS screen or EDID, even without ever introducing the dock again. Essentially now bricked with anything but stock bios. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #535] (New) T420: Power light stays off after reboot
by frantic from xboot Sept. 7, 2025

Sept. 7, 2025

Issue #535 has been reported by frantic from xboot. ---------------------------------------- Bug #535: T420: Power light stays off after reboot https://ticket.coreboot.org/issues/535 * Author: frantic from xboot * Status: New * Priority: Low * Target version: master * Start date: 2024-04-24 * Affected hardware: Lenovo ThinkPad T420 ---------------------------------------- I have recently encountered a bug in coreboot where if you reboot the computer, the keyboard power light will stay turned off after it turns back on. Where if you do a clean boot, the light turns on. I am unsure whether this is a coreboot or payload issue. I am using GRUB as my payload. Just run the `reboot` command in Linux and it should be reproducible. Priority set to `Low` as it doesn't affect usability all too much. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #552] (New) X201 not booting with edk2 payload
by Maya Matuszczyk Sept. 7, 2025

Sept. 7, 2025

Issue #552 has been reported by Maya Matuszczyk. ---------------------------------------- Bug #552: X201 not booting with edk2 payload https://ticket.coreboot.org/issues/552 * Author: Maya Matuszczyk * Status: New * Priority: Normal * Category: board support * Target version: none * Start date: 2024-08-18 * Affected hardware: x201 ---------------------------------------- Hello, I tried to update my x201 with a new version of coreboot(I lost the working one). After building(using default config + set to x201 + bigger cbfs + linear high-res framebuffer) with latest release I couldn't get anything with edk2 to boot on it. I've tried changing `RESOURCE_ALLOCATION_TOP_DOWN` and using newer/older tags of MrChromebox's edk2 fork. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #600] (New) [Intel Eaglestream platform ]PCH HSIO bifurcation.
by guo deng Sept. 7, 2025

Sept. 7, 2025

Issue #600 has been reported by guo deng. ---------------------------------------- Bug #600: [Intel Eaglestream platform ]PCH HSIO bifurcation. https://ticket.coreboot.org/issues/600 * Author: guo deng * Status: New * Priority: Normal * Target version: 25.03 * Start date: 2025-06-21 * Due date: 2025-06-30 * Affected versions: 25.03 * Needs backport to: 25.03 * Related links: Please refer to the following linker which is about the intel eaglestream platform CRB board in Coreboot. https://github.com/coreboot/coreboot/tree/main/src/mainboard/intel/archerci… * Affected hardware: [Intel Eaglestream platform ] * Affected OS: NONE ---------------------------------------- [Intel Eaglestream platform ] I have already checked the coreboot code , but I can't find any code about how to configure the PCH HSIO pcie bifurcation by Intel FSP ? Please refer to the following linker which is about the intel eaglestream platform CRB board in Coreboot. ( https://github.com/coreboot/coreboot/tree/main/src/mainboard/intel/archerci… ) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Support #597] (New) success mb/dell: OptiPlex 5040 SFF works with adjusted Optiplex 3050 Micro code port
by Walter Sonius July 8, 2025

July 8, 2025

Issue #597 has been reported by Walter Sonius. ---------------------------------------- Support #597: success mb/dell: OptiPlex 5040 SFF works with adjusted Optiplex 3050 Micro code port https://ticket.coreboot.org/issues/597 * Author: Walter Sonius * Status: New * Priority: Normal * Category: board support * Target version: none * Start date: 2025-05-19 * Affected versions: 25.03 ---------------------------------------- Not sure to put this under support or refactoring, since adding this code to upstream coreboot using gerrit may look straight forward and easy to have a nice working optiplex_5040 port. My concern is however that the original `dell/optiplex_3050` code might need to be refactored into a variant first before this code will be accepted and that refactoring may be to much for me as a newbie. But it works... it works really well indeed. By mostly reusing `dell/optiplex_3050` port code which takes care of handling some variants 'SFF/MICRO' hinted by 'ramstage.c' for its own 3050 series itself, I just reused all of the code which I mostly don't understand and therefor may be wrong to put that as NEW board into the code tree. Although I have 'autoport logs' made for my 'optiplex_5040_sff' I don't know how to translate/apply correct that to my model(if needed). But since you have to start somewhere, and autoport only made logs I therefor just want to share this code and progress. Specs: Dell Optiplex 5040 SFF Motherboard: DP/N 0T7D40, CN-0T7D40-72200, 588-00HF-A00 OEM BIOS version: 1.22.0 03/16/2022 Reg Model: D11S Reg Type: D11S001 Service tag: HPR6C92 CPU: i3-6100 This Optiplex 5040 SFF motherboard looks very similar to the 3050 SFF(shares the same OEM BIOS as the 3050 micro) except for the following visual differences: 4 DDR3L slots vs 2 DDR4 slots (DDR4-sodimm on the micro) 1 PCIe 4x length (open) black slot vs 1x length (closed), micro none 3 SATA connectors vs 2 SATA (black missing), micro one 4 USB3 back ports vs 2 USB3 2 DisplayPorts vs 1 DisplayPort 1 serial vs 0 serial port 1 VGA(using motherboard header) vs 0 VGA 2 PS2 vs 0 PS2 ports Q170 chipset vs B250 chipset First the initial deguard requirement was the same for my optiplex_5040 sff as for the optiplex_3050 micro, as well as flashing or recovery. A minor edit to the [deguard code](https://ticket.coreboot.org/issues/588) is necessary to complete the deguard instruction. With the following crucial edits to the 'optiplex_3050' port its 'Kconfig', 'romstage.c' and minor edits to the existing 'devicetree.cb' almost everything started working: First hang on RAM issue ["[EMERG] FspMemoryInit error, status=0x80000007"](https://ticket.coreboot.org/issues/594) was fixed by adjusting 'Kconfig' `config DIMM_SPD_SIZE` from `default 512 # DDR4` to `256 # DDR3` and editing 'romstage.c' with additional addresses and changing `CaVrefConfig 2` to `0` made all 4 DIMM slots work: ``` > struct spd_block blk = { .addr_map = { 0x50, 0x51, 0x52, 0x53 } }; mem_cfg->DqPinsInterleaved = 1; > mem_cfg->CaVrefConfig = 0; mem_cfg->MemorySpdDataLen = blk.len; > mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; > mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; > mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; > mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; ``` By some additional edits to 'devicetree.cb' all PCIe slots(16x,4x,M2-ssd), all USB2&3 ports, all SATA ports and both PS2 ports started to function. Only the USB OC values have my concern, don't know what they stand for. ``` > # SLOT2 x16 > device ref peg0 on > register "Peg0MaxLinkWidth" = "Peg0_x16" > > # Configure PCIe clockgen in PCH > register "PcieRpClkReqSupport[0]" = "1" > register "PcieRpClkReqNumber[0]" = "0" > register "PcieRpClkSrcNumber[0]" = "0" > end > --- > device ref south_xhci on > register "usb2_ports" = "{ > [0] = USB2_PORT_MID(OC0), // Front panel (blue) > [1] = USB2_PORT_MID(OC0), // Front panel (blue) > [2] = USB2_PORT_MID(OC3), // Back panel (blue) > [3] = USB2_PORT_MID(OC2), // Back panel (blue) > [4] = USB2_PORT_MID(OC1), // Back panel (blue) > [5] = USB2_PORT_MID(OC1), // Back panel rightup (black) > [6] = USB2_PORT_MID(OC1), // Back panel (blue) > [7] = USB2_PORT_MID(OC1), // Back panel rightlow (black) > [8] = USB2_PORT_MID(OC_SKIP), // Front Panel rightlow (black) > [9] = USB2_PORT_MID(OC_SKIP), // Front Panel rightup (black) > > }" > register "usb3_ports" = "{ > [0] = USB3_PORT_DEFAULT(OC0), // Front panel (blue) > [1] = USB3_PORT_DEFAULT(OC0), // Front panel (blue) > [2] = USB3_PORT_DEFAULT(OC2), // Back panel (blue) > [3] = USB3_PORT_DEFAULT(OC2), // Back panel (blue) > [4] = USB3_PORT_DEFAULT(OC1), // Back panel (blue) > [5] = USB3_PORT_DEFAULT(OC1), // Back panel (blue) > }" > end --- > register "SataPortsEnable[1]" = "1" > register "SataPortsEnable[2]" = "1" --- < device ref pcie_rp21 on < register "PcieRpClkReqSupport[20]" = "1" < register "PcieRpClkReqNumber[20]" = "3" < register "PcieRpAdvancedErrorReporting[20]" = "1" < register "PcieRpLtrEnable[20]" = "true" < register "PcieRpClkSrcNumber[20]" = "3" < register "PcieRpHotPlug[20]" = "1" < end < < # Realtek LAN < device ref pcie_rp5 on < register "PcieRpClkReqSupport[4]" = "0" < register "PcieRpHotPlug[4]" = "0" < end < < # M.2 WiFi < device ref pcie_rp8 on < register "PcieRpClkReqSupport[7]" = "0" < register "PcieRpHotPlug[7]" = "1" --- > # SLOT3_M.2 > device ref pcie_rp17 on > register "PcieRpClkReqSupport[16]" = "1" > register "PcieRpClkReqNumber[16]" = "3" > register "PcieRpAdvancedErrorReporting[16]" = "1" > register "PcieRpLtrEnable[16]" = "true" > register "PcieRpClkSrcNumber[16]" = "3" > register "PcieRpHotPlug[16]" = "1" > end > > # SLOT1 x4 > device ref pcie_rp9 on > register "PcieRpClkReqSupport[8]" = "0" > register "PcieRpHotPlug[8]" = "1" > end --- > device pnp 2e.1 on # 8042 > io 0x60 = 0x60 > irq 0x0f = 0 > irq 0x70 = 1 > irq 0x72 = 12 > end --- > chip drivers/pc80/tpm > device pnp 0c31.0 on end > end --- > device ref gbe on end ``` Also TPM2 and onboard ethernet came alive with final edits to 'Kconfig': ``` > select MAINBOARD_HAS_TPM2 > select MEMORY_MAPPED_TPM > select MAINBOARD_USES_IFD_GBE_REGION ``` All audio ports including chassis speaker(soundcard) work using unchanged optiplex_3050 code, however autoport logs ran on OEM show different codec(chipset) and parameters for the 5040_sff compared to 3050 micro this may need to be alterned for correctness? Video output was unreliable until I replaced 'data.vbt' with the one extracted from original Dell Optiplex 5040 SFF 1.22 OEM bios (debugfs) and altered 'gma-mainboard.ads' to have HDMI and 2 DisplayPorts working perfectly. Only the VGA port, which is shown as 3rd DisplayPort (xrandr) uses the original motherboard breakout to the chassis VGA won't work at all (port not detected no BOOT nor OS). ``` ports : constant Port_List := (HDMI1, -- External HDMI DP2, -- External DP (bottom) DP1, -- External DP (top) DP3, -- External VGA (opt. breakout cable) others => Disabled); ``` Tested this on coreboot-25.03-519-ga2010cf5eeea both SeaBIOS 1.16.3 and EDK2 MrChromeBox 2502 payloads booting KDE NEON Linux 6.11 fine. Besides the "VGA port" only "Wake for LAN" isn't working for me yet every other port/connection/slot does work even combined iGPU and dGPU, leds, and CPU Fan speed also varies boot/restart. My concern is with the USB OC values, allot of GPIO values copied from the 3050 port and not correct to autoport and other stuff I might overlook. Feel free to check the added drop in optiplex_5040_sff.zip file with mostly a copy of 3050 micro port code to build a functional optiplex_5040_sff target or spin a variant into gerrit which I can assist and confirm testing. ---Files-------------------------------- autoport-corebooted-dell_optiplex_5040_sff.zip (208 KB) autoport-OEM122-dell_optiplex_5040_sff-deguard.zip (419 KB) optiplex_5040_sff.zip (14 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Support #581] (New) success new variant "compaq_pro_6300_sff" for hp/snb_ivb_desktops compatible with "compaq_8300_elite_sff" template
by Walter Sonius July 8, 2025

July 8, 2025

Issue #581 has been reported by Walter Sonius. ---------------------------------------- Support #581: success new variant "compaq_pro_6300_sff" for hp/snb_ivb_desktops compatible with "compaq_8300_elite_sff" template https://ticket.coreboot.org/issues/581 * Author: Walter Sonius * Status: New * Priority: Normal * Category: board support * Target version: none * Start date: 2025-03-15 ---------------------------------------- Successful flash and coreboot SeaBIOS functioning of a HP "compaq_pro_6300_sff" with a unchanged "compaq_8300_elite_sff" template using coreboot (24.12-758-g1e7ba810c6bb) and SeaBIOS (version rel-1.16.3-0-ga6ed6b70). These two HP Compaq devices are extremely similar, they use the same OEM proprietary BIOS upgrade files. Hardware wise the only 3 noticeable differences are that the "compaq_8300_elite_sff" comes with a Q77 chipset, SuperIO NPCD378 and J32 labeled 16x length "white" PCI-E slot versus a Q75 chipset, SuperIO NPCD379HAKFX with the J32 labeled slot populated with a limited physical 1x length "black" PCI-E slot on the "compaq_pro_6300_sff". Flashing from OEM proprietary BIOS 3.08revA enabling the FDO jumper on the motherboard as described for the compaq_8300_elite_sff works by booting with "iomem=relaxed" kernel parameter and specifying the specific 16MB chip 25Q128A: flashrom -p internal -w cbtest.rom -c "MT25QL128" Tested and Working: Poweron/Poweroff/Reboot CPU i3-3220 / e3-1225v2 RAM 1x 2x 4x populated slots total of 4GB/8GB/16GB/24GB (both 1.35v and 1.5v modules mixed with ECC) Serial port (including coreboot) PS2 keyboard (including SeaBIOS) PS2 mouse SATA 3 ports (blue/white/white) USB 2.0 4x front & 2x back ports USB 3.0 4x back ports Ethernet 1Gbit/100Mbit Display port works in SeaBIOS and OS VGA port only works in OS! PCI using realtek RTL8169 1Gb PCIE 3.0 16x using 2.0 8x 10Gb intel X540-AT2 / using 1.0 16x Nvidia Geforce 6200 LE (also works in SeaBIOS) PCIE 2.0 1x using 2.0 1x 2.5Gb realtek RTL8125 PCIE 2.0 1x using 1.0 1x 1Gb intel 82574L (SeaBIOS loads option rom) Audio built-in speaker (plays music in OS compared to legacy bleep pc-speaker) Audio front panel 3.5 mm headphone jack (auto disables built-in Speakers and selects Headphones) Audio front panel 3.5 mm headphone&mic jack (only microphone works with 4 pin 3.5mm combi mic/headphone) Audio back panel 3.5mm green jack (manually select Line Out and it works) Sensors CPU and 2 motherboard sensors SuperIO Booting USB / SATA(HDD/DVD) OS: Fedora-mate Linux kernel 6.11.4 / 6.13.6, KDE neon Linux kernel 6.8.0-52 Flashrom: needs additional parameters compared to OEM BIOS both for read/write depending on flashrom version? flashrom -p internal:boardmismatch=force,ich_spi_mode=hwseq -w test.rom -c "Opague flash chip" Tested not Working: RAM ECC functioning (see coreboot log) SATA port black Wakeonlan, it just auto wakes from itself so cannot verify... iGPU multigpu with PCIE nvidia geforce 6200 le, only PCIE nvidia geforce works and iGPU gets disabled. What to do next to get this "compaq_pro_6300_sff" variant officially supported? *Supply more logs/info? *Fill a bug for the ECC not working or first get this variant supported as is? *Fill a bug that VGA doesn't work in SeaBIOS? *Fill a bug/ticket on the flashrom support list for the difference in parameters needed pre/post flash? https://support.hp.com/us-en/drivers/hp-compaq-pro-6300-small-form-factor-p… https://support.hp.com/in-en/drivers/hp-compaq-elite-8300-small-form-factor… Walter Sonius ---Files-------------------------------- cb-log-hp-compaq_pro_6300_sff.txt (51.8 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #596] (New) Allocate resources from top down AND extend PCIe resource window above 4G together breaks libgfxinit bootscreen
by Walter Sonius July 5, 2025

July 5, 2025

Issue #596 has been reported by Walter Sonius. ---------------------------------------- Bug #596: Allocate resources from top down AND extend PCIe resource window above 4G together breaks libgfxinit bootscreen https://ticket.coreboot.org/issues/596 * Author: Walter Sonius * Status: New * Priority: Normal * Target version: none * Start date: 2025-05-19 * Affected versions: 25.03 ---------------------------------------- When enabling both `Allocate resources from top down` [enabled by default and fixed recently](https://review.coreboot.org/c/coreboot/+/87504) and `Extend resource window for PCIe devices above 4G` libgfxinit will break during bootscreen and other PCIe issues like failing wifi drivers may occur. Tested coreboot-25.03-519-ga2010cf5eeea (a2010cf5eeea6ad4a154cfb13760092f0865af3f) with Dell_Optiplex_5040_sff (i3-6100) and earlier Coreboot 25.03-467-gf0ad05b57ebe with Lenovo [x201](https://ticket.coreboot.org/issues/548#note-10) with MrChromeBox EDK2 2502. Can/should these 2 options be used together, if I understand correctly when using a modern efi GOP dGPU together with resizeable-bar all 3 options(+Support PCIe Resizable BARs) need to be enabled? Only using `Allocate resources from top down` or `Extend resource window for PCIe devices above 4G` does not lead up to this issue. ---Files-------------------------------- cb-log-dell-5040-sff-notd-a4b-ok-bootscreen.txt (41 KB) cb-log-dell-5040-sff-td-noa4b-ok-bootscreen.txt (41 KB) cb-log-dell-5040-sff-td-a4b-no-bootscreen.txt (40.5 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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