November 2025 - coreboot - mail.coreboot.org

[coreboot - Bug #598] (New) Lenovo m920x RAM compatibility issue
by Dawid Wrobel April 6, 2026

April 6, 2026

Issue #598 has been reported by Dawid Wrobel. ---------------------------------------- Bug #598: Lenovo m920x RAM compatibility issue https://ticket.coreboot.org/issues/598 * Author: Dawid Wrobel * Status: New * Priority: Normal * Target version: none * Start date: 2025-06-04 * Affected versions: main ---------------------------------------- Hi there, I recently flashed my m902x with coreboot (25.03-643-g69a067a9d62c-dirty). Everything seemed to work fine until I tried upgrading the memory from a single 8GB stick to 2 x 32GB (Crucial CT2K32G4SFD832A, https://eu.crucial.com/memory/ddr4/CT2K32G4SFD832A) The system won't boot in any configuration (a single stick in either slot or both). I get no display out, the system stays on and stuck, apparently, with high CPU usage causing fans to kick in. I have no serial port in this system at the moment (backordered an extension module), but am wondering if it will be of any help and if there's any other way to debug it? Do note that the system *is* capable of running 64GB memory, as it was reported already, so I wonder if this is a matter of some SPD misconfiguration? Crucial lists the 2x16GB modules as compatible with this system (https://eu.crucial.com/compatible-upgrade-for/lenovo/thinkcentre-m920x-tiny…) and they have seemingly identical specs as the 2x32GB ones. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #592] (New) Lenovo M920q can't use DIMM2 RAM slot
by Coreboot Enjoyer April 6, 2026

April 6, 2026

Issue #592 has been reported by Coreboot Enjoyer. ---------------------------------------- Bug #592: Lenovo M920q can't use DIMM2 RAM slot https://ticket.coreboot.org/issues/592 * Author: Coreboot Enjoyer * Status: New * Priority: Normal * Category: coreboot common code * Target version: none * Start date: 2025-04-15 * Affected versions: main * Related links: https://github.com/Thrilleratplay/coreboot-builder-scripts/issues/33 Also, it looks like a similar issue to https://ticket.coreboot.org/issues/462 * Affected hardware: Lenovo M920q ---------------------------------------- Building the current coreboot source, as well as commits 497298708c330deb479fbf3ee6a3acc8bff2a102, 640a41f3ee938b794b140218921e0fd63b1d9235 and 7945a31e9172ec2939cc1abc6036962a6efb601b, produces the firmware, that allows to initialize the motherboard if only DIMM1 RAM slot is filled. It fails to initialize, if DIMM1 RAM slot is empty and DIMM2 is filled, as well as if both DIMM1 and DIMM2 are filled. The issue is reproducible with different RAM sticks. I tried every possible combination with Kingston 32GB (2666MHz, CL 19-19-19-43) and Samsung 8GB (2400MHz, CL 17-17-17-39) -- the motherboard recognizes RAM sticks correctly, but still fails when the DIMM2 is filled with any RAM stick. I have also attached the build config file, which uses most of the default options. ---Files-------------------------------- m920q-dimm2-config.txt (27.6 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #449] (New) ThinkPad T440p fail to start, continous beeping & LED blinking
by Crazy Fox Feb. 21, 2026

Feb. 21, 2026

Issue #449 has been reported by Crazy Fox. ---------------------------------------- Bug #449: ThinkPad T440p fail to start, continous beeping & LED blinking https://ticket.coreboot.org/issues/449 * Author: Crazy Fox * Status: New * Priority: Normal * Category: coreboot common code * Target version: 4.18 * Start date: 2023-01-14 * Affected versions: 4.18 * Affected hardware: haswell ---------------------------------------- Hi, Team Being corebooted before and works fine on 4.17. After flashing 4.18 my t440p wont startup (black screen, constant beeping & LED blinking). I've tried and retried different nconfigs but result is the same. I know that it is lack of information, but I need to recover the laptop first to grab some logs from it. Log from FT232H's debug is attached, the rest of info (defconfig, flashrom command etc. will upload soon) ---Files-------------------------------- coreboot_t440p_emerg.log (7.85 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #576] (New) GPIO locking is broken on Kaby Lake and possibly other platforms
by Mate Kukri Jan. 25, 2026

Jan. 25, 2026

Issue #576 has been reported by Mate Kukri. ---------------------------------------- Bug #576: GPIO locking is broken on Kaby Lake and possibly other platforms https://ticket.coreboot.org/issues/576 * Author: Mate Kukri * Status: New * Priority: Normal * Target version: none * Start date: 2025-01-30 ---------------------------------------- Many supported Kaby Lake boards (and possibly newer platforms as well) are vulnerable to [TPM GPIO reset attacks](https://mkukri.xyz/2024/06/01/tpm-gpio-fail.html). Trying to fix this by marking the affected GPIOs as locked in gpio.h and even also selecting `SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS` does not work. This was discovered last year and briefly discussed on #coreboot, but it came up again on the Heads matrix group in relation to supporting the TPM on the in-progress ThinkPad T480 port. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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coreboot architecture with signed FSP
by Werner Zeh Jan. 1, 2026

Jan. 1, 2026

Dear coreboot community, as some of you may have heard from the OSFC already, there are plans at Intel to restructure the way FSP is executed [1]. The main goal is to switch to an operation mode where only Intel signed FSP binaries can be executed. This comes, according to the current plans, with an architectural change that will affect coreboot's execution flow. In this proposed, changed execution flow a new FSP component will be loaded at reset vector and do the verification of the following FSP components like FSP-T, FSP-M and FSP-S. Then, the execution flow will continue in FSP and calls to coreboot code shall happen. In this new flow, no self-built FSP binaries can be executed anymore as they are not signed by Intel. I want to start a discussion with the community and Intel to see if we can come up with something better than this approach which will not heavily change the coreboot architecture but nevertheless provide a level of confidentiality for Intel's FSP blobs. You all are warmly welcome to participate in this discussion. Feel free to forward this invitation to anyone who might be interested. The call is planned for December 3th at 7 pm CET and will be hosted on Google Meet [2]. Feel free to join and let's have a constructive discussion. Werner [1] https://www.osfc.io/2025/talks/intel-r-signed-fsp-and-verified-boot/ [2] https://meet.google.com/kgh-nquh-usm

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EU-CRA and the ongoing standardization work
by Werner Zeh Dec. 14, 2025

Dec. 14, 2025

Hi coreboot community. As presented on the last OSFC, there is quite some work currently ongoing in the context of the upcoming EU Cyber Resilience Act (EU-CRA, [1]). Among the activities is the creation of harmonized standards which will be used to help in conformity assessment of the different applications, which are driven by ETSI. Some of the standards are now publicly available for review and I encourage you to take a closer look and provide feedback. You can find the draft standards as well as a feedback form here: [2]. Especially the standard for Boot Managers (see [3]) is highly interesting for the firmware space. In case of questions feel free to reach out to me. Werner [1]: https://eur-lex.europa.eu/legal-content/EN/TXT/?uri=CONSIL%3APE_100_2023_RE… [2]: https://docbox.etsi.org/CYBER/EUSR/Open/ [3]: https://docbox.etsi.org/CYBER/EUSR/Open/EN-304-623_V0.0.4_2025-09-30_Boot_M…

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Jenkins on Debian oldstable vs Dockerfile on stable - update status
by ehaouas Nov. 30, 2025

Nov. 30, 2025

‌ Hello, I noticed an inconsistency in the Debian versions being used: - util/docker/coreboot-sdk/Dockerfile uses Debian stable - Jenkins continues to run on Debian oldstable with GCC-12 This issue was previously discussed in the leadership meeting, and it was agreed that Jenkins should be updated to Debian stable. However, this update still hasn't been implemented. I would like to understand: 1. What technical blockers are preventing this update? 2. Are there specific compatibility issues? 3. What is the expected timeline for resolving this? Thank you for your insights on this matter. Best regards, Elyes

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2025-11-26 - coreboot Leadership Meetings Minutes
by mina＠coreboot.org Nov. 27, 2025

Nov. 27, 2025

# 2025-11-26 - coreboot Leadership Meetings ## Open Action Items * 2025-11-12 * [Done] Werner: Set up a call with Intel in early December * [Open] Martin: Will take care of patches older than a year. * 2024-11-27 * [Open] Send out poll with regards to LLM usage (requested by SFC) * 2024-10-30 * [Open] Add clarification to docs: “Do not use gerrit change-id or CB: format in reference to already-merged patches.” * 2024-10-16 * [Open] Matt: Set up a meeting to discuss board status alternatives and send out invites. * Decouple data collection with uploading * Require gerrit credentials or other auth to push * Json format? * https://github.com/chrultrabook/linux-tools/blob/main/debugging.sh * 2024-09-18 * [Open] Jon: Schedule a dedicated meeting to discuss the Coverity defects and action plan. * Werner: Send out an invite for the meeting. Sent out a poll to find a time slot: https://rallly.co/invite/1c8J3azXAcje * 2024-05-01 * [Open] Nick Van Der Harst volunteered for Dutch. "gogo gogo" would like to translate to Russian (?). * 2024-01-10 * Nico: (https://review.coreboot.org/q/topic:enforce_region_api) * [Open] Daniel: Look at how we want to localize (non-console) strings for coreboot. Long-term project. ## Announcements & Events ## Late GMT coreboot Leadership Meeting Minutes ## Attendees Mina Asante, Werner Zeh, Matt DeVillier, Jay Talbott, Karthik R. ## Minutes ### [Werner] Coverity-Project is looking for some refactoring of their services. They want to understand if the projects using their services would be willing to sponsor their open program with money. * [Matt D] I’m not opposed to using coreboot’s resources to support Coverity; it’s just the question of whether we should make a donation and support their free tier or move up and use their paid services. * [Matt D] I think we should keep this discussion open for the next leadership meeting when we have a larger number of community members present. * [Werner Z] Agreed. ### [Werner Zeh] The meeting between intel and the coreboot community is scheduled for Wednesday, December 3. Further details can be found here, in an email I sent last Monday: (https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/PKFR7R…) A calendar invite will be created, and everyone interested is welcome to join. ## Early GMT coreboot Leadership Meeting Canceled ### No issues on the meeting agenda # Next Leadership Meetings Date * December 10, 2025. * [coreboot Calendar](https://coreboot.org/calendar.html). # Notice Decisions shown here are not necessarily final and are based on the current information available. If there are questions or comments about decisions made, or additional information to present, please put it on the leadership meeting agenda and show up if possible to discuss it. Of course items may also be discussed on the mailing list, but as it's difficult to interpret tone over email, controversial topics frequently do not have good progress in those discussions. For particularly difficult issues, it may be best to try to schedule another meeting. We now host two leadership meetings, one in early GMT and one in late GMT, to better accommodate participants from the Asian time zones. Kindly note that both sessions use the same meeting notes and Google Meet link. # coreboot Leadership Meeting Notes https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgK….

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[coreboot - Bug #617] (New) Missing safeguard: CBFS_SIZE greater than BIOS region in the IFD
by gaspar ilom Nov. 26, 2025

Nov. 26, 2025

Issue #617 has been reported by gaspar ilom. ---------------------------------------- Bug #617: Missing safeguard: CBFS_SIZE greater than BIOS region in the IFD https://ticket.coreboot.org/issues/617 * Author: gaspar ilom * Status: New * Priority: Normal * Target version: none * Start date: 2025-11-14 * Affected versions: main * Affected hardware: haswell ---------------------------------------- There are no effective safeguards to enforce that the `CONFIG_CBFS_SIZE` does not exceed the bios region as declared in the IFD. ### Impact - Downstream under Heads with a maximized bios region for the Haswell boards (T440p and W541) we could verify that this bug leads to an overflow when training the memory cache that makes it not work. This happens both with MRC blob and NRI and causes very slow boot times (20s) and S3 suspend/resume does not work. - Effects on other boards have not been observed but are possible. ### Expected behavior Coreboot should not build successfully if the `CBFS_SIZE` exceeds the bios region in the IFD and error out reporting the problem that caused this. ## Analysis Full details are under the PR in Heads and in particular this comment by @tlaurion https://github.com/linuxboot/heads/pull/2025/#issuecomment-3524672338 Ifttool reports a bios region of 0xBDEFFF (BDEFFF). However, the coreboot config contained: ``` CONFIG_CBFS_SIZE=0xBE4FFF ``` ``` ./build/x86/coreboot-25.09/util/ifdtool/ifdtool --platform ifd2 --layout w541_layout blobs/w541/ifd.bin && cat w541_layout File blobs/w541/ifd.bin is 4096 bytes Wrote layout to w541_layout 00000000:00000fff fd 00021000:00bfffff bios 00003000:00020fff me 00001000:00002fff gbe ``` After fixing the `CONFIG_CBFS_SIZE` the issues were fixed and fast boot with trained memory cache and S3 suspen/resume work again with NRI: https://github.com/linuxboot/heads/pull/2025/commits/9b8b9cacdcea4f67c95dce… -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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coreboot Meetings Announcement And Agenda Call
by mina＠coreboot.org Nov. 24, 2025

Nov. 24, 2025

Dear coreboot Community, Please be reminded that our early GMT and late GMT coreboot leadership meetings are scheduled for Wednesday, November 26, 2025. [1] Kindly take a moment to update the agenda items with issues you'd like to discuss during these meetings. [2] Thank you. ## Current Agenda Items * No active issues on the agenda yet. [1](https://coreboot.org/calendar.html) [2](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkK…

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