June 2023 - coreboot - mail.coreboot.org

[coreboot - Bug #499] (New) coreboot will not boot edk2 on Lenovo T440p with CONFIG_RESOURCE_ALLOCATION_TOP_DOWN enabled, cannot disable this setting during build
by Oberon 4071 Aug. 31, 2023

Aug. 31, 2023

Issue #499 has been reported by Oberon 4071. ---------------------------------------- Bug #499: coreboot will not boot edk2 on Lenovo T440p with CONFIG_RESOURCE_ALLOCATION_TOP_DOWN enabled, cannot disable this setting during build https://ticket.coreboot.org/issues/499 * Author: Oberon 4071 * Status: New * Priority: Normal * Category: coreboot common code * Start date: 2023-06-29 * Affected versions: 4.21 * Needs backport to: none * Affected hardware: lenovo/t440p ---------------------------------------- coreboot revision in git: feb27dcbf3fc685b070c950a16e8adec958bc1ce coreboot revision (git describe --tags): 4.20-520-gfeb27dcbf3 Tested payloads: edk2 from MrChromebox revision uefipayload_202304 and uefipayload_202306 coreboot will not boot my Lenovo ThinkPad T440p with CONFIG_RESOURCE_ALLOCATION_TOP_DOWN enabled, when using the edk2 payload (MrChromebox version, either uefipayload_202304 or uefipayload_202306). The display sometimes turns on, indicating that some of the hardware initialization was successful, but the payload will not start. I tried to disable CONFIG_RESOURCE_ALLOCATION_TOP_DOWN in .config, but the build process insists on leaving this config enabled. This seems to be caused by the RESOURCE_ALLOCATION_TOP_DOWN setting changed to "def_bool y" in src/device/Kconfig in commit 5226301765ded70e0ef640e5252bbaca8cd14451 (allocator_v4: Treat above 4G resources more natively). The make target for building coreboot seems to automatically rerun olddefconfig, causing this setting to always remain enabled no matter what was previously saved in the .config file. Modifying src/device/Kconfig to change RESOURCE_ALLOCATION_TOP_DOWN to "def_bool n" appears to fix the problem on my machine. I have attached my .config file (with CONFIG_RESOURCE_ALLOCATION_TOP_DOWN enabled to reproduce the problem). ---Files-------------------------------- .config (20.7 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #495] (Response Needed) Stoney not booting PSPSecureOS -- Graphics driver takes 30 minutes to start
by CoolStar Organization Aug. 14, 2023

Aug. 14, 2023

Issue #495 has been reported by CoolStar Organization. ---------------------------------------- Bug #495: Stoney not booting PSPSecureOS -- Graphics driver takes 30 minutes to start https://ticket.coreboot.org/issues/495 * Author: CoolStar Organization * Status: Response Needed * Priority: High * Category: chipset configuration * Target version: none * Start date: 2023-06-14 * Affected versions: 4.21, 4.15, 4.16, 4.17, 4.18, 4.19, master * Affected hardware: stoney * Affected OS: Windows 10, Windows 11 ---------------------------------------- Windows 11 Graphics driver takes 30 minutes to start on Stoney due to missing PSPSecureOS. Windows 10 20H2 and newer hangs on boot (potentially from the same thing) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #496] (New) Missing malloc check in libpayload
by Keith Makan Aug. 14, 2023

Aug. 14, 2023

Issue #496 has been reported by Keith Makan. ---------------------------------------- Bug #496: Missing malloc check in libpayload https://ticket.coreboot.org/issues/496 * Author: Keith Makan * Status: New * Priority: Normal * Target version: none * Start date: 2023-06-27 * Affected versions: 4.21 * Affected hardware: ALL * Affected OS: ALL ---------------------------------------- libpayload in payload/libpayload/drivers/options.c::get_option_as_string does not issue a NULL check against malloc's return code. Should there be a NOMEM error this may result in a NULL pointer deref or crash. The following code extract illustrates the mentioned issue: ` int get_option_as_string(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, char **dest, const char *name) { ... /* extra byte to ensure 0-terminated strings */ raw = malloc(cmos_length+1); memset(raw, 0, cmos_length+1); <--- no check against malloc's return code ` -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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Tree maintenance and build nodes
by Kyösti Mälkki Aug. 6, 2023

Aug. 6, 2023

Hi A couple of questions, less technical than usual. Do we have any sample cases of bringing boards back from older branches? I would like to have a branch set up for bringing back some selected AGESA from 4.18 branch. My plan would be to backport features from ToT into said new branch and resolve issues there. Once considered clean enough, it should be a three commit drop (vendorcode, platform, boards) to land on master? Is there someone (corporate) currently funding or hiring personnel with reviews and tree maintenance as a priority? Is there currently anyone actually assigning from their existing resources to put attention to frameworks, while customers' board ports and resolving their issues have tight schedules? Regards, Kyösti Mälkki

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[coreboot - Feature #476] (New) Add option to convert coreboot-inited linear frame buffer to efifb directly
by Bill XIE Aug. 2, 2023

Aug. 2, 2023

Issue #476 has been reported by Bill XIE. ---------------------------------------- Feature #476: Add option to convert coreboot-inited linear frame buffer to efifb directly https://ticket.coreboot.org/issues/476 * Author: Bill XIE * Status: New * Priority: Normal * Category: coreboot common code * Target version: none * Start date: 2023-03-30 * Affected OS: GNU/Linux ---------------------------------------- Currently, the linear frame buffer that coreboot initializes should be handled by Linux kernel with dedicated driver "simplefb", but most installer of GNU/Linux distributions only enables "efifb" support, which causes a GNU/Linux installer kexec-ed from a Linux payload running atop simplefb unable to output graphics. Currently, Grub payload could turn coreboot-initialized simplefb to efifb, which can be easily examined from the dmesg log of GNU/Linux booted from Grub payload running atop coreboot-inited linear frame buffer (simplefb). Chainloading a Linux payload with a minimal Grub payload only containing module "linux" and "cbfs" could make the Linux payload running atop efifb, of which GNU/Linux installers can make use, but the related code could be ported to coreboot to make things easier. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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Potential EC refactor for Lenovo laptops
by Avery June 30, 2023

June 30, 2023

Hello, I've been reverse-engineering the ThinkPad X230's MEC 1619 EC firmware (G2HT35WW) and the UEFI binaries which interface with it on ports 62h/66h and 1600h/1604h. In particular I've been looking at the process for flashing new EC firmware, referencing the public MEC1618 datasheet[1], so I could try to flash new EC firmware on a corebooted ThinkPad; the relevant binaries are the following: * EcFwUpdateDxe 0C396FCA-6BDA-4A15-B6A3-A6FA4544BDB7 * EcIoDxe 114CA60C-D965-4C13-BEF7-C4062248E1FA * Installs a native protocol interface 3161DDAB-9600-4301-AAB2-93006395824A * EcIoSmm 03EBDB4B-96BA-4F40-8329-7F3AA8865707 * Installs a native protocol interface AADE7C97-98E7-4CFA-B4EF-BBE20506A31D From this, I found that these binaries uses at least some of the the EC register layout for Quanta's firmware for IT8518 ECs (ec/quanta/it8518/acpi/ec.asl), which is included in mb/google/stout. The stout codename refers to ThinkPad X131e, which are also Ivy Bridges, and also has a different mainboard tree in mb/lenovo/x131e which separately uses ec/lenovo/h8/acpi/ec.asl. The X230 mainboard also uses the H8S ASL. Both the H8S and IT8518 definitions line up pretty well for the most part, but here are also some evidence from my reversing on the X230: EcIoDxe exposes a function that appears to implement the SMBus Host Controller Interface specifications. The following are the EC registers used there: * 50h SMB_PRTCL * 51h SMB_STS * 52h SMB_ADDR * 53h SMB_CMD * 54h-73h SMB_DATA * 74h SMB_BCNT EcFwUpdateDxe also updates the register at 3Dh, bitwise-orring it with DFh. This action is said to restrict EC flash access past the boot sequence [2], and lines up with the description of "Password Control" given by the IT8518 ASL. Since the H8 configuration appears to be common across multiple boards, I believe these two can be merged seeing as the IT8518 definitions are a bit more detailed, potential mainboard-specific quirks notwithstanding. I'm curious to hear if there would be any issues or incompatibilities with this. Cheers, Avery [1]: https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocum… [2]: https://i.blackhat.com/USA-19/Thursday/us-19-Matrosov-Breaking-Through-Anot…

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disable efficient-cores or performance-cores in Intel 12th gen processors
by baptx June 28, 2023

June 28, 2023

Hello, For people who use the 12th generation of Intel Core processors, they may want to disable efficient-cores in the BIOS to improve performance ( https://www.reddit.com/r/intel/comments/thp7jh/disabling_the_efficiency_cor…) is it supported by coreboot or Dasharo? Some people may also want to disable performance-cores instead to save more battery ( https://www.reddit.com/r/overclocking/comments/x0xu1c/can_you_disable_perfo…) is it supported also? If some of these disabling option are not available, is there any plan to support them and is there a workaround currently? Thanks.

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Legacy OS Support
by Mason McAlister June 28, 2023

June 28, 2023

hello! any idea when Legacy OS/BIOS support is coming to Coreboot? i'd like to be able to boot legacy OSes (such as Windows 7 and below) on my chromebook, which is using MrChromebox's fork of Coreboot. i'm not "expecting" Legacy OS/BIOS support, UEFI is good enough, i think it'd just be cool if i could get windows XP or windows 7 on a chromebook. cheers! -Mason

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Coreboot's stance on Purism since 2015: What changed ?
by Alexandre Janvrin June 28, 2023

June 28, 2023

Greetings, I have been shopping around for a laptop during the past few weeks, aiming for a mix of performance and privacy. During my search, I came across a blog post by mrnuke: - https://web.archive.org/web/20150223201313/https://blogs.coreboot.org/blog/… (the post was referenced in a Qube OS discussion related to Anti Evil Maid: https://groups.google.com/g/qubes-users/c/sEmZfOZqYXM/m/j5rHeex1BAAJ) I've noticed that this post has disappeared from Coreboot's blog, and that Coreboot now advertises Purism quite differently. From https://www.coreboot.org/users.html: "Purism manufactures security focused laptops designed chip by chip to work with free/libre and open source software. Purism laptops are the only independently-made, brand new, high-performance laptops on the market specifically meant to pair recent technologies with coreboot and a neutralized Intel Management Engine." I also came across Purism's public answer: https://puri.sm/posts/about-purism-and-librems-and-cake/ I guess the change in Coreboot's stance can be explained in a few manners: - Purism genuinely improved since 2015 and is now delivering on their promises, - mrnuke's opinion never reflected Coreboot's opinions, - Purism extended a "helping" hand to Coreboot, in order to align both parties' economical objectives, From an external viewpoint, I'd say that Purism has improved on their delivery, and their narrative seems to be grounded in reality rather than smoke and mirrors. (Even though they currently admit to still having some binary blobs here and there) Can you please provide more context, and indulge in the curiosity of a random user ? (Disclaimer: I do not intend to buy a Purism laptop, not because I think they are bad, but because I'll have a more "Do It Yourself" approach) Best regards, Alexandre (a security/privacy enthusiast)

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2023-06-28 - coreboot Leadership Meeting
by coreboot org June 28, 2023

June 28, 2023

# 2023-06-28 - coreboot Leadership Attendees: DavidH, Jpmurphy, Coolstar, MattD, FelixS, WernerZ, JonathanH, StefanR, MartinR, JuliusW, RonM, KarthikR, DanielM ## Minutes: * [KyöstiM] Make build statistics downloadable from qa.coreboot.org Work to create such tar-file with timestamps and ccache stats started here: [https://review.coreboot.org/c/coreboot/+/75803](https://review.coreboot.org… * Martin will look at making the stats downloadable * [KyöstiM] Is ccache for clang intentionally disabled for coreboot-gerrit queue? I think it would be possible to configure ccache for separate gcc and clang backing storages. * Ccache was causing the build to take longer, so was disabled. Martin did look at separating the two ccache locations, but the GCC ccache is stored in ram, and there isn't typically enough memory to save both. * Look at separating GCC and clang builds into two separate builds. * Look at coverity builds - should probably only build GCC. * [coolstar] Pixel 2013 (Link) I2C bus ACPI (Windows vs Linux) * Attaches to IGD device because the i2c touchpad/touch screen are on it * Brand new drivers that are about to be submitted to MS to get signed – hardware pre-dates I2CSerialBus (which normally would be in HSW+), but new drivers on Windows use it. * It sounds like the best plan is to just push the patches and see if there are any other suggestions. * [Mailing list] Variants * There was a request on the mailing list to look at making a company’s board a variant of the CRB. We should give recommendations in the documentation about when variants should be used. * [Martin] vendors shouldn’t be under other vendors. CRBs shouldn’t be used as baseboards for other boards. * [Werner] Agree with Martin that variants should be used for whitelabel devices, but not for CRBs. * [Ron] Things are the way they are because early in the coreboot project, the other method of having vendors under CRBs was tried. The current method gives free reign to vendors to change whatever they want.Vendors like to tweak their own boards and do not like having other vendors introduce conflicting changes. * What about duplicated code and having to refactor functions out? * Ron - Sure, things can be refactored out, but deduping the code can be very tricky - it leads to a lot of #ifdefs and gets very messy. Mucking about in mainboard code may look good from an abstract firmware engineering standpoint, but leads to issues. * Daniel: Using CRBs for baseboards could work as a tree with another level, but agrees with Ron that having separate boards probably makes more sense. * Who should handle any refactoring? * Martin thinks that pushing refactoring to new coreboot engineers is going to make people want to not contribute to coreboot. * David - Definitely - can’t ask new people to rewrite as a vendor without giving any direction as to why or how, or point at a concrete example. * Ron - Agrees with David - pushing people too hard encourages forks. * Werner - could be a path to more contribution - submit initial patch, then look at rewriting. * David - teaching good code quality and coreboot standards is one thing, but pushing them without direction just leads to frustration from the new person. * Daniel - Experience shows that refactoring without understanding leads to poor refactors. We could use some documentation. Any comments could be written as documentation to help people. * David: “There are plenty of variants in the tree - look at them for examples.” is not helpful - people would have no idea which variant to look at. Especially when one doesn't exist. * Ron - stakes are much higher in firmware. It's easy to mess up and brick a bunch of systems. * Martin & David: Refactoring by beginners causes those beginners to rewrite the code in the CRB, which will lead to issues, especially if they can’t test it. * Stefan - Making code look nice is problematic and can break things. * David will write up some documentation on what was discussed here about when to use variants. Daniel & Werner can help. * Would it be interesting to have “shepherds” to help newcomers to the community? * FelixS: I’m doing this for the releases. * How time consuming is this? * The process is started 6 weeks before the release. It really varies, but typically a few hours a week. * Would people be interested in signing up to shepherd newcomers? * Matt, stefan, martin - sure * Martin will create a signup sheet * Ron, Jonathan, and Jpmurphy would be interested in shadowing until they feel confident. * Martin to send email to the mailing list with a request for additional shepherds. * Make script to help direct attention to patches (status:open and +1'd or +2'd, maybe other criteria) to help get them merged - send to mailing list periodically (weekly digest?). * [DanielM] relaying from Slack * Warner Losh: So I’m trying to understand something about a code change request I got for FreeBSD. A long time ago (2015), we committed: [https://cgit.freebsd.org/src/commit/?id=6c176113bbdd5](https://cgit.freebsd… to implement quirks for what’s not about 10-year-old chromebooks, but specified just the Acer Peppy. Later (2016), I expanded this to all coreboot instances since at the time I only knew that they were in chromebooks. Lately, we’re getting a lot of requests to add exception to the rules that are there. Starting in 2020, we started getting these. I’m wondering if there’s a better way and if people here even know what the issue is/was. DFBSD seems to have deleted all their code for this. [https://github.com/DragonFlyBSD/DragonFlyBSD/commit/ad8b9749306613f2978808b… and [https://github.com/DragonFlyBSD/DragonFlyBSD/commit/7f3d8d5546c701eceefe443… were the original dfbsd commits describing the problem with the emulated i8042. * Could someone reach out to Warner on slack? * Matt and coolstar fixed this in the EC codebase in Matt’s repo. # Notice Decisions shown here are not necessarily final, and are based on the current information available. If there are questions or comments about decisions made, or additional information to present, please put it on the leadership meeting agenda and show up if possible to discuss it. Of course items may also be discussed on the mailing list, but as it's difficult to interpret tone over email, controversial topics frequently do not have good progress in those discussions. For particularly difficult issues, it may be best to try to schedule another meeting. # coreboot leadership meeting minutes https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgK…

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