February 2023 - coreboot - mail.coreboot.org

[coreboot - Bug #439] (New) Lenovo X201 Turbo Boost not working
by Lukas Karg Nov. 17, 2025

Nov. 17, 2025

Issue #439 has been reported by Lukas Karg. ---------------------------------------- Bug #439: Lenovo X201 Turbo Boost not working https://ticket.coreboot.org/issues/439 * Author: Lukas Karg * Status: New * Priority: High * Target version: none * Start date: 2022-11-18 * Affected versions: master * Affected hardware: Lenovo X201 * Affected OS: Linux, Windows, ... ---------------------------------------- -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Feature #433] (New) Unify TPM drivers in coreboot
by Michał Żygowski Sept. 7, 2025

Sept. 7, 2025

Issue #433 has been reported by Michał Żygowski. ---------------------------------------- Feature #433: Unify TPM drivers in coreboot https://ticket.coreboot.org/issues/433 * Author: Michał Żygowski * Status: New * Priority: Normal * Target version: none * Start date: 2022-10-24 ---------------------------------------- Add an option to compile all drivers for TPM 1.2, 2.0 TIS and CRB. The motivation is to not build multiple coreboot ROMs for each possible TPM supported by the platform. The tasks would include: - runtime TPM detection (probing TPM_INTF_CAPABILITY and TPM_INTERFACE_ID) - rename the TPM driver functions, make them static and expose them as a driver structure, e.g. struct tpm_driver { void (*init)(void); int (*open)(void); int (*close)(void); int (*sendrecv)(const uint8_t *sendbuf, size_t send_size, uint8_t *recvbuf, size_t *recv_len); } - based on the detected TPM, hook the tpm_driver functions to provide the global TPM API: tis_open, tis_close, tis_init, tis_sendrecv. Some additional API to get vendor/device name could also be considered. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #415] (New) RESOURCE_ALLOCATION_TOP_DOWN breaks edk2
by Sean Rhodes May 2, 2025

May 2, 2025

Issue #415 has been reported by Sean Rhodes. ---------------------------------------- Bug #415: RESOURCE_ALLOCATION_TOP_DOWN breaks edk2 https://ticket.coreboot.org/issues/415 * Author: Sean Rhodes * Status: New * Priority: Low * Target version: none * Start date: 2022-09-07 * Affected versions: master ---------------------------------------- CB:41957 enabled RESOURCE_ALLOCATION_TOP_DOWN by default, which stopped edk2 from booting. The commit has been reverted, so this ticket is just to post logs. ---Files-------------------------------- resource_allocatorv4.txt (94 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Feature #420] (New) Use standard format of TPM event log
by Krystian Hebel Aug. 7, 2024

Aug. 7, 2024

Issue #420 has been reported by Krystian Hebel. ---------------------------------------- Feature #420: Use standard format of TPM event log https://ticket.coreboot.org/issues/420 * Author: Krystian Hebel * Status: New * Priority: Normal * Target version: none * Start date: 2022-10-12 * Related links: [1] https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClientImplementa… [2] https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClient_PFP_r1p05… ---------------------------------------- Currently coreboot uses proprietary format for TPM event log. TCG has standardized log formats, differently for TPM1.2 (aka legacy or SHA1) [1] and TPM2.0 (aka crypto agile) [2], both of which can be parsed by Linux kernel and exposed in sysfs. I don't know of any tool outside of cbmem which can parse coreboot format; this includes payloads which may be interested in continuing chain of trust started by coreboot. Another incompatibility is caused by vboot's assignment of PCRs. Roles of PCRs are roughly specified by TCG in both of mentioned documents, they are more or less compatible with each other, but not with current coreboot code. These changes could break assumptions made by existing platforms, so they should be made as Kconfig options. This is a tracking issue to collect subtasks that need to be done in order to support standard event log formats. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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QEMU x86 i440fx/piix4 build fails for >= 32MB ROMs - Assertion IS_HOST_SPACE_ADDRESS(host_space_address) failed
by Mike Banon Feb. 20, 2024

Feb. 20, 2024

If I use a default config for i440fx/piix4, building a 16MB ROM works fine, but 32MB or 64MB doesn't work anymore: ... CC postcar/southbridge/intel/common/rtc.o LINK cbfs/fallback/postcar.debug OBJCOPY cbfs/fallback/romstage.elf CREATE build/mainboard/emulation/qemu-i440fx/cbfs-file.vqaXlP.out (from /home/my_custom_path_to/coreboot/.config) CC+STRIP src/lib/cbfs_master_header.c OBJCOPY cbfs/fallback/bootblock.elf OBJCOPY bootblock.raw.elf OBJCOPY bootblock.raw.bin Created CBFS (capacity = 33553892 bytes) BOOTBLOCK CBFS cbfs_master_header CBFS fallback/romstage cbfstool: /home/my_custom_path_to/coreboot/util/cbfstool/cbfstool.c:1145: cbfstool_convert_mkstage: Assertion `IS_HOST_SPACE_ADDRESS(host_space_address)' failed. make: *** [Makefile.inc:1116: build/coreboot.pre] Aborted -- Best regards, Mike Banon Open Source Community Manager of 3mdeb - https://3mdeb.com/

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Coreboot chat room
by Arne April 23, 2023

April 23, 2023

Hi, I just created a XMPP chat room about coreboot on our public XMPP server and I would be happy to make it to an official coreboot chatroom. The server is running since 2,5 years and will stay online for at least the next years. Maybe you like to join. So the main question is, can I write in the chatroom description "official coreboot chatroom"? I would also offer the coreboot delevopers a free XMPP chat account on https://ocean.monocles.de/apps/registration/ or https://ocean.monocles.eu/apps/registration/ Thanks for your project and best regards, Arne

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[GSOC 2023] Libpayload based memtest payload
by Joursoir March 24, 2023

March 24, 2023

Hello everyone, I'm interested in participating in GSoC 2023. I would like to take part in the development of the coreboot, moreover I already have a bunch of commits in the flashrom. I find the "Libpayload based memtest payload" project interesting and have a few questions about it. 1) This project was added a few years ago, also coreboot payload of memtest based on memtest from 2019 (however, in 2022 memtest86+ v6 is released). So, maybe something has changed since that time and not reflected in the docs? I found such ticket: https://ticket.coreboot.org/issues/184 2) Do I understand correctly, that this payload should be memtest-fork with a difference that will be built on libpayload and a design that will allow multiple architectures to be added? 3) There are no mentors at the moment :( I would appreciate any feedback. -- Joursoir

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I need you help.
by email＠danwin1210.de March 14, 2023

March 14, 2023

Hello. I would like to install Coreboot on my Lenovo x230, but I don't know how to do that. Please tell me how to do it. I have done a lot of research on my own, but I just can't figure it out. I am not a computer educated person. I don't have a rasberry pie. Do I need it? And what are skulls and heads, and what is the difference between them and coreboot?

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Coreboot - Intel NUC
by Sandro March 9, 2023

March 9, 2023

Hello, I am contacting you to ask for your opinion. Weeks ago I bought an Intel NUC 11 N5105 (BNUC11ATKC40002 ). Since this board does not have any SATA port, I thought that I could use a SilverStone SST-ECS07 connected to the M.2 slot. When I try to set up the sata adapter connected to my main PC ( ASUS Mainboard ROG Crosshair VIII Hero WI-FI), I have no problems seeing the drives and their partitions.... As soon as I try the same but in the NUC, then the drives are not found......lots of problems booting, and most of the time I am not even able to enter the original Intel BIOS. I reached the Intel discord server and I was able to get some feedback from a NUC team member. You can see the communication with him at: https://discord.com/channels/554824368740630529/1076245516406493195 He was able to confirm the same issues on his side, that it is a problem with this specific model BIOS. And that on other models it works. Sadly, he also gave me no realistic hopes of receiving a BIOS fix from Intel. Since I cannot return the products back I am really sad to have just wasted lots of money on these things and not being able to use them. This is when I came in contact with Coreboot.... this gave me a small light of hope.... Since I really do not know anything about this subject, neither if this would work on this specific motherboard..... I decided to ask for some opinions from you. Hopefully you could give me some good news :) Thank you very much and I wish you a good day. Best regards, Sandro

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[coreboot - Refactoring #460] (New) Make mainboards using the variant concept
by Felix Singer March 9, 2023

March 9, 2023

Issue #460 has been reported by Felix Singer. ---------------------------------------- Refactoring #460: Make mainboards using the variant concept https://ticket.coreboot.org/issues/460 * Author: Felix Singer * Status: New * Priority: Normal * Target version: none * Start date: 2023-02-14 ---------------------------------------- * asrock/ivybridge * asrock/b75pro3-m * asrock/h77pro4-m * asrock/haswell * asrock/b85m_pro4 * asrock/h81m-hds -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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