December 2023 - coreboot - mail.coreboot.org

How to add additional LPC decode ranges to Baytrail.
by Jose Trujillo Dec. 8, 2023

Dec. 8, 2023

Hello Dear Community: I am trying to enable UART port addresses 3e8 and 2e8 to one of my 2 superios I have attached to the same LPC port. I need 4 UART ports. Both superio chips work if I set 3f8 and 2f8 but one at the time (i need to disable the other SIO). Today I was looking at baytrail code but I got lost; I did not even find how the code add 3f8/2f8 in order to do the same to 3e8/2e8. i found the function "lpc_open_pmio_window()" but this didn't build for me on Baytrail. Do somebody know to to add LPC decode ranges for 3e8 and 2e8 on Baytrail? Please let me know. Jose Trujillo.

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[coreboot - Bug #519] (New) make gconfig - could not find glade file
by James Feeney Dec. 7, 2023

Dec. 7, 2023

Issue #519 has been reported by James Feeney. ---------------------------------------- Bug #519: make gconfig - could not find glade file https://ticket.coreboot.org/issues/519 * Author: James Feeney * Status: New * Priority: Normal * Target version: none * Start date: 2023-12-07 * Affected versions: 4.21 ---------------------------------------- $ git rev-parse HEAD 62c25351c101a3d5c7104aa6fc34e71990478dde Arch Linux make 4.4.1-2 $ make gconfig ... (gconf:825619): libglade-WARNING **: 09:26:11.670: could not find glade file '/sdb/coreboot.main/build/util/kconfig/gconf.glade' ** (gconf:825619): ERROR **: 09:26:11.673: GUI loading failed ! make: *** [build/util/kconfig/Makefile.real:47: gconfig] Trace/breakpoint trap (core dumped) $ find -name gconf.glade ./util/kconfig/gconf.glade $ ll /sdb/coreboot.main/build/util/kconfig/gconf.glade /bin/ls: cannot access '/sdb/coreboot.main/build/util/kconfig/gconf.glade': No such file or directory -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #518] (New) make xconfig - g++: fatal error: no input files
by James Feeney Dec. 7, 2023

Dec. 7, 2023

Issue #518 has been reported by James Feeney. ---------------------------------------- Bug #518: make xconfig - g++: fatal error: no input files https://ticket.coreboot.org/issues/518 * Author: James Feeney * Status: New * Priority: Normal * Category: build system * Target version: none * Start date: 2023-12-07 * Affected versions: 4.21 ---------------------------------------- $ git rev-parse HEAD 62c25351c101a3d5c7104aa6fc34e71990478dde Arch Linux make 4.4.1-2 $ make -d xconfig ... Found '/sdb/coreboot.main/util/kconfig/qconf.cc'. ... No implicit rule found for '/sdb/coreboot.main/util/kconfig/qconf.cc'. ... Finished prerequisites of target file 'build/util/kconfig/qconf.o'. Must remake target 'build/util/kconfig/qconf.o'. /sdb/coreboot.main/util/kconfig/Makefile.inc:63: update target 'build/util/kconfig/qconf.o' due to: target does not exist ... g++: fatal error: no input files compilation terminated. ... -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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Baytrail issue to communicate with superios.
by Jose Trujillo Dec. 6, 2023

Dec. 6, 2023

Hello All: I hope you are doing great. The system: Baytrail E3845, 4GB DDR3, fintek (f81803a) @0x4e and Winbond (w83627dhg) @0x2e, etc... I just built coreboot (master) the last few days, everything works wonderfully except 2 things: - Libgfxinit probably because this board is using the AUX channel instead DDI to communicate with the monitors; seems to me libgfxinit cannot find monitors thru DP ports but I could be wrong because neither VGA gets initialized; and eventually Linux always initialize the video correctly. - SuperIOs not working; "cat /proc/interrupts" shows not activity from any serial port to any processor, but, I set accordingly (konfig, devicetree and superio.asl) I will check on Monday if the route definitions of "irqroute.h" are ok. Using "superiotool" to scan for SIO devices finds Winbond W83627DHG and dumped all its registries but doesn't show Fintek f81803 because of lack of support, so, data exchange between the processor and the SIO chips via LPC port seems to be fine, maybe just need to fix the interrupt issues. Any help will be highly appreciated, Thank you, JT

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Announcement: flashrom-stable continues as flashprog
by Nico Huber Dec. 6, 2023

Dec. 6, 2023

Hi everybody! as you may know already, flashrom-stable was removed from review.coreboot.org a while ago. flashrom-stable was a short- lived semi-fork, based on flashrom v1.2 [1]. The effort to keep developing a stable flash programming tool for everyone, however, shall continue. I have hence renamed flashrom-stable to *flashprog*. Now it's definitely a fork. The main reason for the fork is that I saw the flashrom master (now main) branch to become unmaintainable. Probably because we merged too much code together, without actually managing to work together on a product. Beside names, I tried to keep everything as usual. There's a wiki (slowly filled with contents from the old one) https://flashprog.org/ an IRC channel #flashprog on libera.chat and a mailing list, of course flashprog(a)flashprog.org managed at https://mail.sourcearcade.org/postorius/lists/flashprog.flashprog.org/ Review continues on a Gerrit instance, albeit on https://review.sourcearcade.org/ And you can clone the repository from a GitHub mirror https://github.com/SourceArcade/flashprog.git Now that all this is done, I hope to return to work on the source code again. There are still many patches open that were pending for flashrom-stable. And it looks like the next release candidate is only one commit away :) So stay tuned! Nico [1] https://mail.coreboot.org/hyperkitty/list/flashrom-stable@flashrom.org/thre…

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Bootflow on ARM64 Server Discussion
by mina＠coreboot.org Dec. 5, 2023

Dec. 5, 2023

Thank you to all who were able to join the discussion pertaining to Bootflow on ARM64 server. Please access the overview of the meeting using the link below: https://docs.google.com/document/d/1z3fLdUmbOBKvHJfub8ki9YWjuqpK_1PY0H4BWwm… .

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Linux boot delayed by value of generic.reset_off_delay_ms (touchscreen reset)?
by Paul Menzel Dec. 5, 2023

Dec. 5, 2023

Dear coreboot folks, On the Dell Latitude 5430 Chromebook (google/brya/var/crota) there is a delay of 160 ms during startup in the Linux kernel [1]: [ 0.000000] microcode: microcode updated early to revision 0x430, date = 2023-06-07 [ 0.000000] Linux version 5.15.124-20281-g306376f9e9db (chrome-bot@chromeos-release-builder-us-central1-c-x32-9-oel9) (Chromium OS 17.0_pre496208_p20230501-r16 clang version 17.0.0 (/mnt/host/source/src/third_party/llvm-project 98f5a340975bc00197c57e39eb4ca26e2da0e8a2), LLD 17.0.0) #1 SMP PREEMPT Mon Oct 2 18:31:36 PDT 2023 […] [ 0.150271] ACPI: PM: Power Resource [PR00] [ 0.313289] ACPI: PM: Power Resource [PR01] A @google.com person commented, that this *could* be caused by the reset delay of the ELAN touchscreen. From `src/third_party/coreboot/src/mainboard/google/brya/variants/crota/overridetree.cb`: device ref i2c3 on chip drivers/i2c/hid register "generic.hid" = ""ELAN900C"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" register "generic.reset_delay_ms" = "150" register "generic.reset_off_delay_ms" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "generic.enable_delay_ms" = "6" register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 0x16 on end end end As I have been bitten the last time, I tried to flash a Dell Chromebook, I am weary to test, so I am asking here. > The delay is unavoidable, although I suppose there's room for > improvement on making ACPI power sequencing parallelizable or > otherwise deferring it until the device is actually getting probed > (preferably using asynchronous probe, since this is a slow device -- > ChromeOS tends to configure touchscreen drivers for async probe > already, or else loaded as modules). > > Perhaps you can take this problem upstream if you'd like to work on > something, but from a ChromeOS perspective this is either Intended > Behavior or a Feature Request. I don't think we're interested in > tracking this as a Feature Request here. During startup this reset delay should not hold up the boot, should it? Could the firmware reset the touchscreen, and somehow message the OS, that it’s not needed anymore? Kind regards, Paul [1]: https://issuetracker.google.com/issues/303565666 PS: I was unable to change the issue title to correct PR01 to PR00.

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48 hours before DUG #4 & vPub 0x9 opensource online party!
by Mike Banon Dec. 5, 2023

Dec. 5, 2023

Dear friends, I invite you to a joint DUG #4 & vPub 0x9 event that starts this Thursday at 5 PM UTC - in exactly 48 hours since this e-mail. Would you like to learn & discuss about: * coreboot-based Dasharo firmware distribution and its unique features? * cool hardware devices supporting the opensource firmwares, like NovaCustom new laptop? * opensource firmware world and its current events in general, i.e. AMD OpenSIL news? Then this upcoming event - is an excellent opportunity for you to have a great time in a friendly company of firmware enthusiasts. The 1st part of our event - DUG #4 - is dedicated to Dasharo distribution of coreboot opensource firmware with advanced features like GUI & FLASHBIOS and the ecosystem around it. DUG will take place between 5-7 PM UTC - and then around 7 PM UTC will switch to vPub opensource online party! The past joint events have been highly successful and I'm sure you will find this one interesting as well ;-) Both sound/video and text chats will be available for your convenience More details and Join links are available here - [*] https://vpub.dasharo.com/e/11/dasharo-user-group-4 P.S. to avoid missing out future events, join our Matrix or tiny-volume event notification newsletter: [*] https://matrix.to/#/#dasharo-osf-vpub:matrix.org [*] https://newsletter.3mdeb.com/subscription/0_K65I7ro (just ~4 e-mails per year) -- Best regards, Mike Banon Open Source Community Manager of 3mdeb - https://3mdeb.com/

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[coreboot - Bug #516] (New) brya/var/crota: `ACPI BIOS Error (bug): Failure creating named object [\_SB.MPTS], AE_ALREADY_EXISTS (20210730/dswload2-327)`
by Paul Menzel Dec. 4, 2023

Dec. 4, 2023

Issue #516 has been reported by Paul Menzel. ---------------------------------------- Bug #516: brya/var/crota: `ACPI BIOS Error (bug): Failure creating named object [\_SB.MPTS], AE_ALREADY_EXISTS (20210730/dswload2-327)` https://ticket.coreboot.org/issues/516 * Author: Paul Menzel * Status: New * Priority: Normal * Target version: none * Start date: 2023-12-02 ---------------------------------------- On the Dell Latitude 5430 Chromebook (brya/var/crota) with ChromeOS, Linux 5.15.133 reports an ACPI error: [ 0.000000] Linux version 5.15.133-20573-g839a3133d611 (chrome-bot@chromeos-release-builder-us-central1-a-x32-6-ibti) (Chromium OS 17.0_pre498229-r6 clang version 17.0.0 (/mnt/host/source/src/third_party/llvm-project 14f0776550b5a49e1c42f49a00213f7f3fa047bf), LLD 17.0.0) #1 SMP PREEMPT Sun Nov 26 18:55:03 PST 2023 2023-12-01T11:43:58.591525Z INFO kernel: [ 0.000000] Command line: cros_secure console= loglevel=7 init=/sbin/init cros_secure drm.trace=0x106 root=/dev/dm-0 rootwait ro dm_verity.error_behavior=3 dm_verity.max_bios=-1 dm_verity.dev_wait=1 dm="1 vroot none ro 1,0 6348800 verity payload=PARTUUID=12e8cf21-bcc0-49b5-85bb-56fb8102f7d4/PARTNROFF=1 hashtree=PARTUUID=12e8cf21-bcc0-49b5-85bb-56fb8102f7d4/PARTNROFF=1 hashstart=6348800 alg=sha256 root_hexdigest=4ad313ce4c441485f2be87533efe22a0d8b61bffb78260d17ccd2672e7edb538 salt=8051d68355ccfca99de821939b957ff34d38b866a2951a595e4c0613a1c51f97" noinitrd vt.global_cursor_default=0 kern_guid=12e8cf21-bcc0-49b5-85bb-56fb8102f7d4 add_efi_memmap noresume i915.modeset=1 ramoops.ecc=1 tpm_tis.force=0 intel_pmc_core.warn_on_s0ix_failures=1 i915.enable_guc=3 i915.enable_dc=4 xdomain=0 swiotlb=65536 intel_iommu=on i915.enable_psr=1 […] [ 0.000000] DMI: Google Crota/Crota, BIOS Google_Crota.14505.456.0 04/21/2023 […] [ 0.146114] ACPI BIOS Error (bug): Failure creating named object [\_SB.MPTS], AE_ALREADY_EXISTS (20210730/dswload2-327) [ 0.146117] ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20210730/psobject-220) […] -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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Bootflow on ARM64 Server Discussion
by mina＠coreboot.org Dec. 4, 2023

Dec. 4, 2023

Dear community, You are invited to the upcoming meeting on Tuesday, December 5, 2023, from 7:00 PM to 8:00 PM GMT, to continue the discussion of issues pertaining to the ARM64 server.[1] Here are links to some relevant documents to be considered: * ARM Server Base Boot Security Requirements PDF Download * ARM Base Boot Requirements * Background doc on ARM servers using ACPI & SMBIOS [1]meet.google.com/sxc-vcax-xwg

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