November 2019 - coreboot - mail.coreboot.org

OpenBSD won't install on an x220 Thinkpad with Coreboot
by Robert Milton April 12, 2020

April 12, 2020

I'm trying to get OpenBSD to install on an x220 Thinkpad with Coreboot/SeaBIOS but I'm running into two problems: the ethernet device doesn't work and OpenBSD doesn't detect my HDD. dmesg said em0 wouldn't load because the EEPROM had an invalid signature. I have no idea why OpenBSD doesn't see my HDD though. It's strange because everything works fine under Linux. And I cannot seem to mount a usb drive under the OpenBSD installer to attach dmesg errors. I originally posted this as a bug report to bug report mailing list but Theo said it would be better suited for Coreboot's and wasn't a bug in OpenBSD.

4 4

Mainboard porting assistance
by Benjamin Doron April 9, 2020

April 9, 2020

Hi all, I own an Acer Aspire VN7-572G and have not been impressed with its OEM firmware. After discovering that it does not utilise Intel's Boot Guard technology, that several Skylake and Kabylake laptops (it has a Skylake chip, but I read that the platforms are similar) have received successful coreboot ports and reading the porting guide on the wiki, I figured that I could give porting coreboot to my laptop a shot. When I was done, I figured that I had an image that might boot so I flashed it to my laptop with a Raspberry Pi and a SOIC clip. However, here's what it does: a) It powers on quietly, as expected; b) The backlight and power LED light up; c) The fans spin up to high and then it stays that way. It does nothing else. The display is dark too. After 15 minutes and a second attempt, I figured that I could no longer blame anything on a long first boot-up and gave up and flashed back to stock. Now, in all honesty I should have tried first without cleaning Intel ME but I find it so much more likely that I did something wrong than that cleaning ME was the sole problem. Can anyone advise me on how to continue? My code is here: https://github.com/benjamindoron/coreboot

7 42

Optiplex 790 now has preliminary support by coreboot
by Taiidan＠gmx.com Jan. 15, 2020

Jan. 15, 2020

https://review.coreboot.org/21774 In case anyone else didn't notice - It is a sandy/ivy system with IOMMU. This is great and should help get coreboot in to the corporate user world.

2 1

Coverity
by awokd Dec. 31, 2019

Dec. 31, 2019

Could a Coreboot Coverity admin please re-run the scan against master? Looks like the last analyzed version was from Sep 24, 2019. I would like to see what AGESA issues remain. -- - don't top post Mailing list etiquette: - trim quoted reply to only relevant portions - when possible, copy and paste text instead of screenshots

2 2

Call to FSP_FSP_INIT never returns back
by Naveen Chaudhary Dec. 13, 2019

Dec. 13, 2019

Hi All, Need some guidance. Please read. I am porting coreboot for a "Broadwell D 1519" based motherboard which has both Memory Down as well as 2 DIMM slots. Hence, I built an image for Facebook Watson since its the closest mainboard with no code changes. The call from FSP_FSP_INIT never returns to the ChipsetFspReturnPoint( ). Probably something crashed inside the FSP or something else. This is possibly happening because I have passed no information regarding the RAM chips (down or DIMM) from romstage_fsp_rt_buffer_callback(). I have following 2 questions : 1. How can I see the default values for FSP UDP structure, so that I get to know what I need to modify? BCT tool does not dump that info. 2. In intel/soc/fsp_broadwell/ , the save_dimm_info() is done after FSP_FSP_INIT returns. Shouldn't the SPD details have been fetched before and passed to the FSP_FSP_INIT, as it is this API that handles the memory init. Regards, Naveen

4 10

PCIe Hotplug for Thunderbolt and U.2
by Jeremy Soller Dec. 4, 2019

Dec. 4, 2019

This is to continue the discussion from the coreboot leadership meeting. Thunderbolt devices are not correctly initialized by Coreboot such that the OS can boot without kernel parameters and allow for Thunderbolt hotplugging. Additional bus numbers and memory must be allocated. I will be working on support for this for our System76 mainboards. Here were the notes taken about it during the meeting, see 9 October 2019, PCIe Hotplug on newer Intel socs: https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgK… -- Jeremy Soller System76 Engineering Manager jeremy(a)system76.com

3 7

AMD binaryPI board removals
by Kyösti Mälkki Dec. 4, 2019

Dec. 4, 2019

Hi As of 27th November and commit [1] platforms using AMD binaryPI blobs have been disabled from automatic build testing. The following are affected: * amd/bettong * amd/db-ft3b-lc * amd/lamar * amd/olivehillplus * bap/ode_e21XX This is inline with CAR_GLOBAL_MIGRATION deprecation as mandated by 4.11 release requirements. You should expect that the board sources and platform support will disappear by 14th December, at latest, unless you show interest *and* are able to provide bootlogs for the boards above. PCEngines APU2 and variants are an exception to this, they were converted to POSTCAR_STAGE and work away from ROMCC_BOOTBLOCK shows promising results. [1] https://review.coreboot.org/c/coreboot/+/37170 Regards, Kyösti Mälkki

4 13

Intel ME ignition firmware becoming available
by Michal Zygowski Nov. 29, 2019

Nov. 29, 2019

Just in case somebody doesn't know yet.. https://edk2.groups.io/g/devel/message/50920 https://edk2.groups.io/g/devel/message/50921 -- Michał Żygowski Firmware Engineer http://3mdeb.com | @3mdeb_com

3 2

System hangs during pci init
by Kuppa Omkar Nov. 27, 2019

Nov. 27, 2019

Hi everyone, I'm trying to boot camelback mountain platform with coreboot 4.10. It looks like the system halts during pci devices initialization. The following is the log from the system. I added traces in expected functions but none of them are called. romstage_main_continue status: 0 hob_list_ptr: 7f100000 FSP Status: 0x0 CBMEM: IMD: root @ 7efff000 254 entries. IMD: root @ 7effec00 62 entries. CBFS: 'Master Header Locator' located CBFS at [200200:800000) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 1dd40 size f7fa Decompressing stage fallback/ramstage @ 0x7eeb3fc0 (1350040 bytes) Loading module at 7eeb4000 with entry 7eeb4000. filesize: 0x1fd98 memsize: 0x149958 Processing 2587 relocs. Offset value of 0x7e0b4000 coreboot-4.10-ae317695e3f03d55fbba1805ff06e004383e67c8 Tue Nov 26 09:26:56 UTC 2019 ramstage starting (log level: 7)... BS: BS_PRE_DEVICE times (us): entry 6302 run 5917 exit 6302 CBFS: 'Master Header Locator' located CBFS at [200200:800000) CBFS: Locating 'cpu_microcode_blob.bin' CBFS: Found @ offset 44c0 size 19800 microcode: sig=0x50663 pf=0x10 revision=0x700000c CPUID: 00050663 Cores: 12 Stepping: V2 Revision ID: 05 msr(17) = 0010000000000000 msr(ce) = 20080833f3811600 BS: BS_DEV_INIT_CHIPS times (us): entry 6302 run 39810 exit 6302 Enumerating buses... enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 7) CPU_CLUSTER: 0 enabled enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 6) DOMAIN: 0000 enabled PCI: pci_scan_bus for bus 00 enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) FSP Header Version: 1 FSP Revision: 3.3 PCI: 00:00.0 [8086/6f00] enabled PCI: 00:01.0 [8086/6f02] enabled PCI: 00:02.0 subordinate bus PCI Express PCI: 00:02.0 [8086/6f04] enabled PCI: 00:02.2 subordinate bus PCI Express PCI: 00:02.2 [8086/6f06] enabled PCI: 00:03.0 [8086/6f08] enabled PCI: 00:05.0 [8086/6f28] enabled PCI: 00:05.1 [8086/6f29] enabled PCI: 00:05.2 [8086/6f2a] enabled PCI: 00:05.4 [8086/6f2c] enabled PCI: 00:05.6 [8086/6f39] enabled PCI: 00:06.0 [8086/6f10] enabled PCI: 00:06.1 [8086/6f11] enabled PCI: 00:06.2 [8086/6f12] enabled PCI: 00:06.3 [8086/6f13] enabled PCI: 00:06.4 [8086/6f14] enabled PCI: 00:06.5 [8086/6f15] enabled PCI: 00:06.6 [8086/6f16] enabled PCI: 00:06.7 [8086/6f17] enabled PCI: 00:07.0 [8086/6f18] enabled PCI: 00:07.1 [8086/6f19] enabled PCI: 00:07.2 [8086/6f1a] enabled PCI: 00:07.3 [8086/6f1b] enabled PCI: 00:07.4 [8086/6f1c] enabled enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) PCI: 00:14.0 [8086/8c31] enabled PCI: 00:16.0 [8086/8c3a] enabled PCI: 00:16.1 [8086/8c3b] enabled PCI: 00:16.2 [8086/8c3c] enabled PCI: 00:16.3 [8086/8c3d] enabled enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) PCI: Static device PCI: 00:19.0 not found, disabling it. enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) PCI: Static device PCI: 00:1d.0 not found, disabling it. enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) PCI: 00:1f.0 [8086/8c54] enabled enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) PCI: 00:1f.2 [8086/8c02] enabled enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) PCI: 00:1f.3 [8086/8c22] enabled enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) PCI: Static device PCI: 00:1f.5 not found, disabling it. PCI: 00:1f.6 [8086/8c24] enabled PCI: Leftover static devices: PCI: 00:19.0 PCI: 00:1d.0 PCI: 00:1f.5 PCI: Check your devicetree.cb. PCI: pci_scan_bus for bus 01 scan_bus: scanning of bus PCI: 00:01.0 took 211304 usecs PCI: pci_scan_bus for bus 02 PCI: 02:00.0 [8086/6f50] enabled PCI: 02:00.1 [8086/6f51] enabled PCI: 02:00.2 [8086/6f52] enabled PCI: 02:00.3 [8086/6f53] enabled PCIE CLK PM is not supported by endpoint ASPM: Enabled None PCIE CLK PM is not supported by endpoint ASPM: Enabled None PCIE CLK PM is not supported by endpoint ASPM: Enabled None PCIE CLK PM is not supported by endpoint ASPM: Enabled None Failed to enable LTR for dev = PCI: 02:00.0 Failed to enable LTR for dev = PCI: 02:00.1 Failed to enable LTR for dev = PCI: 02:00.2 Failed to enable LTR for dev = PCI: 02:00.3 scan_bus: scanning of bus PCI: 00:02.0 took 436766 usecs PCI: pci_scan_bus for bus 03 PCI: 03:00.0 [8086/15ac] enabled PCI: 03:00.1 [8086/15ac] enabled Enabling Common Clock Configuration PCIE CLK PM is not supported by endpoint ASPM: Enabled L1 Enabling Common Clock Configuration PCIE CLK PM is not supported by endpoint ASPM: Enabled L1 scan_bus: scanning of bus PCI: 00:02.2 took 341959 usecs PCI: pci_scan_bus for bus 04 PCI: 04:00.0 [10de/128b] enabled PCI: 04:00.1 [10de/0e0f] enabled scan_bus: scanning of bus PCI: 00:03.0 took 276570 usecs scan_bus: scanning of bus PCI: 00:1f.0 took 2 usecs scan_bus: scanning of bus PCI: 00:1f.3 took 2 usecs scan_bus: scanning of bus DOMAIN: 0000 took 2992237 usecs scan_bus: scanning of bus Root Device took 3017444 usecs done FspNotify(EnumInitPhaseAfterPciEnumeration) Returned from FspNotify(EnumInitPhaseAfterPciEnumeration) BS: BS_DEV_ENUMERATE times (us): entry 6302 run 3037335 exit 16712 found VGA at PCI: 04:00.0 Setting up VGA for PCI: 04:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:03.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... fsp_mem_base: 0x7f000000 fsp_mem_len: 0x00800000 tseg_base: 0x7f800000 tseg_len: 0x00800000 highmem_size: 0x00000000 80000000 tolm: 0x80000000 Top of system low memory: 0x80000000 FSP memory location: 0x7f000000 (size: 8M) tseg: 0x7f800000 (size: 0x00800000) Available memory above 4GB: 2048M Adding PCIe config bar base=0x80000000 size=0x10000000 PCI: 00:05.6 register 10(ffffffff), read-only ignoring it PCI: 00:05.6 register 14(ffffffff), read-only ignoring it PCI: 00:05.6 register 18(ffffffff), read-only ignoring it PCI: 00:05.6 register 1c(ffffffff), read-only ignoring it PCI: 00:05.6 register 20(ffffffff), read-only ignoring it PCI: 00:05.6 register 24(ffffffff), read-only ignoring it PCI: 00:05.6 register 30(ffffffff), read-only ignoring it PCI: 00:06.0 register 10(ffffffff), read-only ignoring it PCI: 00:06.0 register 14(ffffffff), read-only ignoring it PCI: 00:06.0 register 18(ffffffff), read-only ignoring it PCI: 00:06.0 register 1c(ffffffff), read-only ignoring it PCI: 00:06.0 register 20(ffffffff), read-only ignoring it PCI: 00:06.0 register 24(ffffffff), read-only ignoring it PCI: 00:06.0 register 30(ffffffff), read-only ignoring it PCI: 00:06.1 register 10(ffffffff), read-only ignoring it PCI: 00:06.1 register 14(ffffffff), read-only ignoring it PCI: 00:06.1 register 18(ffffffff), read-only ignoring it PCI: 00:06.1 register 1c(ffffffff), read-only ignoring it PCI: 00:06.1 register 20(ffffffff), read-only ignoring it PCI: 00:06.1 register 24(ffffffff), read-only ignoring it PCI: 00:06.1 register 30(ffffffff), read-only ignoring it PCI: 00:06.2 register 10(ffffffff), read-only ignoring it PCI: 00:06.2 register 14(ffffffff), read-only ignoring it PCI: 00:06.2 register 18(ffffffff), read-only ignoring it PCI: 00:06.2 register 1c(ffffffff), read-only ignoring it PCI: 00:06.2 register 20(ffffffff), read-only ignoring it PCI: 00:06.2 register 24(ffffffff), read-only ignoring it PCI: 00:06.2 register 30(ffffffff), read-only ignoring it PCI: 00:06.3 register 10(ffffffff), read-only ignoring it PCI: 00:06.3 register 14(ffffffff), read-only ignoring it PCI: 00:06.3 register 18(ffffffff), read-only ignoring it PCI: 00:06.3 register 1c(ffffffff), read-only ignoring it PCI: 00:06.3 register 20(ffffffff), read-only ignoring it PCI: 00:06.3 register 24(ffffffff), read-only ignoring it PCI: 00:06.3 register 30(ffffffff), read-only ignoring it PCI: 00:06.4 register 10(ffffffff), read-only ignoring it PCI: 00:06.4 register 14(ffffffff), read-only ignoring it PCI: 00:06.4 register 18(ffffffff), read-only ignoring it PCI: 00:06.4 register 1c(ffffffff), read-only ignoring it PCI: 00:06.4 register 20(ffffffff), read-only ignoring it PCI: 00:06.4 register 24(ffffffff), read-only ignoring it PCI: 00:06.4 register 30(ffffffff), read-only ignoring it PCI: 00:06.5 register 10(ffffffff), read-only ignoring it PCI: 00:06.5 register 14(ffffffff), read-only ignoring it PCI: 00:06.5 register 18(ffffffff), read-only ignoring it PCI: 00:06.5 register 1c(ffffffff), read-only ignoring it PCI: 00:06.5 register 20(ffffffff), read-only ignoring it PCI: 00:06.5 register 24(ffffffff), read-only ignoring it PCI: 00:06.5 register 30(ffffffff), read-only ignoring it PCI: 00:06.6 register 10(ffffffff), read-only ignoring it PCI: 00:06.6 register 14(ffffffff), read-only ignoring it PCI: 00:06.6 register 18(ffffffff), read-only ignoring it PCI: 00:06.6 register 1c(ffffffff), read-only ignoring it PCI: 00:06.6 register 20(ffffffff), read-only ignoring it PCI: 00:06.6 register 24(ffffffff), read-only ignoring it PCI: 00:06.6 register 30(ffffffff), read-only ignoring it PCI: 00:06.7 register 10(ffffffff), read-only ignoring it PCI: 00:06.7 register 14(ffffffff), read-only ignoring it PCI: 00:06.7 register 18(ffffffff), read-only ignoring it PCI: 00:06.7 register 1c(ffffffff), read-only ignoring it PCI: 00:06.7 register 20(ffffffff), read-only ignoring it PCI: 00:06.7 register 24(ffffffff), read-only ignoring it PCI: 00:06.7 register 30(ffffffff), read-only ignoring it PCI: 00:07.0 register 10(ffffffff), read-only ignoring it PCI: 00:07.0 register 14(ffffffff), read-only ignoring it PCI: 00:07.0 register 18(ffffffff), read-only ignoring it PCI: 00:07.0 register 1c(ffffffff), read-only ignoring it PCI: 00:07.0 register 20(ffffffff), read-only ignoring it PCI: 00:07.0 register 24(ffffffff), read-only ignoring it PCI: 00:07.0 register 30(ffffffff), read-only ignoring it PCI: 00:07.1 register 10(ffffffff), read-only ignoring it PCI: 00:07.1 register 14(ffffffff), read-only ignoring it PCI: 00:07.1 register 18(ffffffff), read-only ignoring it PCI: 00:07.1 register 1c(ffffffff), read-only ignoring it PCI: 00:07.1 register 20(ffffffff), read-only ignoring it PCI: 00:07.1 register 24(ffffffff), read-only ignoring it PCI: 00:07.1 register 30(ffffffff), read-only ignoring it PCI: 00:07.2 register 10(ffffffff), read-only ignoring it PCI: 00:07.2 register 14(ffffffff), read-only ignoring it PCI: 00:07.2 register 18(ffffffff), read-only ignoring it PCI: 00:07.2 register 1c(ffffffff), read-only ignoring it PCI: 00:07.2 register 20(ffffffff), read-only ignoring it PCI: 00:07.2 register 24(ffffffff), read-only ignoring it PCI: 00:07.2 register 30(ffffffff), read-only ignoring it PCI: 00:07.3 register 10(ffffffff), read-only ignoring it PCI: 00:07.3 register 14(ffffffff), read-only ignoring it PCI: 00:07.3 register 18(ffffffff), read-only ignoring it PCI: 00:07.3 register 1c(ffffffff), read-only ignoring it PCI: 00:07.3 register 20(ffffffff), read-only ignoring it PCI: 00:07.3 register 24(ffffffff), read-only ignoring it PCI: 00:07.3 register 30(ffffffff), read-only ignoring it PCI: 00:07.4 register 10(ffffffff), read-only ignoring it PCI: 00:07.4 register 14(ffffffff), read-only ignoring it PCI: 00:07.4 register 18(ffffffff), read-only ignoring it PCI: 00:07.4 register 1c(ffffffff), read-only ignoring it PCI: 00:07.4 register 20(ffffffff), read-only ignoring it PCI: 00:07.4 register 24(ffffffff), read-only ignoring it PCI: 00:07.4 register 30(ffffffff), read-only ignoring it Done reading resources. Setting resources... PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:01.0 24 <- [0x00fbffbfff - 0x00fbffbffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:01.0 20 <- [0x00fbffbfff - 0x00fbffbffe] size 0x00000000 gran 0x14 bus 01 mem PCI: 00:02.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:02.0 24 <- [0x00fbffbfff - 0x00fbffbffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:02.0 20 <- [0x00fb700000 - 0x00fb7fffff] size 0x00100000 gran 0x14 bus 02 mem PCI: 02:00.0 10 <- [0x00fb700000 - 0x00fb701fff] size 0x00002000 gran 0x0d mem64 PCI: 02:00.1 10 <- [0x00fb702000 - 0x00fb703fff] size 0x00002000 gran 0x0d mem64 PCI: 02:00.2 10 <- [0x00fb704000 - 0x00fb705fff] size 0x00002000 gran 0x0d mem64 PCI: 02:00.3 10 <- [0x00fb706000 - 0x00fb707fff] size 0x00002000 gran 0x0d mem64 PCI: 00:02.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io PCI: 00:02.2 24 <- [0x00fb200000 - 0x00fb6fffff] size 0x00500000 gran 0x14 bus 03 prefmem PCI: 00:02.2 20 <- [0x00fb800000 - 0x00fb8fffff] size 0x00100000 gran 0x14 bus 03 mem PCI: 03:00.0 10 <- [0x00fb200000 - 0x00fb3fffff] size 0x00200000 gran 0x15 prefmem64 PCI: 03:00.0 20 <- [0x00fb600000 - 0x00fb603fff] size 0x00004000 gran 0x0e prefmem64 PCI: 03:00.0 30 <- [0x00fb800000 - 0x00fb87ffff] size 0x00080000 gran 0x13 romem PCI: 03:00.1 10 <- [0x00fb400000 - 0x00fb5fffff] size 0x00200000 gran 0x15 prefmem64 PCI: 03:00.1 20 <- [0x00fb604000 - 0x00fb607fff] size 0x00004000 gran 0x0e prefmem64 PCI: 03:00.1 30 <- [0x00fb880000 - 0x00fb8fffff] size 0x00080000 gran 0x13 romem PCI: 00:03.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 04 io PCI: 00:03.0 24 <- [0x00f0000000 - 0x00f9ffffff] size 0x0a000000 gran 0x14 bus 04 prefmem PCI: 00:03.0 20 <- [0x00fa000000 - 0x00fb0fffff] size 0x01100000 gran 0x14 bus 04 mem PCI: 04:00.0 10 <- [0x00fa000000 - 0x00faffffff] size 0x01000000 gran 0x18 mem PCI: 04:00.0 14 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x1b prefmem64 PCI: 04:00.0 1c <- [0x00f8000000 - 0x00f9ffffff] size 0x02000000 gran 0x19 prefmem64 PCI: 04:00.0 24 <- [0x0000001000 - 0x000000107f] size 0x00000080 gran 0x07 io PCI: 04:00.0 30 <- [0x00fb000000 - 0x00fb07ffff] size 0x00080000 gran 0x13 romem PCI: 04:00.1 10 <- [0x00fb080000 - 0x00fb083fff] size 0x00004000 gran 0x0e mem PCI: 00:05.4 10 <- [0x00fb910000 - 0x00fb910fff] size 0x00001000 gran 0x0c mem PCI: 00:14.0 10 <- [0x00fb900000 - 0x00fb90ffff] size 0x00010000 gran 0x10 mem64 PCI: 00:16.0 10 <- [0x00fb915000 - 0x00fb91500f] size 0x00000010 gran 0x04 mem64 PCI: 00:16.1 10 <- [0x00fb916000 - 0x00fb91600f] size 0x00000010 gran 0x04 mem64 PCI: 00:16.2 10 <- [0x0000002050 - 0x0000002057] size 0x00000008 gran 0x03 io PCI: 00:16.2 14 <- [0x0000002078 - 0x000000207b] size 0x00000004 gran 0x02 io PCI: 00:16.2 18 <- [0x0000002058 - 0x000000205f] size 0x00000008 gran 0x03 io PCI: 00:16.2 1c <- [0x000000207c - 0x000000207f] size 0x00000004 gran 0x02 io PCI: 00:16.2 20 <- [0x0000002040 - 0x000000204f] size 0x00000010 gran 0x04 io PCI: 00:16.3 10 <- [0x0000002060 - 0x0000002067] size 0x00000008 gran 0x03 io PCI: 00:16.3 14 <- [0x00fb911000 - 0x00fb911fff] size 0x00001000 gran 0x0c mem PCI: 00:1f.2 10 <- [0x0000002068 - 0x000000206f] size 0x00000008 gran 0x03 io PCI: 00:1f.2 14 <- [0x0000002080 - 0x0000002083] size 0x00000004 gran 0x02 io PCI: 00:1f.2 18 <- [0x0000002070 - 0x0000002077] size 0x00000008 gran 0x03 io PCI: 00:1f.2 1c <- [0x0000002084 - 0x0000002087] size 0x00000004 gran 0x02 io PCI: 00:1f.2 20 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io PCI: 00:1f.2 24 <- [0x00fb913000 - 0x00fb9137ff] size 0x00000800 gran 0x0b mem PCI: 00:1f.3 10 <- [0x00fb914000 - 0x00fb9140ff] size 0x00000100 gran 0x08 mem64 PCI: 00:1f.3 20 <- [0x0000002020 - 0x000000203f] size 0x00000020 gran 0x05 io PCI: 00:1f.6 10 <- [0x00fb912000 - 0x00fb912fff] size 0x00001000 gran 0x0c mem64 Done setting resources. Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 6303 run 11571183 exit 6302 Enabling resources... PCI: 00:00.0 subsystem <- 8086/6f00 PCI: 00:00.0 cmd <- 400 PCI: 00:01.0 bridge ctrl <- 0003 PCI: 00:01.0 cmd <- 00 PCI: 00:02.0 bridge ctrl <- 0003 PCI: 00:02.0 cmd <- 06 PCI: 00:02.2 bridge ctrl <- 0003 PCI: 00:02.2 cmd <- 06 PCI: 00:03.0 bridge ctrl <- 000b PCI: 00:03.0 cmd <- 07 PCI: 00:05.1 cmd <- 04 PCI: 00:05.2 cmd <- 04 PCI: 00:05.4 cmd <- 06 PCI: 00:05.6 cmd <- ffff PCI: 00:06.0 cmd <- ffff PCI: 00:06.1 cmd <- ffff PCI: 00:06.2 cmd <- ffff PCI: 00:06.3 cmd <- ffff PCI: 00:06.4 cmd <- ffff PCI: 00:06.5 cmd <- ffff PCI: 00:06.6 cmd <- ffff PCI: 00:06.7 cmd <- ffff PCI: 00:07.0 cmd <- ffff PCI: 00:07.1 cmd <- ffff PCI: 00:07.2 cmd <- ffff PCI: 00:07.3 cmd <- ffff PCI: 00:07.4 cmd <- ffff PCI: 00:14.0 subsystem <- 8086/8c31 PCI: 00:14.0 cmd <- 02 PCI: 00:16.0 cmd <- 06 PCI: 00:16.1 cmd <- 02 PCI: 00:16.2 cmd <- 01 PCI: 00:16.3 cmd <- 03 PCI: 00:1f.2 subsystem <- 8086/8c02 PCI: 00:1f.2 cmd <- 03 PCI: 00:1f.3 cmd <- 03 PCI: 00:1f.6 cmd <- 02 PCI: 02:00.0 cmd <- 06 PCI: 02:00.1 cmd <- 06 PCI: 02:00.2 cmd <- 06 PCI: 02:00.3 cmd <- 06 PCI: 03:00.0 cmd <- 02 PCI: 03:00.1 cmd <- 02 PCI: 04:00.0 cmd <- 03 PCI: 04:00.1 cmd <- 02 done. BS: BS_DEV_ENABLE times (us): entry 6302 run 327117 exit 6302 Initializing devices... calling init_dev() Root Device init ... Root Device init finished in 2134 usecs CPU_CLUSTER: 0 init ... MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Setting up local APIC... apic_id: 0x00 done. Setting up SMI for CPU Will perform SMM setup. CPU: Intel(R) Xeon(R) CPU D-1531 @ 2.20GHz. Loading module at 00030000 with entry 00030000. filesize: 0x130 memsize: 0x130 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 11 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...AP: slot 4 apic_id 1. AP: slot 7 apic_id 7. AP: slot 8 apic_id 6. AP: slot 5 apic_id 3. AP: slot 9 apic_id 2. AP: slot 6 apic_id 5. done. AP: slot 3 apic_id 9. AP: slot 2 apic_id 8. Waiting for 2nd SIPI to complete...done. AP: slot 11 apic_id b. AP: slot 10 apic_id a. AP: slot 1 apic_id 4. Loading module at 00038000 with entry 00038000. filesize: 0x1c0 memsize: 0x1c0 Processing 13 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 00038000. Will call 7eec5117(00000000) Installing SMM handler to 0x7f800000 Loading module at 7f810000 with entry 7f81002b. filesize: 0x188 memsize: 0x4190 Processing 11 relocs. Offset value of 0x7f810000 Loading module at 7f808000 with entry 7f808000. filesize: 0x1c0 memsize: 0x1c0 Processing 13 relocs. Offset value of 0x7f808000 SMM Module: placing jmp sequence at 7f807c00 rel16 0x03fd SMM Module: placing jmp sequence at 7f807800 rel16 0x07fd SMM Module: placing jmp sequence at 7f807400 rel16 0x0bfd SMM Module: placing jmp sequence at 7f807000 rel16 0x0ffd SMM Module: placing jmp sequence at 7f806c00 rel16 0x13fd SMM Module: placing jmp sequence at 7f806800 rel16 0x17fd SMM Module: placing jmp sequence at 7f806400 rel16 0x1bfd SMM Module: placing jmp sequence at 7f806000 rel16 0x1ffd SMM Module: placing jmp sequence at 7f805c00 rel16 0x23fd SMM Module: placing jmp sequence at 7f805800 rel16 0x27fd SMM Module: placing jmp sequence at 7f805400 rel16 0x2bfd SMM Module: stub loaded at 7f808000. Will call 7f81002b(00000000) Initializing Southbridge SMI... SMI_STS: PM1 TMROF New SMBASE 0x7f800000 In relocation handler: CPU 0 Relocation complete. Doing parallel SMM relocation. New SMBASE 0x7f800000 In relocation handler: CPU 0 New SMBASE 0x7f7ff000 In relocation handler: CPU 4 New SMBASE=0x7f7ff000 IEDBASE=0x7fc00000 New SMBASE 0x7f7fec00 New SMBASE 0x7f7fdc00 In relocation handler: CPU 9 New SMBASE=0x7f7fdc00 IEDBASE=0x7fc00000 In relocation handler: CPU 5 New SMBASE=0x7f7fec00 IEDBASE=0x7fc00000 Writing SMRR. base = 0x7f800006, mask=0xff800800 Writing SMRR. base = 0x7f800006, mask=0xff800800 Relocation complete. Relocation complete. microcode: Update skipped, already up-to-date New SMBASE 0x7f7ffc00 New SMBASE 0x7f7fe800 In relocation handler: CPU 6 New SMBASE=0x7f7fe800 IEDBASE=0x7fc00000 In relocation handler: CPU 1 New SMBASE=0x7f7ffc00 IEDBASE=0x7fc00000 New SMBASE 0x7f7fe000 In relocation handler: CPU 8 New SMBASE=0x7f7fe000 IEDBASE=0x7fc00000 New SMBASE 0x7f7fe400 In relocation handler: CPU 7 New SMBASE=0x7f7fe400 IEDBASE=0x7fc00000 New SMBASE 0x7f7fd800 In relocation handler: CPU 10 New SMBASE=0x7f7fd800 IEDBASE=0x7fc00000 New SMBASE 0x7f7fd400 In relocation handler: CPU 11 New SMBASE=0x7f7fd400 IEDBASE=0x7fc00000 microcode: Update skipped, already up-to-date Writing SMRR. base = 0x7f800006, mask=0xff800800 Writing SMRR. base = 0x7f800006, mask=0xff800800 Relocation complete. New SMBASE 0x7f7ff400 New SMBASE 0x7f7ff800 In relocation handler: CPU 3 New SMBASE=0x7f7ff400 IEDBASE=0x7fc00000 In relocation handler: CPU 2 Writing SMRR. base = 0x7f800006, mask=0xff800800 New SMBASE=0x7f800000 IEDBASE=0x7fc00000 Relocation complete. Writing SMRR. base = 0x7f800006, mask=0xff800800 microcode: Update skipped, already up-to-date Writing SMRR. base = 0x7f800006, mask=0xff800800 Writing SMRR. base = 0x7f800006, mask=0xff800800 Writing SMRR. base = 0x7f800006, mask=0xff800800 Writing SMRR. base = 0x7f800006, mask=0xff800800 Relocation complete. Relocation complete. microcode: Update skipped, already up-to-date Relocation complete. New SMBASE=0x7f7ff800 IEDBASE=0x7fc00000 Writing SMRR. base = 0x7f800006, mask=0xff800800 Writing SMRR. base = 0x7f800006, mask=0xff800800 Relocation complete. Relocation complete. microcode: Update skipped, already up-to-date Relocation complete. Relocation complete. microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date Relocation complete. microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date Initializing CPU #0 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 Init Broadwell-DE core. CPU #0 initialized Initializing CPU #4 Initializing CPU #5 Initializing CPU #9 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 Init Broadwell-DE core. Init Broadwell-DE core. CPU #5 initialized CPU #9 initialized Initializing CPU #7 Initializing CPU #8 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 Init Broadwell-DE core. Init Broadwell-DE core. CPU #7 initialized Initializing CPU #11 Initializing CPU #10 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 Init Broadwell-DE core. Initializing CPU #3 Initializing CPU #2 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 Init Broadwell-DE core. Init Broadwell-DE core. CPU #3 initialized CPU #2 initialized Initializing CPU #6 Initializing CPU #1 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 Init Broadwell-DE core. Init Broadwell-DE core. CPU #6 initialized CPU #1 initialized Init Broadwell-DE core. CPU #11 initialized CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 CPU #8 initialized Init Broadwell-DE core. CPU #10 initialized CPU #4 initialized bsp_do_flight_plan done after 550 msecs. Enabling SMIs. Locking SMM. CPU_CLUSTER: 0 init finished in 704074 usecs PCI: 00:01.0 init ... DEVTREE: dev or chip_info is NULL Please let me know how to resolve this. Thanks in advance, Omkar L&T Technology Services Ltd www.LTTS.com L&T Technology Services Limited (LTTS) is committed to safeguard your data privacy. For more information to view our commitment towards data privacy under GDPR, please visit the privacy policy on our website www.Ltts.com. This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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Gotta look for the next target after Asus P2B family and i440BX
by Keith Hui Nov. 27, 2019

Nov. 27, 2019

Hi guys, You'll know me as one of the driving forces keeping our i440BX port alive. I did see the two latest patches trying to modernize it and I swear I'll get to it soon, because to be honest, that P2B-LS board has a special place in my mind and is not going away, although it is not seeing much use anymore in practice, which brings me to my next step and question. I have three more modern boards (read: 2012 and they share the same 16GB pair of DDR3L memory modules) with cousins already in the tree but not the exact model. I do know I need to get some info in, but I want to get a take on which one will have the best chance to get a working port first: Lenovo ThinkPad X230 Tablet. This is now my daily machine. Due to some snafu on my part I bought a second unit with only Wacom pen but no touch. The non-tablet X230 is in the tree and there were some notes on tablet hardware. I need to buy a test clip to access the flash chip. Now I wonder if this guy is "already" supported. Asus M4A785TD-M EVO. AM3, family 10h, closest cousin was m4a785t-m, but I don't know where it went now. Asus P8Z77-M. Closest cousin is p8z77-m_pro. Mine is not pro, but I don't know off my head what the difference is. And I get to deal with ME. More info once I get back to my desktop. Keith

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