April 2017 - coreboot - mail.coreboot.org

Lenovo T410 Coreboot
by A. Veek Dec. 14, 2018

Dec. 14, 2018

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Re: [coreboot] No VGA output on e350m1 after flashing. what to do?
by Reiner Luett Sept. 12, 2017

Sept. 12, 2017

Hi! On 30.06.2013 19:28, Christian Weinz wrote: > Maybe I didn't include the VGA option in the make menuconfig process. > How can I solve this problem? You need to add the VGA Option ROM (VGA BIOS -> Add VGA BIOS image). I've extracted it from the UEFI, but you also could use these: http://www.coreboot.org/index.php?title=ASRock_E350M1&oldid=11114 at the end of the page or you also may be able to use the default AMD fam14 (Persimmon) vbios. You will need to agree to the click through: http://wwwd.amd.com/support/vbioslic.nsf/userverify?openform http://www.coreboot.org/AMD_DB-FT1_PERSIMMON It's a pity, that bios_extract didn't work for now. You could use the AMI Aptio EFI MMTool with wine: http://win-lite.de/benutzer/fernando/BIOS-Tools/AMI_Aptio_EFI_MMTool_v4.50.… You need to extract OntarioEFIVbios with PCI ID 1002,9802 as Option ROM. Regards, Reiner --

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Re: [coreboot] How to improve the boot time of the Asus KGPE-D16?
by Daniel Kulesz Aug. 11, 2017

Aug. 11, 2017

Hi, I wanted to try caching of the MRC training data. As described in Timothy's post, I commented the following line: > allow_config_restore = 0; However, I was not able to measure any effects regarding boot time. Does this setting only work with cbfs enabled? And if so, is it necessary to set additionally any cbfs variables? Cheers, Daniel P.S. Hope this time I've set the Reply-To header correctly. > On 03/02/2017 02:17 PM, Paul Menzel wrote: > > Dear Arthur, dear Timothy, > > > > > > Am Donnerstag, den 02.03.2017, 13:38 -0600 schrieb Timothy Pearson: > >> On 03/02/2017 01:30 PM, Arthur Heymans wrote: > >>> Paul Menzel writes: > >>> > >>>> I think most of the time is spent in RAM initialization. > >>>> > >>>> 1. Do board owners with similar amount of memory (independent of the > >>>> board) have similar numbers? > >>>> 2. What are the ways to improve that? Is it possible? For example, can > >>>> the modules be probed in parallel (if that isn?t done already)? > >>>> > >>> > >>> I'm not the right person to answer this since I don't know this > >>> code/hardware that well, but on modern Intel hardware native code uses > >>> the MRC cache to store dram training results and restore those on > >>> next boots (and resume from suspend) if no change in dimm configuration > >>> was detected. > >>> > >>> Maybe something like this could also be applied here (or maybe it's already > >>> the case since it includes code to access spi flash)? > >> > >> Yes, this is already implemented as an option, and it does a fairly > >> decent job of reducing training overhead to almost nothing, > > > > Interesting. What option is that? > > > > Also, besides the file `s3nv` I don?t see anything else in CBFS. Where > > is the training data cached? > > That's it. The cache is mandatory for S3 resume, and optional at boot. > > That being said, the pathways are present but are deactivated due to > historical instability and are not tied in to an nvram variable at this > time. If you want to test, you'll need to edit the source file > "src/northbridge/amd/amdmct/mct_ddr3/mct_d.c"; near line 2730 you'll see > a FIXME comment and this line: > > allow_config_restore = 0; > > Comment that line out and recompile to test. I strongly suggest running > memtest across multiple warm and cold boots (and reboots) before > determining the functionality is stable enough for use.

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Where to buy the KCMA-D8? *brand new*
by Taiidan＠gmx.com June 9, 2017

June 9, 2017

Does anyone know? I have checked everywhere I can't find the accessories for the board family either (TPM etc) I would just get another KGPE-D16 but I want to make a router with one of the 35W C32 "EE" opterons and the retail price is a little cheaper. And does anyone know how much longer they are making the KGPE-D16? I wanna buy more before they stop (I could get arm or power, but I still need x86 to play video games) I suppose it is possible to port to another better available similar board like something from supermicro (H8DGI-way, way better specs, first released 2014) but I have no idea how complex that is.

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Re: [coreboot] Recommended memory for coreboot + ASUS KGPE-D16
by Taiidan＠gmx.com May 9, 2017

May 9, 2017

On 04/30/2017 08:05 AM, BogDan Vatra wrote: > Hi, > > I'd like to build desktop/workstation for my personal use (lots of > compilations + of course gaming on linux) > I bought 2 x 6276 CPUs and a KGPE-D16, eprom programmer, etc. now I'm > looking to buy some RAM. > My goal is to have a quad channel 64Gb and because I looking for a > desktop/workstation I think the best choice will be ECC UDIMMs and not > RDIMMs. > Will coreboot support 8 x 8Gb DDR3 UDIMMs 1600Mhz? If yes, there are > any recommended brands/product series? > If not, then what is the best option for achieving my goal? > > Thanks! > > Yours, > BogDan. > RDIMM's are generally cheaper as ECC UDIMM's are rare, and it doesn't matter what brands or w/e you use AFAIK - I have never had problems with mismatched ebay sticks. If you want to play games on higher settings that can't utilize 16 cores you will have to get a better CPU, like a 6328, 6386SE or 6287SE. Something cool you can do with this too is play yours in a VM like me with an attached graphics card. I would do a 6328 and a 6386SE combo with the first used for games. If you want 1600mhz you need 63xx CPU's I believe.

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Re: [coreboot] Coreboot on the Supermicro H8SCM-F
by Patrick 'P. J.' McDermott May 2, 2017

May 2, 2017

On 2017-04-26 at 15:25, Rene Shuster wrote: > Maybe even FSF-endorsed. Great news! Spread the news. The H8SCM is a nice find, but unfortunately probably not eligible for FSF certification. The board has an old AGP-based Matrox G200eW GPU. In addition to having a non-free VBIOS [1], the GPU has a "WARP Engine" – a RISC coprocessor core with non-free microcode (loaded by Linux [2]) to do triangle setup operations [3]. So, a couple of blobs that would be rather non-trivial to reverse engineer and replace. The board could surely run headless without them, but the FSF most likely wouldn't certify it since users could be tempted to load the blobs to get video output and graphics acceleration. [1]: https://www.coreboot.org/Board:supermicro/h8scm#Extract_VGA_BIOS [2]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/dri… [3]: https://en.wikipedia.org/wiki/Matrox_G200 -- Patrick "P. J." McDermott: http://www.pehjota.net/ Lead Developer, ProteanOS: http://www.proteanos.com/ Founder and CEO, Libiquity: http://www.libiquity.com/

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Recommended memory for coreboot + ASUS KGPE-D16
by BogDan Vatra April 30, 2017

April 30, 2017

Hi, I'd like to build desktop/workstation for my personal use (lots of compilations + of course gaming on linux) I bought 2 x 6276 CPUs and a KGPE-D16, eprom programmer, etc. now I'm looking to buy some RAM. My goal is to have a quad channel 64Gb and because I looking for a desktop/workstation I think the best choice will be ECC UDIMMs and not RDIMMs. Will coreboot support 8 x 8Gb DDR3 UDIMMs 1600Mhz? If yes, there are any recommended brands/product series? If not, then what is the best option for achieving my goal? Thanks! Yours, BogDan.

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Re: [coreboot] Intel ME The Way of the Static Analysis
by Zoran Stojsavljevic April 30, 2017

April 30, 2017

Very good presentation from Dmitry Sklyarov. Despite there are some inaccuracies, the work done by his team on ME 11 is impressive. :-) Here, I am just thinking loud... Interesting... ME 11 has some new HW concepts, introduced by INTEL for SKL onward. Knowing the EGO trips of the leading INTEL people, I would not be surprised to see that ARC/SPARC is actually swapped with quark (shrinked PENTIUM on 22nm), introduced as serious challenge to ARM in IOT space by BK, CEO of INTEL, when BK was just a TMG leader (Y2013). Quark is his beloved baby, crown of his technical career (leading him to be CEO). Actually, quark is pushed into very serious designs all over the place, from 3 years ago, fast forwarded in Time. So quark could be the replacement. AS additional justification for BK's decisions, dated more than 3 years ago. Looking what MINIX3 itself is, it kinda confirms my thoughts: http://www.minix3.org/ *MINIX 3 is a free, open-source, operating system designed to be highly reliable, flexible, and secure. It is based on a tiny microkernel running in kernel mode with the rest of the operating system running as a number of isolated, protected, processes in user mode.* The another interesting fact I did not know is that ME is taking minimum 2x of consecutive 16MB of DRAM (this I new already), but that this DRAM is not accessible by OS, running on CPU. Thus, Since I know that these 32MB of memory are very close to TOM (on the first 4GB of memory), and reserved by the time HECI I/F starts synchronising BIOS and ME engines, by 99.999% users while BIOS executes, but for more Coreboot knowledgeable people right after MRC algorithm is done/executed), it forces me to think that there is another INTEL HW extension, hidden, which assures that this memory is NOT accessible. Or, perhaps, one of variable MTRR definitions is used for this purpose (procedure embedded in BIOS). I need to investigate more on this topic. MINIX3 on the top of quark is viable design. Especially that there is superuser mode, there are discovered UNIX FS definitions (user/group/world permissions on extensions), and modular packages (all modern Linux distros have this concept). And... Notion of ring0 and ring3, introducing additional layer of ME protection (not available by RTOS ThreadX, my best guess). Very interesting presentation, indeed. But I need to watch it several times, to let additional ideas to pop in my mind... ;-) Thank you (Dmitry especially), Zoran On Wed, Apr 26, 2017 at 10:57 PM, Patrick Georgi via coreboot < coreboot(a)coreboot.org> wrote: > Fun tidbit: The ME is running MINIX3 (confirmed by a file in the > Google cache: http://webcache.googleusercontent.com/search? > q=cache:tCcU0NRwTnQJ:ftp://ftp.supermicro.com/CDR-X11-UP_ > 1.10_for_Intel_X11_UP_platform/Intel/ME/Other_ > Licenses/Minix3_License.txt+&cd=1&hl=de&ct=clnk&gl=de&lr=lang_de%7Clang_en > ) > > 2017-04-26 22:47 GMT+02:00 Youness Alaoui <kakaroto(a)kakaroto.homelinux.net > >: > > Thanks for the links. > > This is the article that I had seen : > > http://blog.ptsecurity.com/2017/04/intel-me-way-of-static-analysis.html > > > > > > On Tue, Apr 25, 2017 at 10:38 AM, Shawn <citypw(a)gmail.com> wrote: > >> > >> slide: > >> https://www.troopers.de/downloads/troopers17/TR17_ME11_Static.pdf > >> > >> video: > >> https://www.youtube.com/watch?v=2_aokrfcoUk > >> > >> -- > >> coreboot mailing list: coreboot(a)coreboot.org > >> https://mail.coreboot.org/mailman/listinfo/coreboot > > > > > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > https://mail.coreboot.org/mailman/listinfo/coreboot > > > > -- > Google Germany GmbH, ABC-Str. 19, 20354 Hamburg > Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: > Hamburg > Geschäftsführer: Matthew Scott Sucherman, Paul Terence Manicle > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] Coreboot wiki: what license is the content under?
by Sam Kuper April 29, 2017

April 29, 2017

On 03/04/2017, Sam Kuper <sam.kuper(a)uclmail.net> wrote: > On 03/04/2017, ron minnich <rminnich(a)gmail.com> wrote: >> Could we, please, agree on what the question is; write the question; and >> ask a lawyer, preferably someone involved in the CC license creation in >> the first place? All this interpretation of legalese by coders is bound to >> end badly. Having re-read the emails from Nico Huber and from David Hendricks in this thread, and having also re-read the relevant parts of the FAQ, I now agree with Nico and David about how to interpret CC BY. Even so, I remain in favour of CC BY-SA 3.0 over CC BY, in order to achieve license compatibility with Wikipedia, Stack Exchange, OpenZFS, and various other wikis and technical documentation projects that might want to include content from the coreboot wiki or vice versa. > Here is the email I sent to Creative Commons. It is imperfect, but I > hope will be good enough. [...] Mari from Creative Commons replied to me, offering to check with the Creative Commons legal team whether CC BY 3.0 gives an adapter permission to apply a different license to the work as a whole (as I formerly thought) rather than just to the adapter's contribution (as David and Nico believe). Because there now seems to be unanimity within the mailing list on how to interpret CC BY, getting a lawyer's opinion may be superfluous. However, I would be happy to accept Mari's offer if you or other core coreboot contributors would like me to. Best regards

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Re: [coreboot] Warm reset support in Coreboot
by Idwer Vollering April 28, 2017

April 28, 2017

Do you have access to, or read, the relevant datasheet(s)? http://www.intel.com/Assets/PDF/datasheet/322896.pdf for example appiies to NM10 and describes the bits involved on section 13.7.5 (RST_CNT). 2017-04-28 12:46 GMT+02:00 <Sibi.Rajasekaran(a)dell.com>: > Hi, > > > > Is there a way to do warm reset in Rangeley based systems in Coreboot? > > I tried writing 0x6 to the 0xcf9 interface, but it was a cold reset rather > than a warm reset. > > > > Thanks, > > Sibi > > > > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot

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