May 2016 - coreboot - mail.coreboot.org

Lenovo T410 Coreboot
by A. Veek Dec. 14, 2018

Dec. 14, 2018

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Re: [coreboot] No VGA output on e350m1 after flashing. what to do?
by Reiner Luett Sept. 12, 2017

Sept. 12, 2017

Hi! On 30.06.2013 19:28, Christian Weinz wrote: > Maybe I didn't include the VGA option in the make menuconfig process. > How can I solve this problem? You need to add the VGA Option ROM (VGA BIOS -> Add VGA BIOS image). I've extracted it from the UEFI, but you also could use these: http://www.coreboot.org/index.php?title=ASRock_E350M1&oldid=11114 at the end of the page or you also may be able to use the default AMD fam14 (Persimmon) vbios. You will need to agree to the click through: http://wwwd.amd.com/support/vbioslic.nsf/userverify?openform http://www.coreboot.org/AMD_DB-FT1_PERSIMMON It's a pity, that bios_extract didn't work for now. You could use the AMI Aptio EFI MMTool with wine: http://win-lite.de/benutzer/fernando/BIOS-Tools/AMI_Aptio_EFI_MMTool_v4.50.… You need to extract OntarioEFIVbios with PCI ID 1002,9802 as Option ROM. Regards, Reiner --

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ASUS KCMA-D8 workstation board port offer
by Timothy Pearson Jan. 20, 2017

Jan. 20, 2017

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 All, After reviewing some of the comments on the ASUS KGPE-D16 being essentially too large of a system and too expensive for many people, and the fact that modern, blob-free systems are not really available in the mid-range arena, Raptor Engineering would like to offer to create a native initalization blob-free port for the ASUS KCMA-D8, which is essentially the KGPE-D16's ATX-compatible "little brother". We would be asking $15,000 for the port, including upstreaming to the master coreboot tree. We already have extensive experience with these Family 10h/15h boards, and would be able to create a port of similar quality to the existing KGPE-D16 source in terms of both code quality and overall functionality. If this is something you might be interested in please let me know. We are able to accept multiple payments from various sources for the same project (within limits), so if this is something your local Linux groups or similar might be interested in we should be able to keep the cost on any one individual or organization to a reasonable level. Thank you for your consideration, - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) http://www.raptorengineeringinc.com -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQEcBAEBAgAGBQJWQROpAAoJEK+E3vEXDOFbR2cH/3FTqGFH+cU/HVrBUPcoKjii h9OC7SGeXdyoLZvob/YayG+g47Yppkg2um4pAC7dmGl/OXtkGh13hlsrQ8BNiYcz g0kQUdNKYh9dmBC3YnlxU6a7psh473TdyuLILrl7/8WgI8DZnRtjy62Oo5k6XAKW jfYb/bGC8I3tArYrgQDmFxz2dOejuTZit56I+mbWNtvbuQov2BDmrPPMLRuEvG3M QHCAo/Pjaajzl4rmtrgu0GHcxHsgAnJcnrcPkFYeSDKt7QxSTNOB6NqhcnYdh1SY RiA5Z/3enuDs+XNhS+6qMeKOcrEuf+Ccs7sGsgq5tWm20JA+bBoByvrXhHqVUxU= =DKfR -----END PGP SIGNATURE-----

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Porting coreboot on ASUS M5A78L-M LX3
by Алексей Боровиков Aug. 15, 2016

Aug. 15, 2016

Hi! I need help to porting coreboot Asus M4a785m on Asus M5a78l-m lx3. I'm trying to porting coreboot on the motherboard Asus M5a78l-m lx3 (rs780l/sb710). I cannot find documentation for the northbridge rs780l. My configuration: cpu - Athlon 2 x2 220 (K10), memory - 2 + 2 Gb DDR3, video - Asus GT520, sata segate hdd 500Gb, sata asus dvd-rw. I have a positive result for the configuration with memory 2Gb and external video card Asus GT520. I can load Linux kernel 2.6. But, i have two problems: 1. I cannot load coreboot with internal graphics card (hd 3000). Coreboot stops loading and to print on console "Calling option ROM…". May be the problems with gfx configuration? 2. I cannot run Linux with memory 4Gb. Coreboot is loading, SeaBios is loading too, but Linux stop load on usb3-2 and ata1 setup. May be the problems with memory map? Please, help me. I can provide all the necessary information from the log coreboot, SeaBios and Linux. Thanks.

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Re: [coreboot] Microcode problem with Braswell CPU
by Alexander Böcken July 25, 2016

July 25, 2016

Hello Zoran, again, thanks for your clues to this problem. I don't think post code 0x52 is about memory configuration. The post code appears when I call TempRamInit which is supposed to enable Cache-as-RAM. Real memory is initialized at a later call to FspMemoryInit. coreboot supplies the location of the microcode and a cachable region to TempRamInit. Additionally, there are some settings that can be applied to the FSP image with Intel's Binary Configuration Tool. I don't know if these are used during TempRamInit, but I'll try and fiddle around with them. I agree, it would be helpful to have a list of post codes that can be output by FSP. Otherwise it's all speculation as what is wrong. Regards, Alex

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Re: [coreboot] Where is the first instrucion?
by Alex G. July 25, 2016

July 25, 2016

On 01/10/2016 10:23 AM, ron minnich wrote: > One thing I think you'd enjoy doing is building the qemu target, setting > up qemu with gdb, and just watching what happens, instruction by > instruction, as the system boots. One exercise I liked doing was to rewrite the entire boot flow, from reset vector to protected mode entry. Tested on qemu, put it on hardware, nothing burned. Alex > ron > > On Sun, Jan 10, 2016 at 3:28 AM Rafael Machado > <rafaelrodrigues.machado(a)gmail.com > <mailto:rafaelrodrigues.machado@gmail.com>> wrote: > > Hi Peter and Rudolf. > Thanks for the answers and tips. They are realy helpfull ! > I'll take a look. > > Rafael R. Machado > > > Em Sáb, 9 de jan de 2016 17:19, Rudolf Marek <r.marek(a)assembler.cz > <mailto:r.marek@assembler.cz>> escreveu: > > Hi, > > I guess your question is more general than the coreboot related > right? > > If you have a firmware image dump of the flash (not the file you > download from > board vendor) then yes, first location to be executed is the > instruction located > 16 bytes before end of the image. > > In coreboot see in build/ bootblock_inc.S which also has > reset16.inc and > entry16.inc which is a real start. Consult the Intel or AMD > manual to see the > CPU state after reset. The CPU starts in real mode, but CS base > is shifted to > last 64KB before end of 4GB address space. In general your CPU > starts in > compatible mode with 8086 manufactured in 1978. > > Thanks > Rudolf > > -- > coreboot mailing list: coreboot(a)coreboot.org > <mailto:coreboot@coreboot.org> > http://www.coreboot.org/mailman/listinfo/coreboot > > >

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How to change the Core input voltage setting?
by 김유석 책임연구원 June 6, 2016

June 6, 2016

Dear Sir. My HW enginner required to me. that Change the setting of "Core input voltage". But, I don't know everything this one. Because x86 platform is first time of my develop life. Anyway, I'm try to find the something on coreboot source code. But, still unknow. So, I need a start point or key point that Initial code for "Core input voltage". Please advise to me. Thank you.

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Add bootorder file for Seabios
by Naveed Ghori June 5, 2016

June 5, 2016

What is the easiest way to do this. Is there already a way to do it cleanly and have the bootorder file in the mainboard area or will I have to add a patch to add it on to CBFS. Regards, Naveed Ghori | Lead Firmware & Driver Engineer DTI Group Ltd | Transit Security & Surveillance 31 Affleck Road, Perth Airport, Western Australia 6105, AU P +61 8 9373 2905,151 | F +61 8 9479 1190 | naveed.ghori(a)dti.com.au Visit our website www.dti.com.au<http://www.dti.com.au> The information contained in this email is confidential. If you receive this email in error, please inform DTI Group Ltd via the above contact details. If you are not the intended recipient, you may not use or disclose the information contained in this email or attachments.

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SeaBIOS with native graphics initialization?
by Piotr Kubaj June 2, 2016

June 2, 2016

Hi all, I'm currently running Libreboot 20150518 on ThinkPad X200, but I'd like to switch to Coreboot (the newest stable version, 4.4). The reason is that Libreboot seems to provide only one configuration and its build system seems difficult to understand in comparison to Coreboot. I'd like to use SeaBIOS (as opposed to Libreboot's GRUB) as payload - I also would like to have coreinfo, memtest and nvramcui so that it all provides kind of BIOS-like menu. Is that possible using native graphics initialization without vgabios? There are some recent references that it's possible. I'm asking because, although I have flashing equipment (I've flashed my X200 myself), the flashing took a lot of time, because of too long wires, interferences from PSU etc. I don't want to be forced to flash it again, so I want to be absolutely sure before I switch.

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Re: [coreboot] 16GB dimm on Sandy/Ivy Bridge status
by Patrick Rudolph June 1, 2016

June 1, 2016

Hi Iru, >From T420 manual [1]: "Memory: Up to 8GB DDR3 - 1333MHz (2 DIMM Slots)" While it seems possible to use 16GB (2x 8GB), it isn't possible to use 16GB DIMMs. I haven't tested by myself, but it seems like a hardware limitation. Please provide raminit logs, just to make sure. Regards, Patrick [1] http://www.lenovo.com/shop/americas/content/pdf/notebooks/ThinkPad/t-series… On 2016-05-31 05:04 AM, Iru Cai wrote: > Hi, > > I'm tesing to see if the coreboot Sandy/Ivy MRC supports 16GB DIMMs. > Here's my result. > > I'm using a MT16KTF2G64HZ-1G6A1[1]. My machine is Lenovo T420 with > i7-3630QM. With this module inserted (I've tested 16G+0 and 16G+8G), > the system can light up, but it'll then get crashed. > - with GRUB2 payload, it'll crash after the payload loads > - with SeaBIOS payload with proprietary VGABIOS, I can see the prompt, > and can boot to a GRUB or syslinux loader on my USB stick, but when I > try to boot a system, it get crashed. If I boot to Memtest86+ on my > USB stick, the system will crash when memtest starts to test the > memory. > > And another thing I can see is, the first boot can boot to payload, > but the second boot will fail. I think it's caused by the MRC cache. > > I'm still wondering if Sandy/Ivy northbridge can support 16GB DIMMs. > I'll give a more detailed EHCI debug output later. According to [2], I > think the incompatibility is an MRC issue instead of hardware > incompatibility. > > [1] > https://www.micron.com/parts/modules/ddr3-sdram/mt16ktf2g64hz-1g6?pc={E1D8F… > [2] > http://www.intelligentmemory.com/fileadmin/download/compatibilitylist.pdf > > Iru.

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