February 2016 - coreboot - mail.coreboot.org

Lenovo T410 Coreboot
by A. Veek Dec. 14, 2018

Dec. 14, 2018

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Re: [coreboot] No VGA output on e350m1 after flashing. what to do?
by Reiner Luett Sept. 12, 2017

Sept. 12, 2017

Hi! On 30.06.2013 19:28, Christian Weinz wrote: > Maybe I didn't include the VGA option in the make menuconfig process. > How can I solve this problem? You need to add the VGA Option ROM (VGA BIOS -> Add VGA BIOS image). I've extracted it from the UEFI, but you also could use these: http://www.coreboot.org/index.php?title=ASRock_E350M1&oldid=11114 at the end of the page or you also may be able to use the default AMD fam14 (Persimmon) vbios. You will need to agree to the click through: http://wwwd.amd.com/support/vbioslic.nsf/userverify?openform http://www.coreboot.org/AMD_DB-FT1_PERSIMMON It's a pity, that bios_extract didn't work for now. You could use the AMI Aptio EFI MMTool with wine: http://win-lite.de/benutzer/fernando/BIOS-Tools/AMI_Aptio_EFI_MMTool_v4.50.… You need to extract OntarioEFIVbios with PCI ID 1002,9802 as Option ROM. Regards, Reiner --

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ASUS KCMA-D8 workstation board port offer
by Timothy Pearson Jan. 20, 2017

Jan. 20, 2017

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 All, After reviewing some of the comments on the ASUS KGPE-D16 being essentially too large of a system and too expensive for many people, and the fact that modern, blob-free systems are not really available in the mid-range arena, Raptor Engineering would like to offer to create a native initalization blob-free port for the ASUS KCMA-D8, which is essentially the KGPE-D16's ATX-compatible "little brother". We would be asking $15,000 for the port, including upstreaming to the master coreboot tree. We already have extensive experience with these Family 10h/15h boards, and would be able to create a port of similar quality to the existing KGPE-D16 source in terms of both code quality and overall functionality. If this is something you might be interested in please let me know. We are able to accept multiple payments from various sources for the same project (within limits), so if this is something your local Linux groups or similar might be interested in we should be able to keep the cost on any one individual or organization to a reasonable level. Thank you for your consideration, - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) http://www.raptorengineeringinc.com -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQEcBAEBAgAGBQJWQROpAAoJEK+E3vEXDOFbR2cH/3FTqGFH+cU/HVrBUPcoKjii h9OC7SGeXdyoLZvob/YayG+g47Yppkg2um4pAC7dmGl/OXtkGh13hlsrQ8BNiYcz g0kQUdNKYh9dmBC3YnlxU6a7psh473TdyuLILrl7/8WgI8DZnRtjy62Oo5k6XAKW jfYb/bGC8I3tArYrgQDmFxz2dOejuTZit56I+mbWNtvbuQov2BDmrPPMLRuEvG3M QHCAo/Pjaajzl4rmtrgu0GHcxHsgAnJcnrcPkFYeSDKt7QxSTNOB6NqhcnYdh1SY RiA5Z/3enuDs+XNhS+6qMeKOcrEuf+Ccs7sGsgq5tWm20JA+bBoByvrXhHqVUxU= =DKfR -----END PGP SIGNATURE-----

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Re: [coreboot] Where is the first instrucion?
by Alex G. July 25, 2016

July 25, 2016

On 01/10/2016 10:23 AM, ron minnich wrote: > One thing I think you'd enjoy doing is building the qemu target, setting > up qemu with gdb, and just watching what happens, instruction by > instruction, as the system boots. One exercise I liked doing was to rewrite the entire boot flow, from reset vector to protected mode entry. Tested on qemu, put it on hardware, nothing burned. Alex > ron > > On Sun, Jan 10, 2016 at 3:28 AM Rafael Machado > <rafaelrodrigues.machado(a)gmail.com > <mailto:rafaelrodrigues.machado@gmail.com>> wrote: > > Hi Peter and Rudolf. > Thanks for the answers and tips. They are realy helpfull ! > I'll take a look. > > Rafael R. Machado > > > Em Sáb, 9 de jan de 2016 17:19, Rudolf Marek <r.marek(a)assembler.cz > <mailto:r.marek@assembler.cz>> escreveu: > > Hi, > > I guess your question is more general than the coreboot related > right? > > If you have a firmware image dump of the flash (not the file you > download from > board vendor) then yes, first location to be executed is the > instruction located > 16 bytes before end of the image. > > In coreboot see in build/ bootblock_inc.S which also has > reset16.inc and > entry16.inc which is a real start. Consult the Intel or AMD > manual to see the > CPU state after reset. The CPU starts in real mode, but CS base > is shifted to > last 64KB before end of 4GB address space. In general your CPU > starts in > compatible mode with 8086 manufactured in 1978. > > Thanks > Rudolf > > -- > coreboot mailing list: coreboot(a)coreboot.org > <mailto:coreboot@coreboot.org> > http://www.coreboot.org/mailman/listinfo/coreboot > > >

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Re: [coreboot] On Intel Boot Guard
by Alexander Couzens April 15, 2016

April 15, 2016

Hi Iru, we aren't still sure which boards use Intel Boot Guard and which doesn't use it. But we expect most board use it, because it's "recommended" by intel - as we dont recommend it. Also there isn't yet a test script for Intel Boot Guard. Can you post a link to that forum post? I would like to look into a x240 flash image. If you have such board it would be nice if you can send me a copy of the flash image via private mail. Cheers, lynxis -- Alexander Couzens mail: lynxis(a)fe80.eu jabber: lynxis(a)jabber.ccc.de mobile: +4915123277221

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Target candidate: Dell Latitude E4300
by persmule March 17, 2016

March 17, 2016

Hi, I have found a potential target Dell Latitude E4300 for libreboot (and coreboot), for its similarity with Thinkpad X200S and X200T. This one uses GS45, with (S)P9X00 family cpu (its sibling model e4200 uses SU family cpu), like the X200S and X200T which is supported in coreboot (and libreboot) with gerrit's patch. And not like Latitude E6400, this model uses DDR3 RAM (more like X200S/T). This model uses SMSC FDC37M602, which is already supported with coreboot. Because the succeed for GS45 in X200S/T, I think it's a good porting target for coreboot and libreboot. I managed to get the firmware layout with flashrom(1), which is attached with stdout of flashrom. May they be useful to you. What does the community think about this? Worth it? And, waiting for certain goods' arrival, I plan to disassemble my E4300 to cleanse its cooler and heatsink, and siphon out the whole BIOS image, which will be sent to you soon, too. Regards, Persmule.

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On Memtest86+ change sets up for review
by Paul Menzel Feb. 29, 2016

Feb. 29, 2016

Dear coreboot folks, There are patches up for review [1], creating a new memtest86plus project [2]. Martin, as you are the author, could you please give a little bit more information? The last Memtest86+ release seems to be from 2013, and looking at your change sets there are a lot of patches applied from the distributions. So there is not much maintenance going on upstream. I could not find a mailing list, but there is some activity in the forum [4]. I am interested in what the goal is? Do we want to be the new Memtest86+ upstream? Have you talked to the Memtest86+ folks, so that they are informed? Will they hand over the domain for example? Thanks, Paul [1] https://review.coreboot.org/#/q/project:memtest86plus [2] https://review.coreboot.org/#/c/13818/ [3] http://www.memtest.org/ [4] http://forum.canardpc.com/forums/73-Memtest86-Official-forum

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Fwd: Aspirant for GSOC 2016 with coreboot for ARM64 qemu port
by Saket Sinha Feb. 29, 2016

Feb. 29, 2016

Hi, Congratulations to the coreboot team for selection in GSOC 2016. I am looking forward to participate in GSOC 2016 with coreboot for ARM64 qemu port. I request you to guide me as where to start with to prepare for this project. Regards, Saket Sinha ---------- Forwarded message ---------- From: Saket Sinha <saket.sinha89(a)gmail.com> Date: Fri, Feb 12, 2016 at 10:24 AM Subject: Aspirant for GSOC 2016 with coreboot for ARM64 qemu port To: adurbin(a)chromium.org, coreboot(a)coreboot.org Cc: Patrick Georgi <pgeorgi(a)google.com> Hi, I think this is early for this but I am looking forward to participate in GSOC 2016 with coreboot for ARM64 qemu port. This is to discuss the idea further. I guess the project was a part of last year GSOC as well so we already have some base-work to start with. I request you to guide me as where to start with to prepare for this project. Regards, Saket Sinha

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coreboot candidate: Dell Latitude E4300
by persmule Feb. 27, 2016

Feb. 27, 2016

Hi, This is GS45, with (S)P9X00 family cpu (its sibling model e4200 uses SU family cpu), like the X200S and X200T which is supported in coreboot (and libreboot) with gerrit's patch. And not like Latitude E6400, this model uses DDR3 RAM (more like X200S/T). This model may be better than X200S/T, for it (at least mine) even lacks a ME. Because the succeed for GS45 in X200S/T, I think it's a good porting target for coreboot. It would also be an instant libreboot port, once in coreboot, being GS45. What does the community think about this? Worth it? Regards, Persmule.

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Re: [coreboot] Building ChromeOS from source
by Gregg Levine Feb. 27, 2016

Feb. 27, 2016

Hello! As with everything else concerning a (presumably) open source project, I'm considering it. Still looking for a reasonably good reason. I believe given that interesting problem, I believe I might take a wack at it. ----- Gregg C Levine gregg.drwho8(a)gmail.com "This signature fought the Time Wars, time and again." On Fri, Feb 26, 2016 at 11:11 PM, ron minnich <rminnich(a)gmail.com> wrote: > Do you want to build Chrome from source to? > > I have google doc that explains how building chromeos from source used to > work. Chromeos is quite a monster to build, and my google doc is out of date > (something changed), but it's possible to build a lot from source. Just have > a reasonably powerful CPU handy. > > https://docs.google.com/document/d/1WQnfloMbcR798Lk-iYPbvZt-wplW83IYyCf7SYy… > > One of the side goals of my u-root project is to create a root file system > that is small and simple and might replace chromeos someday. In u-root, > programs are dynamically compiled when you run them, so the root is mostly > source. > > ron > > On Fri, Feb 26, 2016 at 6:52 PM Gregg Levine <gregg.drwho8(a)gmail.com> wrote: >> >> Hello! >> Let us suppose I want to build from source ChromeOS. What is involved >> in doing that? And the reason some of you will ask, it concerns the >> previous discussion on building a ROM image for a particular Intel >> chipset. >> >> If possible I might be able to obtain a board that's reasonably close >> to that chipset. >> ----- >> Gregg C Levine gregg.drwho8(a)gmail.com >> "This signature fought the Time Wars, time and again." >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot

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